JPS61166651A - Replacing system for buffer memory - Google Patents

Abstract

PURPOSE:To improve the using efficiency of the 2nd buffer memory by securing a certain type of correlation between both replacement actions of the 1st and 2nd buffer memories. CONSTITUTION:A buffer memory LBS of a high speed and small capacity is provided together with a buffer memory MBS of a medium speed and large capacity. When a certain block is replaced for the memory LBS, the address information on a subject block is transmitted to the memory MBS. Here a comparator 38' is set to the memory MBS to detect whether a certain one of blocks to be replaced in the memory MBS includes a transmitted address or not. Then a block to be replaced is decided in the memory MBS. In this case, the block sent from the memory LBS is replaced if it is detected by the comparator 38'. While a block to be replaced is decided by an LRU memory 35 when no block sent from the memory LBS is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a second buffer memory (MBS) having a copy of a portion of a main memory;
a first buffer memory (LBS) having a copy of a part of the main storage (MBS) or a copy of a part of the main storage not in the second buffer memory (MBS); In computer systems,
This relates to the second buffer memory (MBS) glue placement method.

In recent large-scale computer systems, a small capacity but high-speed buffer memory (BS) is provided between the central processing unit (CPU) and the main storage unit (MSU), and the average Generally, a method is used to shorten the access time.

However, with recent remarkable advances in hardware technology, the arithmetic units of central processing units (CPUs) are becoming faster and faster, but the capacity of main storage units (MSUs) is also becoming larger. Currently, the speed cannot be increased much.

Therefore, the buffer memory (BS) has been made faster and has a larger capacity to match the speed of the arithmetic unit, but compared to the larger capacity of the main memory (MS[I), The gap is in a situation where it cannot be shortened.

As a means to solve the above problem, a medium-speed, large-capacity buffer memory (BS) is used as a second buffer memory (MB
S) is the high-speed, small-capacity buffer memory (BS) mentioned above.
) (this is called the first buffer memory (LBS)) and the main storage unit (MSU), so-called 2
BACKGROUND ART Hierarchical buffer memory systems are known. below,
These will be referred to as the second BS and the first BS, respectively.

In such a buffer memory system, the problem is replacement in the second BS.

In particular, when the block size of the second BS>the block size of the first BS and the difference is an integral multiple, the replacement blocks of the first BS and the second BS are determined independently of each other. and from the main storage unit (MSU), the second B
There is a problem in that the data moved into S is replaced at the second BS before it is used up (specifically, it is not transferred to the first BS).

Therefore, the first BS replacement operation and 1. 2nd BS
By creating a certain correlation between the replacement operation and the replacement operation, an effective replacement method can be expected.

[Conventional technology]

First, the concept of a computer system including a general two-layer buffer memory (BS) will be explained with reference to FIG.

In this figure, 1 is an arithmetic unit, 2 is a first BS (LB
S), 3 is the second BS (MBS), 4 is the main storage (
MSU).

In such a computer system, the first BS (LB
S) When the data required by the arithmetic unit 1 does not exist in both the main storage unit (MSU) 1 and the second BS (MBS) 2, the data required by the arithmetic unit 1 is stored in the first BS (LBS) 1 and 1 from the main storage unit (MSU) 4.
It operates to transfer data in corresponding blocks to both of the second BS (MBS) 2, and to transfer necessary data from the first BS (LBS) 2 to the arithmetic unit 1.

If data does not exist in the first BS (LBS) 2 but data exists in the second BS (MBS) 3, the data block is transferred from the second BS (MBS) 3 to the first BS (MBS) 3. The block is transferred to the first BS (LBS) 2, and necessary data is further transferred from the first BS (LBS) 2 to the arithmetic unit 1. .

Figure 4 shows a two-layer buffer memory and a main memory (M
An example of the configuration of a three-layer memory system consisting of SU) is shown.

In this configuration example, the plotter size of the first BS (LBS) 2 is 32 bytes, and the plotter size of the second BS (MBS) 3 is four times the block size of the first BS (LBS) 2. It is a 128 byte block,
First BS (LBS) 2. Both the second BS 01BS) have four levels of association (way number): way 0 to way 3.

If the first BS (LBS) 2. Second BS (gate BS
) 3, when the required data does not exist, the first BS (LBS) 21J<request L7trt432
z'(-()(7)F-91>'・1...Block transferred from main storage unit (MSU) 4 and registered in both first BS (LBS) 2. second BSCMBS) 3. Ru. At this time, the way to be registered is the first B
S (LBS)2. The three second BSs (MBS) may be the same way, or may be different ways.

Next, the remaining 96 bytes of the 128-byte block of the second BS (MBS) 3 are divided into 32 bytes x 3 blocks and transferred from the main storage unit (MSU) 4 to the second BS (MBS) 3. (MBS) Registered in 3.

Also, if there is no data in the first BS (LBS) 2 and data exists in the second BS (MBS) 3, the 32-byte data requested by the first BS (LBS) 2 is read from the second BS (MBS) 3 and transferred to the first BS (LBS) 2.

In such a conventional two-layer buffer memory system, when the above data transfer (move-in) is performed,
The so-called LRU method, which removes the oldest data block,
First BS (LBS) 2. Second BS (LBS)
3, each did it independently.

[Problem that the invention seeks to solve]

Therefore, in the conventional system, for example, the first BS (LB
S) The block replaced from 2 is transferred to the second BS.
(MBS) 3, even if the block is included in the second BS (MBS) 3, the block may not be replaced from the second BS (MBS) 3, or conversely, it may not be moved in from the main storage unit (MSU) 4 to the second BS (MBS) 3. The second BS (MBS) 3 may replace the data blocks before the first BS (LBS) 2 uses them up, and the usage efficiency of the second BS (MBS) 3 may be reduced. It often got worse.

In view of the above-mentioned drawbacks of the conventional art, the present invention focuses on the locality of address distribution during program execution, and takes advantage of the feature that accesses to a storage device occur sequentially to some extent in time to a certain continuous area. Considering, the first BS
(LBS) Replace operation in 2 and second BS
It is an object of the present invention to provide a replacement method that improves the efficiency of use in a second BS (MBS) 3 by providing a certain correlation to the replacement operations in the second BS (MBS) 3.

[Means for solving problems]

The purpose of this is: ■ The contents of each sub-block obtained by dividing the block of 8x8' sofa memory into the block size of the first buffer memory (LBS) are stored in the second buffer memory (MBS). The n-bit copy bits indicating that they have been transferred to the second buffer memory (M
A second buffer memory (
When it becomes necessary to replace the block (MBS), the copy bits are referred to and the block is If there is any indication that the contents of all sub-blocks have been transferred to the first buffer memory (LBS), control is given so that that block is preferentially targeted for replacement.

■When replacing a certain block from the first buffer memory (LBS), a means is provided for transmitting the address information of the block to be replaced to the second buffer memory (MBS), and the second buffer memory (MBS)
) also has no data, and the second buffer memory (MB
Any one of the blocks to be replaced in S)
a comparator for detecting whether or not one block contains the transmitted address;
When determining a replacement block for the first buffer memory (LBS), if the comparator detects a block including the address transmitted from the first buffer memory (LBS), replace the block and replace the transmitted address. If a block containing the address that was previously replaced is not detected, the block to be replaced is determined using the LRU method.

This is achieved by the replacement method in the buffer memory of the present invention.

[Effect]

That is, according to the present invention, the block size of the second (7) BS (MBS) is equal to 1
A two-layer buffer whose block size is an integer multiple of the block size of the BS (LBS)
tf: Total ■'Elbow"96 1. (1) From the second BS (MBS) to the first BS (LB
A copy memory is provided to store the copied sub-blocks in S), and when replacement is required in the second BS (MBS), the block with all the sub-blocks copied to the first BS (LBS) is provided. Replace with priority.

(2) Memorize the replacement address (subblock address) in the first BS (LBS), and when replacement is required in the second BS (MBS), if there is a block containing the above subblock, Replace the block with priority.

(3m, if the condition (2) is not met, the known LR
Replace the block selected by the U method.

Therefore, the second BS (?IBS)
This has the effect of improving the usage efficiency of the computer system and improving the performance of the entire computer system.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 1, (a) is, for example, the second BS (M
BS) 3 shows an example of the configuration of the copy bit provided in the tag section, and (b) shows an example of the configuration of the copy bit provided in the tag part of the second BS (M
BS) 3 is shown.

First, referring to (a) in this figure, the operation for copy bits, which is the main focus of the present invention, will be explained.

In this figure (a), 320 is the second BS (MBS)
The number of sub-blocks in the program of the second BS (MBS) 3, that is, 4 bits, is specified for each entry by the copy bit provided in each entry of the tag section 32 in It is provided. 330 is the second BS (
One block (128 bytes) of MBS) 3 is shown, and each time one subblock (32 bytes) is transferred for one block 220 of first BS (LBS) 2,
The 1-bit node of the corresponding copy bit 320 is set to 1', and this figure shows that three sub-blocks have been transferred to the first BS (LBS) 2. .

Next, the replace operation according to the present invention will be explained with reference to (b).

First, the address of the requested data is set in the address register (hereinafter referred to as AR) 31, and at its lower address, the tag section (TAG) 32. data section 33,
LRII memory 35 is referenced.

Next, the upper address in the tag section (TAG) 32.

The comparator (C) 34 compares the upper address of the AR 31 and detects through a NOR circuit (NOR) 38 that the desired data does not exist in the second BS (MBS) 3 (that is, line missing). Then, in order to move in the block from the main storage unit (MSU) (not shown), the address of AR31 is changed to MSAR3.
1' to the main storage unit (MSU),
After a certain period of time, the move-in data is transferred to the second 85 (M
It will be forwarded to BS) 3.

It is necessary to determine a replacement block as the writing destination of the move-in data, but normally, from a total of four blocks determined for each way based on the lower address, the oldest block in the LRU memory 35 is replaced. Selected as a block.

In the present invention, in addition to the information from the LR1l memory 35, an AND circuit (A
The feature is that the information from ND) 36 is used to determine the replacement plotter.

That is, among the outputs ACPYO to 3 of the AND circuit (AND) 36 for each way (here, 0 to 3 correspond to ways O to 3), the block (way) "1' has already been fully loaded. Since the contents have been transferred to the first BS (LBS) 2, this way is preferentially set as the target block for replacement.

In other words, for each way that is a replacement candidate.

Out of the total 4 blocks, the corresponding ^cpyo~3 “
If only one block is 1', that block is to be replaced regardless of the information from the LRU memory 35.

If PYO~3 is set to A corresponding to each way,
If there are a plurality of I (blocks (ways)), the oldest block is selected for replacement based on the information from the LRU memory 35.

Therefore, if there is no block that is 1'' in the corresponding ^CPYO~3, the oldest block is targeted for replacement based on the information from the LRυ memory 35 as before.

The table below shows that when the information in the LRυ memory 35 indicates that the information in the LRυ memory 35 is used in the order of way 06 = way 1c = way 26 = way 3, the replacement determination circuit 37 This shows the replacement block selected in .

As mentioned above, according to the present invention, the second BS (MBS) 3
By replacing unnecessary blocks with priority, the hint rate can be improved and the capacity of the memory system can be improved.

Next, two other embodiments of the present invention will be described with reference to FIG. First, the general operation will be explained.

A tag section (TAG) 22.32 is provided to detect in which way of the buffer memory the requested data address exists.

That is, the lower address of the requested data address is the tag part (T
AG) 22. Address register (LBAR) as the access address of 32 21. (MBAR) 31
The circuit (C) reads out the entries of ways O to 3 at the same time based on the lower address, and compares the registered address with the higher address of the requested data address.
24.34, and if there is a match, it is recognized that the desired data exists in the buffer memory. Which way has data is determined by the old T/N0N-HIT detection circuit-128', 1(IT/N0N-[T detection circuit-238
', a way select signal is sent to the data section 23, etc., and the corresponding data is read out.

In the LRU memory 25.35, contents indicating which way among ways 0 to 3 will be replaced next are registered in a pattern corresponding to each tag part (TAG) access address. There is.

When the buffer memory is accessed and the desired data exists (HIT), the contents of the LRU memory are updated depending on which way did the IIT, and at that point, the oldest used contents are It is controlled so that it becomes the way to replace it.

The desired data does not exist in the above operation (NON-HIT)
), the patterned information is read from the LRU memory 25.35 and the way to be replaced is set to LR.
This is determined by the U determining circuit 127' and the LRU determining circuit 237''. The address used to access the LRU memory 25.35 is the same as the address used to access the tag section (TAG) 22.32.

Next, the first BS (LBS) 2. Second BS (MBS
) There is no data in both 3, and the address corresponding to the lock is the 2nd BS (MBS).
Way 0 of the block address to be replaced with 3
The operation when any of the items 3 to 3 is included will be described below.

(2) If there is no data in the first BS (LBS) 2, it is assumed that the replacement block is determined by the LRU determination circuit 127 to be "way 3", for example.

■ Address of LBAR21 is second BS (MBS)
It is set in MBAR31 of 3, and its tag part (TAG)
32 are accessed. At the same time, the first BS (LBS
) 2, the old address corresponding to the above-mentioned replace block (way) 3 is stored in the 1st BS (LBS
) Tag section (TAG) 2 is generated and set based on the address read from way 3 of 22 and the lower address from the LBAR 21 mentioned above.

■ Second BS (MBS) 3 tag section (TAG) 3
The addresses read from ways 0 to 3 of No. 2 are compared with the upper address of MBAR 31 by comparators (MC1 to MC4) 34.

At the same time, the address sent from the PBAR 29 of the first BS (LBS) 2 is also transferred to the ways O to 3 generated by the lower address of the MBAR 31 and the address read from the ways O to 3 of the tag section (TAG) 32. Corresponding address and comparator (PBCI to PBC4) 34'
compared by.

Here, if the HIT/N0N-HIT detection circuit 238'' detects that there is no desired data in the second BS (MBS) 3, the LRU determination at the first BS (LBS) 2 is performed. In the same way, LRU determination circuit-237
However, if a match signal is output from any one of the comparators (PBC1 to PBC4) 34', determination of the replacement block based on the information from the LRU memory 35 is suppressed. The comparator (PBCI to PBC4) 34' functions to set the way that has obtained the -dispersed output as a replacement way in the LRU determination circuit -237°.

If no matching signal is obtained from the comparators (PBCI to PBC4) 34', the LRU central constant rotation circuit 37 determines the way to be replaced based on the information from the LRU memory 35. .

As is clear from the above, in the present invention, the first B
S (LBS) 2. There is no desired data in any of the second BS (MBS) 3, and the old address corresponding to the replacement block in the first BS (LBS) 2 is transferred to the second BS (MBS) 3.
When the replacement target block of S(MBS) 3 is included, the first
BS (LBS) 2 blocks can be replaced, including the 2nd BS (Mis
) It has the characteristic that it can increase the usage efficiency of 3.

〔Effect of the invention〕

As explained above in detail, the replacement method in the buffer memory of the present invention is such that the storage capacity of the first BS (LBS) <the storage capacity of the second BS (BS),
The block size of S (MBS) is the same as that of the first BS (L
In a computer system equipped with a two-layer buffer memory system whose block size is an integer multiple of the block size of fl) the second BS (MBS) to the first BS (LB
A copy memory is provided to store the copied sub-blocks in S), and when replacement is required in the second BS (MBS), the block with all the sub-blocks copied to the first BS (LBS) is provided. Replace with priority.

(2) Memorize the replacement address (subblock address) in the first BS (LBS), and when replacement is required in the second BS (MBS), there is a second block containing the above subblock. , the block is replaced preferentially.

(31 (11, (When the conditions of (21) are not satisfied, the block selected by the known LRt1 method is replaced.

This has the effect of improving the usage efficiency of the second BS (MBS) and improving the performance of the entire computer system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing another embodiment of the present invention. Figure 3 is a diagram showing an example of the configuration of an information processing system equipped with 2111 layers of buffer memory.
- FIG. 4 is a diagram showing an example of the configuration of a three-layer memory system. It is. In the drawings, 1 is an arithmetic unit, 2 is a first BS (LBS)
. 3 is the second BS (MBs), 4 is the main storage unit (MSU)
. 21 is an address register (LBAR). 22 is a tag section (TAG), and 23 is a data section. 24 is a comparator (C, LCI to LC4). 25 is LRU Mesori. 27' is an LRu determination circuit 28' is a HIT/N0N-HIT detection circuit -1°29
is PBAR. 31 is an address register (AR, MBAR). 32 is a tag section (TAG), and 33 is a data section. 34 C comparison H (C, MCI to MC4). 34゛ is a comparator (PBCI to PBC4). 35 is an LRU memory, and 37 is a replacement determination circuit. 37' indicates the LRU determination circuit 2°, and 38° indicates the HIT/N0N-)IIT detection circuit-2°, respectively. to t-tst

Claims (2)

[Claims] (1) In a set associative type buffer memory, if the desired data exists on the first buffer memory (LBS), read the data from the first buffer memory (LBS), and if the data does not exist, read the data from the first buffer memory (LBS). refers to the second buffer memory (MBS), and if there is data in the second buffer memory (MBS), the data is transferred from the second buffer memory (MBS) to the first buffer memory (LB).
When a block of data is transferred to S) and there is no data in the second buffer memory (MBS), the data is transferred from the main memory to the first buffer memory (LBS) and the second buffer memory (MBS). The block size of the second buffer memory (MBS) is n times the block size of the first buffer memory (LBS) (n≧2). In a computer system equipped with a two-layer buffer memory system that uses an LRU method to replace the oldest block, the data replacement algorithm for both buffer memories (MBS) ), an n-bit copy bit indicating that the contents of each sub-block obtained by dividing the block of the buffer memory into the block size of the first buffer memory (LBS) have been transferred to the first buffer memory (LBS). is provided for each block of the second buffer memory (MBS), and the second buffer memory (MBS)
When the need for replacement arises, among the m blocks (m is the number of associative levels of the second buffer memory (MBS)) that are candidates for replacement, the copy bit is referred to and the block is replaced. If there is an indication that the contents of all the sub-blocks have been transferred to the first buffer memory (LBS), control is performed so that that block is preferentially targeted for replacement. Replacement method for buffer memory. (2) In a set associative type buffer memory, if the desired data exists on the first buffer memory (LBS), read the data from the first buffer memory (LBS), and if the data does not exist, read the data from the first buffer memory (LBS). refers to the second buffer memory (MBS), and if there is data in the second buffer memory (MBS), the data is transferred from the second buffer memory (MBS) to the first buffer memory (LB).
When a block of data is transferred to S) and there is no data in the second buffer memory (MBS), the data is transferred from the main memory to the first buffer memory (LBS) and the second buffer memory (MBS). The block size of the second buffer memory (MBS) is n times the block size of the first buffer memory (LBS) (n≧2). In a computer system equipped with a two-layer buffer memory system that uses an LRU method to replace the oldest block, the data replacement algorithm for both buffer memories (BS) is configured such that the first buffer memory (LBS) ), when replacing a certain block, a means is provided for transmitting the address information of the block to be replaced to the second buffer memory (MBS), and if there is no data in the second buffer memory (MBS), The second buffer memory (MBS)
The second buffer memory (M
BS) control circuit, and the second buffer memory (MB
When determining the replacement block of S), if the comparator detects a block including the address transmitted from the first buffer memory (LBS), replace the block and replace the transmitted address. 1. A replacement method in a buffer memory, characterized in that when a block containing an address is not detected, the LRU method is used to determine a block to be replaced.