JPH01309153A - Information processor - Google Patents

Abstract

PURPOSE:To realize the high-speed accesses to the programs and data stored in a ROM via a cache memory by storing the copy of the information stored in the ROM into the cache memory. CONSTITUTION:When a read access is given to a ROM area, the read data received from a ROM is copied to a cache memory. The address area of the ROM is defined as an area to be copied to the cache memory. Thus the read data received from the ROM is copied to the cache memory in case the cache memory has a mishit when a read access is given to the ROM. The copied data can be read out of the cache memory at a high speed without giving any access to the ROM. Thus the access speed is apparently increased to the ROM.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a storage device in an information processing device, and in particular,
The present invention relates to a cache memory control method suitable for a case including a ROM and a cache memory.

[Conventional technology]

2. Description of the Related Art As a means of apparently speeding up data access from a central processing unit (CPU) to a slow, large-capacity main memory, there is a method of using a high-speed, small-capacity cache memory. In this method, the CPU first accesses the memory of the cache memory to which part of the data in the main memory is copied, and accesses the main memory only when the desired data does not exist in the cache memory. . In normal programs, data access has locality, so by copying appropriate data from main memory to cache memory, the CPU only needs to access the high-speed cache memory for most data accesses. I can do it.

FIG. 2 shows an example of the configuration of a direct map method (also referred to as a congle-end method), which is one method of cache memory.

The cache memory 17 is a BS (buffer storage device, Buff) in which a copy of data in the main memory 4 is stored.
er Storage) 3, and an AA (Address Array) 2 in which an address tag, which is information indicating which address in the main memory 4 the data in the BS 3 belongs to, is stored. AA2 and BS3 are addressed by the lower bit part 10 of the address 9 output by the CPU 1. On the other hand, the remaining upper bit part 11 is stored in AA2 as an address tag 12. When the CPUI accesses the memory, the comparator 5 compares the address upper bit part 11 and the address tag 12 read from the AA2.

If the results of the comparison match, it is called a hit, and if they do not match, it is called a miss, and this information is stored in the hit information 13.
is output from the comparator 5 as

If there is a hit during a memory read (hereinafter referred to as a read hit), the data selector 7 selects B based on the hit information 13.
S data 14 is selected and sent to the CPU through the data bus 16.
Send data to I. If there is a miss when reading the memory (hereinafter referred to as a read miss), the data selector 7 selects the main memory data 15 based on the hit information 13, and sends the data to the CPUI via the data bus 16. Furthermore, when a read miss occurs, the main memory data 15 is
It is copied to BS3 through data buffer 8, and the upper bit part 11 of the address is written to AA2 through address buffer 6.

On the other hand, at the time of memory write, the following operation is performed to maintain consistency between the contents of BS3 and the contents of main memory 4. If there is a hit during memory write (hereinafter referred to as a write hit)
, updates the contents of both the BS 3 and the main memory 4. If a miss occurs during memory write (hereinafter referred to as a write miss), only the main memory 4 is updated.

Note that a method of an information processing device using such a cache memory is described in the Journal of the Information Processing Society of Japan V o 1.

21, No. 4 (Apr, 1980) PP332-34
0 “Cache Storage”.

In addition to the main memory, which is the target of copying to the cache memory, the CPUI memory space includes ROM (Read On).
ly Memory）ya 工／○（Input／ 0ut
(put) devices, etc. are usually mapped.

When accessing devices that are not subject to copying, the CPU bypasses the cache memory and directly accesses these devices. For example, in Intel's cache controller 82385, N CA (
An input terminal called "Non-Cachebel Access" is provided, which allows the cache memory to be bypassed.

Regarding the cache controller, see 82385 data sheet 290143-001 published by Intel Corporation in the United States.
．． It is detailed in PP17.

FIG. 3 shows how the cache memory is updated when accessing the copy target area to the cache memory and the area outside the copy target area.

[Problem that the invention seeks to solve]

The ROM stores programs for starting up the system, basic personnel output programs, and the like.

In addition, 1. Normal programs and data are generally accessed from the CPU after being transferred from a magnetic storage device etc. to the main memory, but by storing this information in ROM, this transfer becomes unnecessary. can do. However, in the above conventional technology, the address area of the ROM is not subject to copying to the cache memory, and there is a problem that programs and data on the ROM cannot be accessed at high speed using the cache memory.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus in which an address area of a ROM is used as an area to be copied to a cache memory, and access to the ROM is made apparently faster.

Another object of the present invention is to provide a cache memory updating method that prevents mismatch between the contents of the ROM and the contents of the cache memory to which the contents are copied.

Still another object of the present invention is to provide main memory and R.
An object of the present invention is to provide an information processing device that can copy one or both of OMs to a cache memory.

Still another object of the present invention is to provide a main memory check method that speeds up the main memory check using a cache memory.

[Means for solving problems]

An object of the present invention is to: At the time of read access to a ROM area,
This is accomplished by copying read data from ROM to cache memory.

Another object of the present invention is achieved by not updating the contents of the cache memory or invalidating the contents of the cache memory even if the cache memory is hit during write access to the ROM.

Another object of the present invention is to provide a register for setting an area to be copied to the cache memory, a means for decoding the main memory area, and a means for decoding the ROM area, and the setting value of the register and the result of the decoding are This is achieved by determining whether or not the area is to be copied to the cache memory based on this information.

Another object of the present invention is achieved by not using the main memory area as the area to be copied to the cache memory, but using the ROM area as the area to be copied to the cache memory during checking of the main memory.

[For production]

By setting the address area of the ROM as the area to be copied to the cache memory, if the cache memory misses during read access to the ROM, the data read from the ROM is copied to the cache memory. The copied data can be read from the high-speed cache memory without accessing the ROM.
Access to OM can be made seemingly faster.

In addition, even if the cache memory is set at the time of write access to the ROM area, the contents of the cache memory are not updated, so there is a ROM whose contents do not change even if a write access is performed, and a cache where the contents of the ROM are copied. There will be no content mismatch with the memory. Alternatively, if the cache memory is hit during a write access to the ROM area, by invalidating the contents of the cache memory, the next access to the address to which the write access was made will always be a miss. In the case of a mishit, the ROM is accessed directly, so
The contents of the ROM area do not appear to the CPU to have changed due to write access.

In addition, the register for setting the area to be copied to the cache memory specifies whether the area to be copied to the cache memory is only the main memory area, only the ROM area, or whether the area to be copied to the cache memory is the main memory area or the ROM area. Set whether to use both. On the other hand, means for decoding the main memory area;
The address is decoded by means for decoding the ROM area, and if it is a main memory area or a ROM area, it is determined whether the area is to be copied to the cache memory based on the setting value of the register.

Also, when performing read/write checks on main memory,
The main memory area is not to be copied to the cache memory, and the ROM area in which the check program is stored is to be copied to the cache memory. This allows direct access to the main memory, and allows the check program to access the cache memory at high speed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, as shown in FIG. 4, the CPUI memory space is 16MB CM=2"), of which
The IMB from address OOOH (H at the end stands for HEX and represents a hexadecimal number) to address 0FFFFFH is in the main memory area,
64KB from address FFoOOOH to address FFFFFFH
(K=210) are allocated to each ROM area. FIG. 5 shows a configuration diagram of this embodiment. The main memory area decoder 18 decodes the value at address 9 and
0000H-OFF FFF FH (1') When the main memory area is present, the main memory area signal 19 is activated. The ROM area decoder 2o decodes the value of address 9 and stores the ROM area of FF0OOOH-FFFFFFH.
If the area is the area, the ROM area signal 21 is activated. OR gate 22 connects main memory area signal 19 and RO
If either of the M area signals 21 is active, the copy target area signal 23 is made active. In accordance with the copy-one target area signal 23, the cache memory control unit 24 configures the cache memory 17 as shown in FIG.
Controls updates of A2 and BS3. The feature of this embodiment is that the ROM area is the area to be copied to the cache memory 17.

FIG. 6 is a configuration diagram of a second embodiment of the present invention. The feature of this embodiment is that an AND gate 25 is added to the first embodiment. The AND gate 25 receives the ROM area signal 21 output from the ROM area decoder 20 and the RD signal 27 indicating read access.

AND gate 25 makes ROM area read signal 26 active when both inputs are active.

The OR gate 22 makes the copy target area signal 23 active when either the main memory area signal 19 or the ROM area read signal 26 is active. This results in
In write access to the ROM area, the copy target area signal 23 does not become active. Based on the copy target area signal 23, the cache memory control unit 24
FIG. 1 shows the update of AA2 and BS3 carried out by . As shown in FIG. 1, even if a write access to the ROM area is hit, the contents of BS3 remain unchanged.

Write access maintains consistency with the ROM whose contents do not change.

FIG. 7 is a configuration diagram of a third embodiment of the present invention. A.A.
A V bit 31 indicating the validity of each content of AA2 is added to AA2. The copy target area signal 23 to the cache memory is obtained by inputting the main memory area signal 19 and the ROM area signal 21 to the OR gate 22, as in the first embodiment. On the other hand, the ROM area signal 21 and the WT signal 29 indicating write access are input to the AND gate 28 to obtain the ROM area write signal 30. The cashier memory control unit 24 receives the ROM area write signal 3.
For a write access where 0 is active, the V bit 31 added to the contents of AA2 referenced in the write access is set to a value indicating invalidity. As a result, when the address to which the above write access was performed is read next.

Since the V bit 31 is invalid, it is treated as a miss. In the case of a read miss, the ROM is directly referenced, so the contents of the BS3 that have been updated when there is a hit in the write access are not referenced.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention.

A feature of this embodiment is that, in addition to the second embodiment shown in FIG. 6, a register 32 is provided for setting an area to be copied to the cache memory. The register 32 has an M bit 33 and R bits 3 and 1, which correspond to a main memory area and a ROM area, respectively. The settings for this register 32 are set using the address 9 and data 16 buses.
U1 does it. The value of M bit 33 and the value of R bit 34 are:
They are output as a main memory area enable signal 35 and a ROM area enable signal 36, respectively. When main memory enable signal 35 and main memory area signal 19 are both active, AND gate 37 activates main memory copy signal 3
8 is active. Similarly, when both the ROM area enable signal 36 and the ROM area read signal 26 are active, the AND gate 39 makes the ROM copy signal 4o active. And main memory copy signal 38 and RO
When any of the M copy signals 40 is active, the OR gate 22 makes the copy 1 target area signal 23 active. This allows cache memory references and updates when accessing the main memory area or ROM area.
Each area can be allowed or prohibited independently.

FIG. 9 is a flowchart for performing a memory check of the main memory 4 by the information processing apparatus including the fourth embodiment shown in FIG. First, before checking the memory of the main memory 4, set “O” to the M bit 33 of the register 32.
Set R bit 34 to 111". This causes RO
Only the M area is the area to be copied to the cache memory. Next, a read/write check is performed on the main memory 4.

At this time, since the main memory area is not subject to copying, the main memory 4 can be directly read and written.

Furthermore, by storing the read/write check program in the ROM which is the area to be copied to the cache memory, the program can be referenced quickly and the check of the main memory 4 can be completed in a short time.

The present invention is not limited to the embodiments described above. For example, the addresses of the ROM area and main memory area may not be the addresses shown in the embodiment. Furthermore, the cache memory method is not limited to the direct map method, but may also be a set associative method. Further, the writing method at the time of writing may be either a write-through method or a copy pack method.

〔Effect of the invention〕

According to the present invention, programs and data stored in a ROM can be accessed at high speed using a cache memory.

Furthermore, according to the present invention, even if a write access is made to the ROM area, there is no mismatch between the contents of the ROM and the contents of the cache memory.

Further, according to the present invention, the area to be copied to the cache memory can be easily set or changed to one or both of the ROM area and the main memory area.

Further, according to the present invention, by the program on the ROM,
Main memory check can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the operation in one embodiment of the present invention, and FIG.
3 is an operational diagram of the cache memory, FIG. 4 is a diagram showing a memory map in one embodiment of the present invention, FIG. 5 is a configuration diagram in one embodiment, FIG. Figure 7. FIG. 8 is a block diagram of another embodiment, and FIG. 9 is a flowchart of the main memory check method according to the present invention. 1...CPU, 2...AA, 3...BS, 4...
・Main memory, 9...Address, 17...Cache memory. 18... Main memory area decoder, 20... ROM area decoder, 22... OR gate, 24... Cache memory control unit, 25... Ungate, 27...
RD double signal 29...WT double signal 3 Figure 4 - Figure 5 Figure O

Claims (1)

[Claims] 1. At least a cache memory, a main memory, and R
An information processing device comprising an OM, characterized in that a copy of information stored in the ROM is stored in the cache memory. 2. At least cache memory, main memory, and R
A cache memory control method, in an information processing device comprising an OM, characterized in that a copy of information stored in the ROM is stored in the cache memory. 3. The cache memory control system according to claim 2, wherein when a copy of the information stored at the address in the ROM is stored in the cache memory, the cache memory is not updated. 4. The cache memory control method according to claim 2, wherein when a copy of the information stored at the address of the ROM is stored in the cache memory, the copy of the information is invalidated. . 5. At least cache memory, main memory, and R
In an information processing device comprising an OM, means is provided for allowing or prohibiting the main memory and the ROM to store copies of information stored in the main memory and the ROM in the cache memory, respectively. An information processing device characterized by: 6. The information processing apparatus according to claim 5, wherein during checking of the main memory, a copy of the information stored in the ROM is allowed to be stored in the cache memory;
A main memory checking method characterized in that storing a copy of information stored in the main memory in the cache memory is prohibited.