JPS63100554A - Memory controller - Google Patents

Abstract

PURPOSE:To extend a ROM area by dividing address multiplex areas of a ROM and a RAM and switching each divided area to a ROM area or a RAM area to use it. CONSTITUTION:If the signal on a memory controlling signal line 103 means extension of the ROM area in case of memory access, a memory control circuit 14 validates a ROM from address 0 to address B on a memory map by the signal on a ROM select signal line 104 and validates a RAM from address B to address C by the signal on a RAM select signal line 105. If the signal on the memory switching signal line 103 means reduction of the ROM area, the memory control circuit 14 validates the ROM from address 0 to address A on the memory map by the signal on the ROM select signal line 104 and validates the RAM from address A to address C by the signal on the RAM select signal line 105.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a memory control device in a computer system.

[Structure of the Invention] “(Means for Solving the Problem) The memory control device of the present invention divides the address multiplexing area into several areas in the address multiplexing area of ROM and RAM. The configuration is such that each area is switched between a ROM area or a RAM area for use.For this reason, a register for latching memory area switching information is added to the components of conventional devices of this type.

(Operation) In the above configuration, the CPU first outputs data indicating switching of an address and a memory area. The input/output control circuit decodes the address and enables the register. Thereby, the data is latched in the register and supplied to the memory control circuit as a memory switching signal. The memory control circuit controls R according to the register output and address.
Generates an OM select signal and a RAM select signal and supplies them to the ROM and RAM, respectively.

This allows the ROM area and RA area to be
It can be used by switching to the M area, so the ROM
It becomes possible to expand the area and RAM area.

(Prior Art) Generally, the memory of a computer system consists of a ROM area and a RAM area, and is configured as shown in FIG. 3, for example. In FIG. 3, when accessing data in ROMB2, CPU 31 outputs an address on address bus 300 and also enables memory control signal line 302 supplied to memory control circuit 34. The memory control circuit 34 then decodes the data on the address bus 300 and enables the ROM select signal line 303. Thereby, the ROM 32 outputs data corresponding to the address on the address bus 300 onto the data bus 301, and the CPU 31 reads the data on the data bus 301.

When writing data to the RAM 33, the CPU 31 outputs an address on the address bus 300 and data on the data bus 301, and enables the memory control signal line 302 supplied to the memory control circuit 34. The memory control circuit 34 then decodes the data on the address bus 300 and makes the RAM select signal 304 valid. Thereby, the RAM 33 writes the data on the data bus 301 to the memory address on the address bus 300.

For reading from RAM 33, CPU 31 outputs an address on address bus 300 and enables memory control signal line 302.

The memory control circuit 34 then decodes the data on the address bus 300 and makes the RAM select signal 304 valid. Thereby, the RAM 33 outputs data corresponding to the address on the address bus 300 to the data bus 301, and the CPU 31 reads the data output onto the data bus 301.

A memory map of a conventional example configured in this manner is shown in FIG. In Figure 4, the ROM is from address 0 to address A.
The area from address A to address B is the RAM area.

(Problems to be Solved by the Invention) However, according to the above-mentioned conventional example, the area used as ROM cannot be used as a RAM area, and in addition, as the degree of integration of systems is increasing, system self-diagnosis and R
In order to bootload AM firmware, etc., it is necessary to expand the ROM area where those programs are stored, but as the ROM area increases, the area that can be used as RAM decreases. There was a drawback.

The present invention has been made based on the above drawbacks, and an object of the present invention is to provide a memory control device that allows expansion of the ROM area without reducing the RAM area by adding a small amount of hardware.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 11 is a CPU. 12 is ROM, 13
is RAM, address bus 100, data bus 10
It is connected to the CPUI 1 via 1. 14 is a memory control circuit. The memory control circuit 14
A control signal supplied from II to the memory control signal line 102, an address supplied via the address bus, and a memory switching signal supplied from a register 16, which will be described later, are input. Thereby, the ROM select signal is transmitted through the ROM select signal line 104 from RO to
112 to R via RAM select signal line 105.
An AM select signal is supplied to the RAM 13. Reference numeral 15 denotes an input/output control circuit, which inputs a control signal supplied from the CPU 11 via an input/output control signal line 106 and an address supplied via the address bus 100, and sends a register control signal line to a register 16 to be described later. 10
7 for supplying control signals. A register 16 receives data supplied from the CPU II via the data bus 101 and supplies a memory switching signal to the memory control circuit 14 via a memory switching signal line 107.

FIG. 2 is a memory map of the above embodiment.

In Figure 2, the area from address O to address A is ROM.
The area from address A to address B is a ROM and RAM switching area, and the area from address B to address C is a RAM area.

The operation of the embodiment of the present invention will be explained in detail below. 1st
In the figure, the CPU II outputs an address onto the address bus 100, and also outputs data indicating memory area switching onto the data bus 101, and makes the input/output control signal line 106 valid. and input/output control circuit 1
5 decodes the address on the address bus 100,
Register control signal line 107 is enabled. As a result, the data on the data bus 101 is latched into the register 16, and the memory switching signal line 1 is sent to the memory control circuit 14.
07 as a memory switching signal.

When accessing the memory, if the signal on the memory control signal line 103 is a signal indicating expansion of the ROM area, the memory control circuit 14 uses the signal on the ROM select signal line 104 to access the address 0 of the memory map in FIG. The ROM from address B to address B is enabled, and the RAM from address B to address C is enabled by a signal on the RAM select signal line 105.

Also, the signal on the memory switching signal line 103 is RO
If the signal means reduction of M area, memory control circuit 1
4 is a signal on the ROM select signal line 104 that selects R from address 0 to address A in the memory map in FIG.
OM is enabled, and the RAM from address A to address C is enabled by a signal on the RAM select signal line 105.

As mentioned above, in the memory area where addresses 0 to B in the memory map in Figure 2 are multiplexed in ROM and RAM, the area from RAM addresses A to B, which was previously unusable, can be used. effective.

Note that in this embodiment, only one of the divided areas is used by switching between the ROM area and the RAM area, but even if there are multiple areas to be switched, the area that can be used as RAM increases. effective.

[Effects of the Invention] According to the present invention, by dividing the address multiplexing area of ROM and RAM and switching between the ROM area and the RAM area for each divided area, the ROM area can be used hidden in the ROM area. This has the effect of making it possible to use areas of the ROM that otherwise could not be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing its memory map, and FIG. 3 is a block diagram of a conventional example.
FIG. 4 is a diagram showing the memory map.

Claims (1)

[Claims] In a computer system that has a memory area consisting of ROM and RAM with multiplexed addresses, the area with multiplexed addresses is divided, and each divided area has a ROM
a register in which information for switching to an area or a RAM area is set; a CPU that outputs an address and the area switching signal to the memory; an input/output control circuit that decodes the address and supplies a control signal to the register; A memory control device comprising a memory control circuit that generates a ROM select signal and a RAM select signal according to a memory switching signal outputted through a register and the address signal, and supplies the signals to the ROM and RAM, respectively.