JPH03214250A - Memory control circuit - Google Patents

Abstract

PURPOSE:To set an optimum division rate based on a control program by dividing a memory into smaller blocks when the same memory are divided and used by plural microprocessors. CONSTITUTION:In regard of the memory data switch circuits 41, 42...4n, a data bus (b) of a main microprocessor 1 is connected to the memory data hi (i=1=n) as long as the memory switch signals gi (i-1-n) are turned on. Meanwhile a data bus (e) of a secondary microprocessor 2 is connected to the data hi when the signals gi are turned off. In regard of the address switch circuits 51, 52...5n, the address state of the microprocessor 1 is transmitted as the memory addresses hi when the signals gi are turned on. Meanwhile the address state of the microprocessor 2 is transmitted as the addresses hi when the signals gi are turned off respectively. In such a constitution, an optimum division rate is set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control circuit, and particularly to a memory control circuit controlled by a plurality of microprocessors.

[Conventional technology]

Conventionally, in this type of memory control circuit, when memory defined in the same address space is divided and used by multiple microprocessors, the divided area is determined at the time of hardware design, and the memory used by each processor is defined. The area and maximum capacity were unchanged.

[Problem to be solved by the invention]

In the above-mentioned conventional memory control circuit having multiple microprocessors, the maximum capacity of memory used by each processor was not variable. It has the disadvantage of being uneconomical because it requires a minimum capacity.

[Means to solve the problem]

The memory control circuit of the present invention has a main microprocessor and one or more sub-microprocessors each having an address bus, a control signal, and a data bus, receives the control signals and the memory address bus, and inputs and outputs the memory data bus. In a microprocessor system including memory, the data buses of multiple microprocessors and the memory data bus are used as input/output, and the input memory switching signal determines which microprocessor the memory belongs to, and the memory data A memory data switching circuit that enables the bus to be opened only to the processor to which the memory belongs, and a memory whose output is the memory switching signal that is the input of the memory data switching circuit, and whose input is the data bus of the main microprocessor. A memory address switching circuit that receives a switching signal setting register, the address bus of each microprocessor, and a memory switching signal as input, and sends the contents of the address bus of the processor to which the memory belongs to the memory as a memory address. have.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a circuit of one embodiment of the present invention. In FIG. 1, a main microprocessor l has an address bus a and a control signal C as output signals, and a data bus b as an input/output signal. The sub microprocessor 2 also has the microprocessor 1, an address bus d and a control signal f as output signals, and a data bus e as an input/output signal.

FIG. 1 shows an example in which the memory is divided into n parts, each with 31 . Memory 32° - ~ -, Memory 3
It is n.

Memory data switching circuits 41, 42, ---4n
is the data bus b of the main microprocessor l, the data bus e of the sub microprocessor 2, and the memory data h 1+
The memory 31 which is the input and output of h 2 r −−−+ h n and which is the output of the memory switching signal setting register 6
, 32, ---, 3n, respectively, memory switching signals g' r g 2+ ---t g
' as input, memory aerodynamic change signal gi (i = 1 ~
n) is in the ON state, the data bus b of the main microprocessor l is connected to the memory data h i (i=l to n), and if it is in the OFF state, the data bus e of the sub microprocessor 2 and the memory data h1 are connected. (i=1 to n) are connected to each other.

Address switching circuits 51, 52, ---, 5
Is n the main microprocessor? The address bus a of microprocessor 1, the address bus d of sub-microprocessor 2, and the memory switching signal gi (i=1-n) are input, and if the memory switching signal gi (i=1-n) is in the ON state, the main The address state of microprocessor l is set to memory address hi
(i=l-n), memory switching signal gi
(i=1 to n) is in the OFF state, the address state of the sub microprocessor 2 is changed to the memory address h i (i
=1 to n).

Next, FIG. 2 shows a specific example of this embodiment, with one main microprocessor and one sub microprocessor, and 4 Mbytes divided into eight parts, 0 and 5.
A case is shown in which a memory of 8 M bytes is used to control the memory of a system, and FIG. 3 shows a memory data switching circuit.

In FIGS. 2 and 3, data buffer 71.7
Reference numeral 2 denotes a buffer that allows data to flow in both directions, and inputs and outputs the data bus b of the main microprocessor l of the data buffer 71 and memory data hi (i=1 to 8).
The data buffer 72 opens when the memory switching signal gi (i=1 to 8) is "1". The data buffer 72 is connected to the data bus e of the sub microprocessor 2 and the memory data h
) as input and output, and memory switching signal g i (i=l
~8) is 10". Therefore, the memory data hi is connected to the data bus b of the main microprocessor 1 when the memory switching signal gi is "l", and when the memory switching signal gi is V"O". It will be connected to the data bus e of the sub microprocessor 2.

Similarly, in FIG. 4, when the memory switching signal gi of the address buffers 81 and 82 is "l", the address bus a of the main microprocessor 1 is connected to the memory switching signal g.
When i is "0", the address bus d of the sub microprocessor 2 is connected to the memory address ji.

In the above system, the memory switching signal gi (i=
1 to 8) are set to 111100000" in order from i=x, memories 31, 32, and 33 are used as memories for the main microprocessor, memories 34 to 38 are used as memories for the sub microprocessor, and 1.5M bytes, and the secondary microprocessor has a memory capacity of 2.5M bytes.Furthermore, if the memory switching signal gi (i=1 to 8) is set to "11111110" in order from i=l, the memory capacity is 4M bytes. Only 0.5 MB of memory 38 is used by the secondary microprocessor, and the remaining 3.5 MB is used by the main microprocessor. This is the area of

〔Effect of the invention〕

As explained above, in the present invention, when the same memory is divided and used by multiple microprocessors, the division ratio can be changed by software by dividing it into smaller blocks, and the optimum division ratio can be set by the control program. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a case where the memory is divided into eight parts in this embodiment.
3 is a diagram showing a memory data switching circuit in this embodiment, and FIG. 4 is a diagram showing a memory address switching circuit in this embodiment. 1-゛----main microprocessor, 2...
Sub-microprocessor, 31-3n...memory, 41-4n...memory data switching circuit,
51~5n...Memory address switching circuit,
6...Memory switching signal setting register, 71
．． 72... Data buffer, 81.82...
...address buffer, a...°°address bus of the main microprocessor, b...data bus of the main microprocessor, C...control signal of the main microprocessor, d. ...Address bus of the sub microprocessor, e...old data bus of the sub microprocessor, f...control signal of the sub microprocessor, g1 to gn...memory switching signal , hl~hn...memory data, j1~jn...memory address.

Claims (1)

[Claims] Generally, a main microprocessor and one or more sub-microprocessors having an address bus, a data bus, and control signals, and a memory including the control signals and the memory address bus as inputs and the memory data bus as input/output. In a processor system, the data bus of each of the plurality of microprocessors and the memory data bus are used as input/output, a memory switching signal as an input determines which microprocessor the memory belongs to, and the memory data is A memory data switching circuit that enables a bus to be opened only to the microprocessor to which the memory belongs, and an output of the memory switching signal that is an input of the memory data switching circuit, a memory switching signal setting register that receives the bus as input, and the address bus of each microprocessor;
1. A memory control circuit comprising: a memory address switching circuit which receives the memory switching signal as an input and sends an address bus of a microprocessor to which the memory belongs to the memory as the memory address.