JPH04170653A - Cache memory system - Google Patents

Abstract

PURPOSE:To effectively utilize a cache memory by providing this cache memory system with a conversion circuit for changing corresponding relation between an address to be applied to a tag part and an address outputted from a processor. CONSTITUTION:Addresses 8 outputted from a processor 1 are divided into a data part 9 and an address part 10 and inputted to a tag part 13, which compares information led by information indicated by the address part 10 in a memory cell 4 with the information of the data part 9 by a comparing part 14 and transfers a compared result 11 to a memory part 3 to transfer control. A conversion circuit 2 is inserted into the data flow to change relation between the address to be applied to the tag part 13 and the address outputted from the processor 1. Even when a program having addresses frequently generating discrepancy is driven in the tag part 13, a cache memory capable of constructing an optimum environment corresponding to an operating state and having a high access speed can be effectively utilized.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to cache memory systems.

[Conventional technology]

Conventionally, in this type of cache memory system, the relationship between the address given to the tag section and the address output by the processor is fixed.

[Problem to be solved by the invention]

In the conventional cache memory system described above, the relationship between the address given to the tag section and the address output by the processor is fixed, so depending on the relationship between the addresses of the program operated in this cache memory system, the tag section This has the drawback that the number of cases in which addresses are duplicated increases, the probability that mismatches in tag parts will occur increases, and the cache memory, which has a fast access speed, cannot be used effectively.

[Means to solve the problem]

The cache memory system of the present invention includes a conversion circuit that changes the correspondence between the address given to the tag section and the address output by the processor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In order to read the memory, the processor 1 outputs a control signal 6 and an address 8. The address 8 output from the processor is input to the memory section 6 together with the control signal 6,
The address 8 is divided into a data part and an address part 10 and input to the tag part 13 .

In the tag section 13, the comparison section 14 compares the information derived from the information indicated in the address section 1 in the memory cell 4 with the information in the data section 9, and passes the comparison result 11 to the memory section 3 for control. yield.

If the comparison results 11 match, the memory unit 3 passes the data in the cache memory to the processor; if they do not match, the memory unit 3 passes the data in the main memory to the processor 1, and at the same time transfers the data to the cache memory. The tag controller 5 updates the memory cell 4 using the control signal 12.

Address 8 output from processor 1 in this flow
There is a conversion circuit 2 that can change the corresponding relationship between the address field 10 and the address field 10 input to the tag section 13.

Here, a specific example will be explained assuming that the bus width of address 8 output from processor 1 is 8 bits.

If the correspondence of the conversion circuit N2 shown in FIG. 1 is in the state shown in FIG. 2, then in the case of the address of the processor shown in FIG. 4,
The tag address is the same for all cycles from A to E, and the contents of the memory cell 4 shown in FIG. 1 are updated by the control signal 12 from the tag control section 5. In other words,
Although A and E in FIG. 4 are addresses from the same processor, the comparison result 11 from the comparator 14 shown in FIG. 1 is in a mismatched state.

However, when the correspondence of the conversion circuit 2 shown in FIG. 1 is changed to the state shown in FIG. 3, as shown in FIG. 5, even though the address of the processor is the same as in FIG. The memory cell 4 is updated by the control signal 12 from the tag control unit 5 shown in the figure, but since the address of the memory cell 4 is different, the data from the comparison unit 14 shown in FIG. The comparison result 11 is a match state.

〔Effect of the invention〕

As explained above, the present invention provides a program that has addresses that frequently cause mismatches in the tag section by changing the corresponding relationship between the address given to the tag section and the address output by the processor. Even if the system is operated, it has the effect of creating an optimal environment according to the operating state and making effective use of cache memory with fast access speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the corresponding relationship between the address given to the tag part and the address output by the processor, and FIGS. FIG. 5 is a diagram illustrating the relationship between the address output by the processor and the address of the tag section, including specific data. DESCRIPTION OF SYMBOLS 1... Processor, 2... Conversion circuit, 3... Memory part, 4... Memory cell, 5... Tag control part, 6...
... Control signal, 7... Data, 8... Address output by the processor, 9... Data section outputted to the tag section, 10... Address section outputted to the tag section, 11...
Matching information of the tag section, 12... Control signal output by the tag control section, 13... Tag section, 14... Comparison section.

Claims (1)

[Claims] A cache memory system comprising a conversion circuit that changes the correspondence between an address given to a tag section and an address output by a processor.