KR960018958A

KR960018958A - Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System

Info

Publication number: KR960018958A
Application number: KR1019940030614A
Authority: KR
Inventors: 원철호; 김성운; 윤석한
Original assignee: 양승택; 재단법인 한국전자통신연구소
Priority date: 1994-11-21
Filing date: 1994-11-21
Publication date: 1996-06-17
Also published as: KR0135927B1

Abstract

본 발명은 다수개의 프로세서(CPU)가 버스를 통하여 메인 메모리에 연결된 다중 프로세서 시스템에 관한 것으로 특히, 각각의 프로세서 보드마다 독특한 기능을 수행하기 위한 중앙처리장치와, 어드레스 버스와 데이타 버스 및 제어 버스로 상기 중앙처리장치와 연결되어 상기 시스템 버스를 통하여 메인메모리 액세스동작을 수행하는 버스정합부와, 상기 제어버스와 어드레스 버스에 연결되고 입력되는 어드레스와 제어 정보를 해독하여 메모리 액세스 사이클을 제어하는 소정갯수의 제어신호를 발생시키는 메모리 제어부와, 상기 데이타 버스를 통하여 상기 중앙처리장치와 연결되어 상기 메모리 제어부의 제어신호에 따라 데이타를 저장 또는 출력하는 레지스터 및 상기 레지스터에 저장되어 있는 데이타와 상기 데이타 버스를 통하여 입력되는 데이타를 비교하여 상기 메모리 제어부에 입력하는 비교기를 포함하는 것을 특징으로 하는 다중프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치를 제공하여 불필요한 동작의 수행을 방지할 수 있는 효과가 있다.The present invention relates to a multiprocessor system in which a plurality of processors (CPUs) are connected to main memory through a bus. In particular, the present invention relates to a central processing unit, an address bus, a data bus, and a control bus for performing unique functions for each processor board. A bus matching unit connected to the central processing unit to perform a main memory access operation through the system bus, and a predetermined number of memory access cycles connected to the control bus and the address bus to read and input address and control information. A memory controller for generating a control signal of the memory; and a register connected to the central processing unit through the data bus to store or output data according to a control signal of the memory controller; and a data stored in the register and the data bus. Day entered through In the multiprocessor system, a main memory access device using a data buffer is used to execute an atomic instruction in a multiprocessor system.

Description

Main Memory Access Device Using Data Buffer When Performing Atomic Instruction in Multiprocessor System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따라 아토믹 명령어 수행시 데이타 버퍼를 사용하여 메인 메모리를 액세스할 수 있도록 구성되어 있는 다중 프로세서 시스템의 구성 예시도,1 is an exemplary configuration diagram of a multiprocessor system configured to access a main memory using a data buffer when performing an atomic instruction according to the present invention.

제2도는 제1도에서 도시되어 있는 다중 프로세서 시스템에서의 아토믹 명령어 수행 과정 순서도.2 is a flow chart of the atomic instruction execution process in the multiprocessor system shown in FIG.

Claims

In a multiprocessor system in which a plurality of processor boards are connected to the system bus to access the main memory for data communication with main memory connected to a system bus, each processor board has a unique function. A central processing unit for performing; A bus matching unit connected to the central processing unit through an address bus, a data bus, and a control bus to perform a main memory access operation through the system bus; A memory control unit connected to the control bus and the address bus and generating a predetermined number of control signals for decrypting an input address and control information to control a memory access cycle; A register connected to the central processing unit through the data bus to store or output data according to a control signal of the memory controller; And a comparator for comparing the data stored in the register with the data input through the data bus and inputting the data to the memory controller. Device.

The method of claim 1, wherein the memory controller transfers an input control signal to the register in a read cycle of atomic data so that a value of the data bus is input to and stored in the register, and transmits an output control signal in a write cycle of atomic data. Main memory access device using a data buffer when performing an atomic instruction in a multiprocessor system, characterized in that to output the contents stored in the register (41).

The memory controller of claim 1, wherein the memory controller examines an output signal of the comparator and stores data output from the CPU in a write cycle of atomic data and data stored in the register in a read cycle of atomic data. In the same case, the main memory access device using a data buffer when performing an atomic instruction in a multiprocessor system, characterized in that for stopping the write operation requested from the central processing unit.

※ Note: The disclosure is based on the initial application.