JP2619425B2 - Sequence controller - Google Patents

Description

The present invention relates to a sequence controller for controlling a machine tool, a robot, and the like.

"Conventional technology" Sequence controllers support relay circuit diagrams
Bit CPUs that specialize in bit-by-bit logical operations because they often execute bit operation instructions such as AND logic
(Processing unit) and a word CPU that specializes in processing ordinary computer instructions such as 16-bit word-by-word numerical calculations
(Processing device) in many cases with a multi-CPU system.

As shown in FIG. 6, a conventional multi-CPU system device
The bit CPU 1 and the word CPU 2 are connected in parallel to the address buses 21, 23 and the data buses 22, 24 of the sequence program memory 3 and the data memory 4, respectively. A bit CPU1 for executing a basic instruction such as a bit operation;
The word CPU 2 that executes application instructions such as numerical calculation is connected to each other by processing request signal lines 25 and 26. Basic control was performed by the bit CPU1, and when the bit CPU1 detected an application instruction, a processing request 25 was issued to the word CPU2, and the word CPU2 was operated. For this reason, word CPU2 that received processing request 25
Requires that the address of the sequence program memory 3 in which the application instruction to be executed is stored be notified from the bit CPU 1 and that the application instruction be read from the sequence program memory 3 and processed again. Therefore, if an application instruction is interposed in the program instruction, there is a problem that the processing speed is extremely reduced.

"Problems to be Solved by the Invention" The present invention has been made in order to solve the above-described problems, and while ensuring the processing speed of a bit operation (basic instruction) which is a basic process of a sequence controller, It is an object of the present invention to provide a device capable of accelerating the processing of an application instruction.

"Means for Solving the Problems" A description will be given with reference to FIG. In order to achieve the above object, according to the present invention, in a multi-CPU sequence controller including a bit CPU 1 mainly performing a bit operation and a word CPU 2 performing a numerical operation and the like, a sequence program memory 3 and a bit CPU 1 are connected. A fetch register 5 for temporarily storing the data of the data bus 12 to be stored by the number of words constituting at least one application instruction, and either the output of the fetch register 5 or the data bus 13 from the data memory 4. Word CPU2
And a data bus selection circuit 7 connected to the data bus 17 of the data memory 4 and one of the output of the fetch register 5, the address bus 14 from the bit CPU 1, or the address bus 16 from the word CPU 2. A selection signal is output to the data bus selection circuit 7 and the address bus selection circuit 6 according to the address bus selection circuit 6 connected to the address bus 15 and the data on the address bus 16 from the word CPU 2 and the processing request signal 18 from the bit CPU 1. And an address decoder circuit 8.

[Operation] According to the above configuration, the basic instruction is a dedicated bit CP.
High-speed processing by U1. On the other hand, since the latest several words of data read by the bit CPU 1 are always stored in the fetch register 5, when the bit CPU 1 detects an application instruction, the number of opcodes, operands, etc. constituting the application instruction is All the word data (instructions) are stored in the fetch register 5. Therefore, the word CPU 2 having received the processing request does not need to read the instruction from the sequence program memory 3 again, and can perform the processing of the applied instruction such as reading the contents of the data memory 4 in accordance with the contents of the fetch register 5. And speed up the processing. When processing the application instruction, the address of the data memory 4 is controlled by the address bus selection circuit 6 and the content of the data bus 17 of the word CPU is controlled by the data bus selection circuit 7, so that the word CPU 2 The data specified by the operand can be read and written without reading the contents, and the processing of the application instruction is further speeded up.

"Example" An example of the present invention will be described with reference to the drawings. First
FIG. 2 is a block diagram showing a basic configuration of the embodiment, and FIGS. 2 and 3 are main block diagrams showing a detailed configuration.

This sequence controller includes two CPUs (central processing units): a bit CPU 1 for executing basic instructions such as bit operations and a word CPU 2 for executing applied instructions such as numerical calculations. The memory includes a sequence program memory 3 for storing a sequence program for machine control including basic instructions and application instructions, and a data memory 4 for storing various data during control. Sequence program memory 3 and bit CPU1
Are directly connected by an address bus 11 and a data bus 12. The data memory 4 and the bit CPU 1 are connected to the data bus 13
Are directly connected, but the address buses 14 and 15 are connected via the address bus selection circuit 6.

The fetch register 5 is connected to the data bus 12 of the sequence program memory 3. The fetch register 5 has four registers 51, 52, 53, 54 as shown in FIG.
This is a register having a capacity of 4 words, and constantly stores the data of the sequence program memory 3 which is addressed and read by the bit CPU 1 over the past four times. When the read data (instruction) is an applied instruction, the contents of the four words include an operation code (51) indicating the type of instruction, and a numerical value (constant) or a numerical value to be processed by the instruction. It consists of three operands (52, 53, 54) indicating the address of the data memory 4.

The output of the fetch register 5 is an address bus selection circuit 6
And a data bus selection circuit 7. As shown in FIG. 2, the data bus selection circuit 7 includes a fetch register 5
Are connected to the address bus selection circuit 6, but only the lower three word registers 52, 53 and 54 are connected. This is because the address bus selection circuit 6 requires only three operand parts.

The address bus selection circuit 6 is connected to an address bus 14 from the bit CPU 1 and an address bus 16 from the word CPU 2 in addition to the output of the fetch register 5. As shown in FIG. 2, the address bus selection circuit 6 comprises three gate circuits 61, 62, 63 and two multiplexers 64, 65, and the selection signals CS0, CS1, CS from the address decoder circuit 8.
2 and three word registers 52, 53, 54 of the fetch register 5 in accordance with the processing request signal ▲ ▼ from the CPU1.
Or one of the address buses 14 and 16 of the bit CPU 1 or the word CPU 2 can be connected to the address bus 13 to the data memory 4. For example, when the processing request signal ▲ is not output from the bit CPU 1, the address bus 14 from the bit CPU 1 is directly connected to the address bus 15 to the data memory 4 by the multiplexer 65.

The data bus selection circuit 7 is connected to a data bus 13 from the data memory 4 in addition to the output of the fetch register 5. The data bus selection circuit 7 has five gate circuits
71, 72, 73, 74 and 75. The outputs of the four word registers 51 to 54 of the fetch register 5 or the data bus 13 from the data memory 4 in accordance with the selection signals CS3, CS4, CS5 and CS6 from the address decode circuit 8. Can be selected and connected to the data bus 17 of the word CPU1.

A processing request signal line 18 from the bit CPU 1 and an address bus 16 from the word CPU 1 are connected to the address decoder circuit 8. As shown in FIG. 3, the address decoder circuit 8 is composed of two NAND gates 82 and 83 with a decode circuit 81.
When ▼ is output, the data on the address bus 16 from the word CPU 2 is decoded and various selection signals CS0 to C
Outputs S6. As described above, the data bus selection circuit 7 and the address bus selection circuit 6 are opened and closed by the selection signals CS0 to CS6.

The bit CPU1 and the word CPU2 are connected by a processing request signal line 18, and the processing of the word CPU2 is started by outputting a processing request signal
The processing of the bit CPU1 is restarted by returning a processing completion signal from the CPU2.

FIG. 4 is a flowchart showing the processing in the bit CPU1.

When the process 100 of the bit CPU 1 is started, an instruction is read from the sequence program memory 3 in step 101.
Next, in step 102, the command is decoded. Next, in step 103, it is determined whether the instruction word is a basic instruction for performing a bit operation such as AND or OR logic or an application instruction for performing a parallel operation for each word such as a numerical calculation. If it is a basic command, the process proceeds to step 104, executes the process of the command, ends the process, and returns to step 101 again. On the other hand, if it is an application instruction, the process proceeds to step 105. In step 105,
Outputs a processing request signal ▲ ▼ to word CPU2. Then, in step 106, the process waits until a signal indicating the completion of the process is returned from the word CPU2.

FIG. 5 is a flowchart showing the processing in the word CPU2.

When the processing request signal ▲ ▼ is output from the bit CPU1, the processing 200 of the word CPU2 is started. First, in step 201, the operation code is read from the fetch register 5. This is because a specific address is output to the address bus 16 and the selection signal
▼ is output and the gate circuit of the data bus selection circuit 7
The operation code is read out by opening the contents of the word register 51, in which the operation code portion of the fetch register 5 is stored, to the data bus 17.

Next, in step 202, it is determined whether the operand following the instruction code is an indirectly-specified instruction specifying the address of the data memory 4 or a directly-specified instruction indicating the constant to be operated. Determine.

If the instruction is an indirect designation, the process proceeds to step 203, where the contents of the data memory 4 designated by the operand portion are read,
Stored in the internal register of word CPU2. For example, it is assumed that the application instruction this time is an addition instruction (ADD, OP1, OP2, OP3). This instruction ADD reads and adds the contents of the memory address specified by OP1 and the contents of the memory address specified by OP2, and stores the result in the memory address specified by OP3. . The word CPU2 that has decoded the operation code ADD of the addition instruction,
Outputs a specific address to the address bus 16 and causes the address decoder circuit 8 to output the selection signal ▲ ▼, so that the gate circuit 61 of the address bus selection circuit 6 and the multiplexer are output.
By opening 64 and 65, the contents OP1 of the word register 52 in which the first operand portion of the fetch register 5 is stored are output to the address bus 15 to the data memory 4. As a result, the data memory 4 outputs the data at the address OP1 to the data bus 13, and the word CPU 2 outputs the data at the data bus selection circuit 7.
Read that data via. Similarly, the word CP
U2 sequentially changes a specific address to be output to the address bus 16, and reads the contents OP of the word register 53 of the fetch register 5.
The contents of the data memory 4 having the memory address 2 are read. Then, in step 205, the arithmetic processing (addition) is performed.
The result is output to the data bus 17. At the same time, by outputting a specific address to the address bus 16, the gate circuit 63 of the address bus selection circuit 6 is opened, and the word register
The contents of operand OP3 stored in 54 are stored in data memory 4
To the address bus 15 to specify a memory address, and store the operation result in the address (OP3).

In this way, even if the application instruction is an instruction that indirectly specifies an operand, the word CPU2 determines the contents OP1,
Processing can be performed by mechanically outputting a specific address and operating the address decoder circuit 8 without knowing OP2 and OP3, so that processing of applied instructions can be speeded up.

On the other hand, in step 201, if the instruction is a directly specified instruction in which the operand itself indicates a constant to be operated, the process proceeds to step 204, where a specific address is output to the address bus 16 and the operand is stored in the fetch register. 5 and the arithmetic processing is performed in step 205.

When the calculation processing is completed, the process proceeds to step 206,
The processing completion signal is returned to the bit CPU1, and the current processing of the word CPU2 ends. In response to the processing completion signal, the bit CPU 1 returns from the standby state of step 106 to step 101 and starts processing the next instruction.

As described above, the word CPU 2 does not need to read the sequence program memory 3 directly, and only outputs a specific address to the address bus 16 in accordance with the content of the decoded opcode and mechanically designates the content of the operand or the operand. The contents of the data memory 4 can be accessed, and the processing speed of the application instruction can be increased.

[Effects of the Invention] As described above, the present invention has the above configuration, and includes a fetch register having a capacity of several words and each bus selection circuit for selecting an address bus and a data bus. The word CPU that processes application instructions can perform processing without reading the contents of the sequence program anew, and the processing speed of application instructions is extremely high in a multi-CPU sequence controller that has a bit CPU and a word CPU. There is an excellent effect that can be.

[Brief description of the drawings]

1 to 5 show an embodiment of the present invention, FIG. 1 is a block diagram showing a basic configuration of a sequence controller of the embodiment, and FIGS. 2 and 3 are block diagrams showing a detailed configuration of main parts. 4 and 5 are flowcharts showing the processing in the bit CPU and the word CPU, respectively, and FIG. 6 is a block diagram showing a conventional apparatus. 1 ... bit CPU, 2 ... word CPU, 3 ... sequence program memory, 4 ... data memory, 5 ... fetch register, 6 ... address bus selection circuit, 7 ... data bus selection circuit, 8 ... Address decoder circuit, 11, 14,
15,16 …… Address bus, 12,13,17 …… Data bus, 18
... Processing request signal line.

Claims (1)

(57) [Claims] 1. A multi-CPU sequence controller mainly comprising a bit CPU for performing a bit operation and a word CPU for performing a numerical operation, etc., wherein data on a data bus connecting a sequence program memory and the bit CPU is A fetch register for temporarily storing at least the number of words constituting at least one application instruction, and a data bus selection circuit for selecting either the output of the fetch register or the data bus from the data memory and connecting to the data bus of the word CPU An address bus selection circuit for selecting any one of the output of the fetch register, the address bus from the bit CPU, and the address bus from the word CPU and connecting to the address bus of the data memory; and an address from the word CPU. The data bus selection according to the bus data and the processing request signal from the bit CPU. And an address decoder circuit for outputting a selection signal to the selection circuit and the address bus selection circuit.