JPS60193046A - Detecting system for instruction exception - Google Patents

Abstract

PURPOSE:To start a microprogram for execution of instructions immediately after a macroinstruction is fetched by using a memory means which stores the proper information on the macroinstruction. CONSTITUTION:Each bit of a state flag 7 is used to display each type of state of a computer related to execution of each macroinstruction and then set and reset by a normal microinstruction in response to each displayed state. Then each word of a memory 5 which is read out with an operation code defined as an address is prescribed as an exception state of the corresponding instruction. Under such conditions, the corresponding bit of the flag 7 is set at ''1'' and other bits are set at ''0''. The data read out of the memory 5 is held at a register 6, and a pair of corresponding bits of the register 6 and the flag 7 is used as the input of a gate of an AND gate 8. The all outputs of the gate 8 are supplied to an OR gate 9.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a microprogram control computer, and particularly to a control method for detecting an instruction exception of a macro instruction.

M) Technical Background As a method for configuring the so-called central processing unit of an electronic computer,
Microprogram control methods are widely used. The microprogram control method has advantages such as fewer circuits and ease of changing functions, but generally the processing speed is slower than a method with a so-called dedicated circuit. It is necessary to introduce

(C) Prior Art and Problems In general, each computer instruction specification defines an exception state. An exceptional state is a state in which the execution of the instruction should be stopped; for example, the execution of a privileged instruction in a computer that is in a non-privileged mode must naturally be prevented from being executed due to the purpose of providing the privileged instruction. Therefore, such a state is one of the exceptional states that should be specified for privileged instructions.

When executing each instruction, the exception state specified in that instruction is checked, and if an exception state exists, the instruction is not executed normally, but after setting the predetermined state information, etc., the exception state is checked. A so-called index is made so that a program that performs cleanup processing in response to the occurrence of the condition can be started.

In conventional microprogram control computers, the microprogram for each instruction (macro instruction) is structured as shown in the schematic processing flow shown in Figure 1. , and only executes its original function when there is no exception condition. Therefore, even though exceptional states rarely occur, fixed processing time is always inserted into instruction execution to check all of them, which causes a decline in computer performance.

(d) Object of the Invention Accordingly, an object of the present invention is to provide an instruction exception detection method that can solve the problems of conventional microprogram computers as described above and improve the performance of the computer with a simple configuration. It is in.

(e) Structure of the Invention According to the present invention, in an instruction exception detection method for a microprogram controlled computer in which execution of macro instructions is controlled by a microprogram, a storage means for storing unique information of each macro instruction; means for accessing the storage means using the operation code of the instruction as an address; means for holding the unique information read by the access means; means for holding the state information of the computer; and generating an AND signal of corresponding bits of both holding means. This can be achieved by an instruction exception detection method characterized by having means for causing a branch to a specific microprogram based on the signal.

(f) Embodiment of the invention FIG. 2 is a block diagram showing an embodiment of the invention. 1 is a control storage device that stores a microprogram, 2 is its address register, and 3 is a microinstruction register that holds microinstructions fetched from the control storage device 1, and macros that are usually fetched from a main storage device, etc., not shown. The entry address of the microprogram that controls the execution of the macro instruction is determined by reading the operation code of the instruction (assumed to be held in register 4). However, in the application of the present invention, any known microinstruction and its control method may be used, and the microinstruction is not limited to a specific method. “In the present invention, the operation code of register 4 is also used to access exception condition storage 5. Each bit of one word of this storage 5 has the number of bits corresponding to each bit of status flag 7. have

Each bit of the status flag 7 is used to indicate various states of the computer related to macroinstruction execution, and each bit is usually set/reset by a microinstruction depending on the state it indicates.

Examples of states represented by these bits include, in addition to the non-privileged mode described above, a non-multiprocessing mode, a mode that does not use extended instructions, and others.

To explain with these examples, the relevant bit of the status flag is set to "1" in each mode of the clay figurine, and for example, the privileged mode is indicated by setting the non-privileged mode bit to 0.

For each word of the storage device 5 that is read using the operating link code as an address, the bit corresponding to the bit of the status flag 7 in the state defined as the exception state of the corresponding instruction is set to "1", and the other bits are set to 0. ”.

For example, for a privileged instruction, the bit corresponding to the non-privileged mode bit of status flag 7 is set to "1". Furthermore, if this instruction is a privileged instruction that can only be used in the extended instruction mode, the bit corresponding to the extended instruction unused mode bit is also set to "1". On the other hand, if this instruction is a privileged instruction that can be used regardless of multiprocessing (i.e., this condition is not defined as an exception state), the bit corresponding to the non-multiprocessing mode bit must be set to 0''. Must be.

Furthermore, in each word corresponding to a non-privileged instruction in the storage device 5,
All bits corresponding to non-privileged mode bits are set to 0''.

Read data from the storage device 5 is held in the register 6. Each corresponding bit pair of register 6 and status flag 7 becomes an input to one gate of AND gate 8, respectively. All outputs of AND gate 8 are input to OR gate 9. Therefore, assuming that the status flag 7 and each word of the storage device 5 are set as described above, when a privileged instruction consisting of, for example, a non-privileged mode is fetched, the non-privileged mode bit and the corresponding register 6 Both bits are 1'', so the AND condition of the bit pair is satisfied,
The exception signal 10, which is the output of the OR gate 9, becomes 1''.

The contents of register 11 are set in control storage address register 2 by exception signal 10 . A fixed exception handling microprogram entry address is set in the register 11 in advance. Therefore, the microprogram can initiate exception handling. The contents of the register 11 may be set to an address determined by a macro instruction.

With the above control system, the flow of processing corresponding to the flowchart of microprogram processing shown in FIG. 1 becomes as shown in the flowchart of FIG. 3.

(Effect of the Phantom Invention As is clear from the above explanation, according to the present invention, there is no need for the microprogram to check the exception status before executing each macro instruction, and the instruction is executed immediately after fetching the macro instruction.) Since the microprogram can be started, the performance of the computer can be improved, and the configuration of the microprogram can be simplified, contributing to improved reliability and reduced costs.

[Brief explanation of the drawing]

FIG. 1 is a flowchart of processing of a conventional instruction execution microprogram, FIG. 2 is a block diagram of an embodiment circuit, and FIG. 3 is a flowchart of processing of an instruction execution microprogram when the present invention is implemented. In the figure, 1 is a control storage device, 2 is a control storage address register, 3 is a microinstruction register, 4 is an operation code register, 5 is an exception condition storage device, 6 is a register, 7 is a status flag, 8 is an AND gate, 9 is an OR gate, 1o is an exception signal line, and 11 is a register. *3TfJ

Claims (1)

[Claims] In an instruction exception detection method for a microprogram controlled computer in which execution of macro instructions is controlled by a microprogram, a storage means for storing unique information of each macro instruction;
means for accessing the storage means using the operation code of the macro instruction as an address; means for holding the unique information read by the access means; means for holding the state information of the computer; and an AND signal of corresponding bits of both holding means. 1. An instruction exception detection method comprising: means for generating a signal; and means for causing a branch to a specific microprogram based on the signal.