JPS62150434A - Loop control type data processor - Google Patents

Abstract

PURPOSE:To execute repetitively only the data processing by not reading an address stored with the initializing instruction when the execution of initializing is not required. CONSTITUTION:When power is applied, '1' is set to an RES register 20 and '0' is set to an OEN register 17. When '1' is set to the register 17 succeedingly, a write signal is outputted from an instruction decoder 13 to a RAM 19 and a storage instruction is executed. Thus, data write from an input/output port 21 is enabled to the RAM 19 to execute the data processing. The content of the register 20 is set to the register 23 by a read signal outputted from the decoder 13. When the content is '0', the designated address of the program counter 11 is set to address '0', and initialization is executed. Then the data processing is repetitively executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a loop control type data processing device that does not have any branch instructions other than a branch instruction to address θ, for example.

[Background Art] For example, in a loop control type data processing device that does not have a branch instruction other than a branch instruction to address O, initialization is performed to uniquely set the state of the data processing device.
Data processing operations are performed within one loop control. That is, once the initialization is executed, the configuration is such that the execution of the initialization can be prohibited so that only data processing is executed repeatedly thereafter.

However, with this configuration, even when initialization is not executed, all addresses where initialization instructions are stored are read by the program counter. This results in longer program loops and slower data processing, regardless of whether initialization and data processing is performed.

Therefore, a loop control type data processing device that can effectively perform data processing is required.

[Problem to be solved by the invention] The present invention has been made in view of the above-mentioned points. The present invention aims to provide a loop control type data processing device that can repeatedly execute only data processing without reading the address where the data is stored.

[Means for Solving the Problem] That is, in the present invention, execution of a branch instruction to address 0 can be controlled based on the contents set in the output permission register, and initialization can be executed. After that,
(3) A predetermined value is set in the RES register so that the program can branch to address θ where the data processing program is stored.

[Operation] That is, in a loop control type data processing device using the above means, the address where the initialization instruction is stored is called only when initialization is requested, and the initialization is performed. After execution, the address where the data processing program is stored is called by a branch instruction to address O, and only this data processing is repeatedly executed.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a loop control type data processing device, in which a program counter 11 is connected to a ROM 12.
It specifies the address of the instruction stored in the . The ROM 12 with the specified address outputs the instruction stored at the specified address to the instruction decoder 13. This instruction decoder 13 decodes the instruction output from the ROM 12 and sends a signal corresponding to the instruction to the address bus 14. Output to data bus 15 and control bus 16. The signals output to this control bus 1B are a read signal and a write signal. The output permission (OE M) register 17 is used to determine the execution of a store instruction, and the output of this OEN register 17 is output to the AND circuit 1.
It is connected to one of the inputs of 8. This AND circuit 18
The other input of is connected to the control bus 16.

Therefore, the write signal output from the OEN register 17 to the RAM 19 via the control bus 16 is
It is determined by the logical product of the contents set in the OEN register 17 and the write signal output from the instruction decoder 13. Therefore, the reset (RES) register 20
If the signal set in the OEN register 17 via the data bus 15 from
A write signal to 9 is generated and a store instruction is executed,
Data can now be written from the human output port 21 to the RAM 19. Further, if the signal set in the register OE N 17 is logic "0", this write signal will not be generated and the store instruction will not be executed.

The logic unit (LU) 22 performs logical operations based on control signals output from the instruction decoder, and the results of the operations are stored in a result register 9 (RR) 23.
is stored in The output of this RR register 23 is connected to the input of the logic unit 22 and the instruction decoder 13. From the RR register 23 to the instruction decoder 13, logic “
1, that is, when a restart instruction is output, the program counter 11 is set to address θ by the instruction decoder 13.

FIG. 2 is a flowchart explaining the operation of the above embodiment. First, when the power is turned on, "1" is set in the RES register 20, and in step 101, the inverted RES, that is, rOJ, is set in the OEN register. It is set to 17. Next, in step 102, if the content set in the OEN register is "1", a write signal is output from the instruction decoder 13 to the RAM 19, and the store instruction is executed. When the store instruction is executed, data can be written from the input/output port 21 to the RAM 19, and normal data processing is executed. Also, OEM
If the content set in the register 17 is "0", a write signal to the RAM 19 is not output, and the store instruction is not executed. Therefore, data processing is no longer executed.

In step 103, the contents of the RES register 20 are changed to RR by the read signal output from the instruction decoder 13.
It is set in register 23, and the set content is "1".
If so, the process advances to the instruction at the next address, ie, step 104. Further, if the content set in the RR register 23 is "0", a restart instruction is executed. That is, the address specified by the program counter 11 is set to address 0, and the operation of step 101 is executed. In step 104, the contents of the RES register 20 are set in the OEN register 17. Step 105
So, what is the content set in this OEN register 17?
”, initialization is executed. And step 1
At step 06, the RES register is set to "0" and the address designated by the program counter 11 becomes address 0, so the operation at step 101 is executed again.

That is, after initialization is once executed in step 105, the operations from step 101 to step 103, that is, data processing, are repeatedly executed.

[Effects of the Invention] As described above, according to the present invention, execution of a branch instruction to address O can be controlled based on the contents set in the RES register, and the above-mentioned By setting a predetermined value in the RES register, it is possible to branch to address 0 where the data processing program is stored. Therefore, if there is no need to perform initialization, do not call the address where the initialization instruction is stored.
Only data processing can be executed repeatedly.

Therefore, data processing speed is faster than that of conventional data processing devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating a data processing apparatus according to an embodiment of the present invention, and FIG. 2 is a flowchart showing the operation of the data processing apparatus. 11...Program counter, 12...ROM, 1
3...Instruction decoder, 17...OEN register, 1
8...AND circuit, 19...RAM, 20...R
ES register, 22...Logic unit, 23...Result register. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] In a loop control type data processing device that does not have any branch instructions other than a branch instruction to address 0, writing that allows or prohibits the execution of a store instruction based on the contents set in an output permission register. a control means; a restart control means for permitting or prohibiting the execution of a branch instruction to address 0 where a data processing program is stored based on the contents set in the output permission register; and the restart control means. a restart setting means for setting a predetermined value in the output permission register after initialization is executed so that a branch to address 0 is executed by the loop control type, comprising: Data processing equipment.