JP2903601B2 - Microcomputer with built-in ROM - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a built-in ROM, and particularly achieves a dynamic BT screening effect.
It relates to a microcomputer with a built-in ROM.

[Conventional technology]

Conventionally, the BT screening (bias temperture: temperature voltage application screening) method of a one-chip microcomputer includes a method called static BT screening and a method called dynamic BT screening. In the static BT screening method, only the power supply voltage is supplied without operating the device, and the device is left at a high temperature. However, in this method, since no voltage is applied to most signal lines because the device is in an inactive state, only a small BT screening effect can be obtained. On the other hand, in the dynamic BT screening method, a signal is externally supplied to a device, the device is left in a high temperature state while operating, and a voltage is sometimes applied to an internal signal line to enhance a BT screening effect. However, the BT device for generating the signal to be supplied to the device was very expensive. Therefore, as a means to enhance the BT screening effect, an external clock
BT screening is performed by causing the CPU to sequentially execute a group of instructions stored in the CPU and to activate the internal circuit. However, usually, there are many jump instructions in the instruction group stored in the ROM, and the internal instruction to which only the clock signal is applied is used.
In most cases, the ROM operation mode loops a specific address of the ROM and executes only a limited instruction. In order to avoid this, by prohibiting the execution of the jump instruction by a control signal, it is possible to execute all of the instruction group stored in the ROM. In this manner, the one-chip microcomputer with a built-in ROM was activated, and BT screening was performed.

[Problems to be solved by the invention]

In the conventional microcomputer described above, when performing BT screening, it is effective when another instruction group is stored after the address following the jump instruction,
An inconvenience occurs when data is stored after the jump instruction. In other words, if the execution of the jump instruction is prohibited by the control signal, even if the data is stored at the next address, the CPU cannot determine that the data is the data, and will continue to execute it as an instruction. The CPU does not work properly and cannot perform effective BT screening.

[Means for solving the problem]

The present invention has a built-in ROM in which instructions or data are stored in advance, an internal operation based on the execution of the instructions read from the ROM is performed normally, and the BT screening during the BT screening
When the instruction read from the ROM is a branch instruction, a microcomputer with a built-in ROM that executes the next address by disabling or disabling the branch instruction is executed. Means for decoding and detecting the first and second instructions for execution prohibition and execution permission respectively, and a signal for prohibiting or invalidating instructions other than the first and second instructions in response to the respective detection signals of the means. And means for holding and outputting.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of a microcomputer with a built-in ROM according to the present invention. FIG. 2 is an example of a ROM memory map. The ROM address signal 20 is a signal for inputting a ROM address from the internal data bus 18 to the ROM address register 16. The ROM address signal 20 is an output signal of the gate circuit unit 13. The inputs of the gate circuit section 13 are the jump ROM address signal 12, the sequential ROM address signal 19, and the control signal.
It is 11. The output of the ROM address register 16 is connected to the ROM address decoder 14, and the output of the ROM address decoder 14 is supplied to the ROM cell unit 15. The accessed output of the ROM cell unit 15 is output to an internal data bus 18 and an instruction register (IR) 21 through a ROM output circuit 17. IR
The output of 21 is input to an instruction decoder (ID) 22. Instruction code detection signal lines 25 and 26 output from ID 22 are connected to the input of RS flip-flop 23. The control signal from the ID 22 and the output line 27 from the RS flip-flop 23 are connected to the control signal output circuit 24.

In the ROM cell section 15, as shown in FIG.
A jump instruction is at address (X-1), an arbitrary instruction 1 is at address X, an arbitrary instruction 2 is at address (X + n), and data is between addresses (x + 1) to (X + n-1). It is assumed that it is stored. In this state, when the jump instruction and the data part originally exist in the ROM cell part 15, arbitrary instructions 1 and 2 are added before and after the data part, and
It is stored in the M cell unit 15.

In the configuration described above, X is set by the address register 16.
When the address is specified and the instruction 1 is selected from the ROM cell section 15, the instruction 1 is taken into the ID 22 through the output circuit section 17 and the IR 21. The ID 22 detects the instruction when the instruction 1 is input, and outputs a detection signal to the S (set) terminal of the RS flip-flop 23 through the instruction code detection signal line 25. The RS flip-flop 23 receives this and outputs a “0” level signal, which is supplied to the AND circuit in the control signal output circuit unit 24 through the RS flip-flop output line 27. As a result, all the control signals generated by the control signal output circuit section 24 become “0” outputs. That is, it is in a non-execution state for the one-chip microcomputer with the ROM. Thereafter, since the RS flip-flop 23 holds "0" until the instruction 2 is executed, the non-executed state of the ROM built-in one-chip microcomputer continues.

Next, the ROM address is sequentially incremented, the address Y is designated by the address register 16, and the ROM cell section 15 is designated.
Considering the case where instruction 2 is selected from
And taken into ID22 through IR21. The ID 22 detects the instruction 2 when the instruction 2 is input, and outputs a detection signal to the R (reset) terminal of the RS flip-flop 23 through the instruction code detection signal line 26. The RS flip-flop 23 receives this and outputs a “1” level signal, which is supplied to an AND circuit in the control signal output circuit 24 through the RS flip-flop output line 27. As a result, the control signal generated by the control signal output circuit 24 is determined by the output signal from the ID 22 supplied to the other input of the AND circuit. That is,
For a one-chip microcomputer with a built-in ROM, it is in a normal execution state. Thereafter, since “1” is held by the RS flip-flop 23, the one-chip microcomputer with a built-in ROM enters a normal execution state.

〔The invention's effect〕

As described above, according to the present invention, the BT screening can be performed by setting the data portion in the internal ROM to the non-execution state and executing only the instruction group, so that the BT screening with higher reliability can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is a diagram illustrating an example of a memory map of a ROM. 11: Control signal, 12: Jump ROM address signal, 13
…… Gate circuit, 14… ROM address decoder, 15…
... ROM cell section, 16 ... ROM address register section, 17 ... RO
M output circuit section, 18 internal data bus, 19 sequential ROM address signal, 20 ROM address input signal, 21 instruction register, 22 instruction decoder, 23 RS flip-flop, 24 Control signal output circuit section.

Claims (1)

(57) [Claims] An internal operation based on the execution of an instruction read out from a ROM in which a command or data is stored in advance is performed during a normal time, and the internal operation is performed during a BT screening.
When the instruction read from the ROM is a branch instruction, in a microcomputer with a built-in ROM that disables or disables the execution of the branch instruction and continuously executes the instruction at the next address, Means for decoding and detecting the first and second instructions for prohibiting execution and permission for execution, respectively, and disabling or disabling execution of instructions other than the first and second instructions in accordance with the respective detection signals of the means. Means for holding and outputting a signal.