JPH02302855A - Memory control system - Google Patents

Abstract

PURPOSE:To simplify processing procedure and to shorten a processing time by writing data in one memory out of two memories using an address bus and a data bus in common and having the same storage capacity, and at the time of detecting the validity of a data attribute, switching a write command and a read command and reading out the data written in one memory. CONSTITUTION:In the 1st and 2nd memories 1, 2 using the address bus 100 and the data bus 101 in common and having the same storage capacity, the validity of the attribute of data is detected at the time of writing the data in the 1st memory 1, and when the validity is detected, the write command to the 1st memory 1 is switched to a read command from the 2nd memory 2 and the data written in the 1st memory 1 are read out. Consequently, the processing procedure for writing write data in the memory in simplified and the processing time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a memory control method, and more particularly to a memory control method for protecting memory when writing data to a memory.

Conventional technology Conventionally, in this type of memory control method, in order to protect the data stored in memory, write data is once taken into a register, and the attributes of the write data are determined using modifiers added to the data. Generally, a comparison is performed, and the write data can only be written to the memory when the comparison result is correct.

In conventional memory control methods like this, the write data is loaded into the register, compared, and then written to the memory again, so the processing steps until the writing of the write data to the memory is completed are becomes complicated and takes a long time to complete,
When it is necessary to read write data from the memory, there is a drawback that it is necessary to compare the attributes of the write data in line 9 and then wait for reading until the writing to the memory is completed.

OBJECT OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional methods as described above, and provides a memory control method that can simplify the processing procedure when writing data to memory and shorten the processing time. For the purpose of providing.

Structure of the Invention A memory control method according to the present invention includes first and second memories having the same storage capacity that share an address bus and a data bus, and an attribute of the data when writing data to the first and second memories. a detecting means for detecting validity; and controlling to give a read instruction to the second memory when giving a write instruction to the first memory;
control means for switching the write instruction and the read instruction to the first and second memories in accordance with the detection result of the detection means; When writing is performed and the validity of the attribute of the data is detected by the detection means, the control means switches the write instruction and the read instruction to the first and second memories, It is characterized in that the data written in the memory of the device is not read out.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, memories 1 and 2 share an address bus 100 and a data bus Lot, and have the same storage capacity.

The attribute comparator 3 compares the attributes of the data written into the memory 1.2 manually via the data bus lot, and sends the comparison result to the flip-flop circuit 4 and a host device (not shown) via the signal line 04. Output.

The flip-flop circuit 4 uses signal lines 105 and 108 for each word of the memories 1 and 2 based on the address input via the address bus 100 and the comparison result from the attribute comparator 3 input via the signal line 104. When instructing memory 1 to read, it instructs memory 2 to write, and inverts the instruction in accordance with the comparison result from attribute comparator 3.

The selector 5 selects data buses 102.1 from each of the memories 1 and 2.
03 is selected according to an instruction from the flip-flop circuit 4 inputted via the signal line 105, and the read data is sent to the host device via the data bus 107. Send to.

FIG. 2 is a block diagram showing the configuration of the flip-flop circuit 4 of FIG. 1. In the figure, when the comparison result from the attribute comparator 3 indicating the attribute result is "1", that is, the attribute of the write data is correct, the address decoder 41 of the flip-flop circuit 4 decodes the write address of the data, and Flip-flop 42- corresponding to
The value of i (i=1°2, . . . , n) is inverted at the same time as data writing is completed.

The flip-flop 42-1 has a one-to-one correspondence with the address input via the address bus 100, and sets the value input from the address decoder 41 via the signal line 110-i, and outputs the value. It is output to the selector 43 via the signal line 111-i.

Based on the address input via the address bus 100, the selector 43 selects the value of the flip-flop corresponding to the address from among the values of the flip-flop 42-1 sent via the signal line lLi1, and selects the value of the flip-flop corresponding to the address. The value of the output voltage is outputted to the memory 1, the selector 5, and the inverter 44 via the signal line 105, respectively.

Inverter 44 inverts the value from selector 43 and sends the inverted value to memory 2 via signal line 106.

The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

First, for initial state setting, the flip-flop circuit 4
When is reset, the flip-flops 42-I of the flip-flop circuit 4 become "0", the memory 1 is instructed to read by the flip-flop circuit 4, and the memory 2 is instructed to write by the flip-flop circuit 4, and the flip-flop circuit 4 instructs the memory 2 to write. , the selection circuit 5 selects the read data from the memory 1.

Note that when the value of the flip-flop 42-1 becomes "1" due to the reset of the flip-flop circuit 4, writing is instructed to the memory 1, reading is instructed to the memory 2, and the selector 5 selects the memory 2. Read data from is selected.

After setting this initial state, when a write address and write data are input via the address bus 100 and the data bus 101, the flip-flop circuit 4 applies the write address to the memory 2 to which writing is instructed. An operation to write the write data to the specified address is performed, and in parallel with this write operation, the attribute comparator 3
The attributes of the write data are compared.

As a result of the attribute comparison in the attribute comparator 3, if it is determined that the attribute of the write data is correct, the flip-flop of the flip-flop circuit 4 corresponding to the write address is completed at the same time as writing of the write data is completed. At the same time, when the value of the memory 2 corresponding to the write address is inverted and the word in the memory 2 corresponding to the write address becomes the read state, the word in the memory 1 corresponding to the write address that has been in the read state is changed to the write state from now on. become a state.

After that, when reading data at the same address as this write address, the selector 5 selects the flip-flop circuit 4.
Since the data to be read from the memory 2 is selected by the instruction, the data written to the memory 2 by the above-described operation is read out as is.

Furthermore, when writing data to the same address as this write address, the data is written to the specified address of the memory 1 instructed by the flip-flop circuit 4, in the same manner as the above-mentioned operation. In parallel with this write operation, the attribute comparator 3 compares the attributes of the data.

As a result of the attribute comparison in the attribute comparator 3, if the attribute of the data is determined to be correct, the flip-flop 42-i of the flip-flop circuit 4 corresponding to the address is activated at the same time as writing of the data is completed. be reversed.

The above control is performed for each word of each memory 1.2 using the flip-flop 42-1 of the flip-flop circuit 4.

If it is determined that the attribute of the data is incorrect as a result of the attribute comparison in the attribute comparator 3, the data is written to the memory specified by the flip-flop circuit 4, but the attribute comparator 3 Since the comparison result is 0'', the flip-flop 42 of the flip-flop circuit 4
Since -1 is not inverted, the data in the memory in the read state is not destroyed, and the data is normally protected.

In this case, by reporting the comparison result of the attribute comparator 3, that is, the fact that the attribute of the write data is incorrect, to the higher-level device (-9=), the higher-level device can detect the error of incorrect attributes.

In this way, address bus 100 and data bus 10
When data is written to the memory 1 in the memories 1 and 2 that share the memory 1 and have the same storage capacity, the attribute comparator 3 detects the validity of the attribute of the data, and based on the detection result. When the validity of the attribute of the data is detected, the write state of the memory] is changed to the read state according to an instruction from the flip-flop circuit 4, the read state of the memory 2 is set to the write state, and the data written in the memory 1 can be read. By doing so, each word of memories 1 and 2 can be used alternately as read memory or write memory.

Therefore, when data is written to the memories 1 and 2, storage protection can be performed normally and in the cylinder.

In addition, since the attribute comparator 3 compares the attributes of the data in parallel with writing the data, the processing procedure until the writing of the data to the memory 1.2 is completed can be simplified. The time can be significantly reduced.

Furthermore, if the validity of the attribute is detected as a result of the comparison of the attributes of the data that is performed in parallel with the writing of the data, the memories 1 and 2 are placed in the read state at the same time as the writing of the data is completed. It is possible to read out data from the memories 1 and 2 without having to wait until the writing of data, which is performed after attribute comparison, is completed, as in the conventional case.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, data is written to the first memory in the first and second memories that share an address bus and a data bus and have the same storage capacity. When the validity of the attributes of the data is detected, and as a result, when the validity of the attributes of the data is detected, switching between a write instruction to the first memory and a read instruction to the second memory is performed. By reading the data written to the first memory using the first memory, the processing procedure when writing data to the memory can be simplified and the processing time can be shortened. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of the flip-flop circuit of FIG. 1. Description of symbols of main parts 1.2...Memory 3...Attribute comparator 4...Flip-flop circuit 5...Selector 41...・Address decoder 42-1 to 42-n...Flip-flop 43
...Selector 44 ...Inverter

Claims (1)

[Claims] (1) first and second memories having the same storage capacity that share an address bus and a data bus, and a detection means that detects the validity of the attributes of the data when writing data to the first and second memories; , when giving a write instruction to the first memory, a read instruction is given to the second memory, and according to the detection result of the detection means, the write instruction to the first and second memories and control means for switching the read instruction; when the data is written into the first memory under the control of the control means and the validity of the attribute of the data is detected by the detection means; The control means controls the first
and a memory control system characterized in that the write instruction and the read instruction to the second memory are switched to read data written to the first memory.