JPH03105630A - Error correcting system - Google Patents

Abstract

PURPOSE:To improve the retry rate by executing such an error correction as correct data in the other file in which there is no error is written in a file in which an error is generated, in the case of an error is generated in one file of duplexed register files. CONSTITUTION:In a register file 1 and 2, the same data is stored in the same address of each of them. For instance, when an error is not detected in an error check circuit 5, and an error is detected in an error check circuit 6, a read address selector 9 and a write address selector 12 are switched by the output of an AND gate 8, and in both of them, an output of a read address register 4 is selected. Subsequently, from the register file 1 in which an error is not detected, correct data is read out to a signal line 107, and correct data is re-stored in the address in which an error is detected in the register file 2. In such a way, the error is recovered effectively, and the retry rate can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to error correction systems, and more particularly to systems for correcting errors occurring in software-visible registers within an IF_N processing unit.

2. Description of the Related Art In general, information processing apparatuses often have two software-visible register files of the same configuration because it is necessary to read different addresses at the same time. Examples of such structures include one register file with two read ports, two slave latches each, or two identical register files.

Then, a parity check was performed on each output. Additionally, if an error is detected as a result of the parity check, a hardware error interrupt will be generated.
Error angle analysis and retry work are performed using a microprogram or diagnostic device.

In the conventional error handling method for information processing devices described above, in order to repair the value of the register file where the error occurred, the software instruction is traced back and written to the address of the register file where the error has occurred. The software instruction must be executed again. However, if the processing has progressed several instructions after that, it is very difficult to return to the write instruction, and there is a drawback that the retry rate is low.

OBJECTS OF THE INVENTION The present invention has been made to overcome the above-mentioned conventional drawbacks, and its purpose is to provide an error correction system that can effectively repair errors and improve the retry rate.

Structure of the Invention The error correction system according to the present invention is an error correction system that corrects errors in each data in first and second storage means in which the same data is stored at the same address, and that an error detection means for detecting an error in the data being read; and an error detection means detecting an error in the data read in response to a read command to the first storage means.
addressing means for setting the read address of the storage means as the read address of the second storage means; and addressing the data from the second storage means specified and read by the addressing means to the first storage means. The device is characterized in that it has means for writing to the same address as the read address.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of the main parts of an information processing apparatus including an embodiment of an error correction system according to the present invention.

In the figure, an information processing apparatus employing an error correction system according to an embodiment of the present invention includes register files 1 and 2.
, read address registers 3 and 4, error check circuits 5 and 6, AND circuits 7 and 8, read address selectors 9 and 10, and write address selector 1.
1 and 12, and write data selectors 13 and 14. It is assumed that the write address is given via a signal line 101 from a CPU (not shown), and the write data is given via a signal line 102. Furthermore, the register files 1 and 2 may be well-known memory circuits constituted by RAM, but are not limited thereto.

Both register files 1 and 2 are 32-bit, 4-parity, 16-word, software-visible general-purpose register files.

Read address registers 3 and 4 are registers that hold read addresses of register files 1 and 2, respectively.

Error check circuits 5 and 6 are connected to register files 1 and 6, respectively.
Read data 10 which is output from register file 2
7. This circuit performs 108 parity checks.

AND gates 7 and 8 as well as read address selectors 9 and 10 respectively control register files 1. It has a function as a selection circuit for a read address to 2.

Write address selectors 11 and 12 are circuits for selecting write addresses to register files 1 and 2, respectively.

The write data selectors 13 and 14 are respectively circuits for selecting write data to the register file 1.2.

In this structure, the normal write operation is an operation in which write data on the signal line 102 is written to the write address specified by the signal line 101 in both the register files 1 and 2. In other words, the same data is stored in the register files 1 and 2 at the same address.

In addition, the normal read operation is a read operation from the address specified by the output of the read address register 3 for register file 1, and a read operation from the address specified by the output of the read address register 4 for register file 2. It is.

Furthermore, read data 1 from register file 1
07 is input to the error check circuit 5, and a parity check is performed based on the parity bit. On the other hand, read data 108 from the register file 2 is input to the error check circuit 6, and a parity check is performed in the same way. will be held.

1] In normal times, in response to requests from two lower-level devices (not shown), the upper-level device (not shown)/a C
The PU specifies different read addresses for register files 1 and 2, and sends out different read data. In other words, high-speed access is achieved by duplicating the held data.

Next, the operation when an error occurs will be explained. Assume now that the error check circuit 5 does not detect an error, but the error check circuit 6 detects an error. Then,
The operation of the lower-level device is suppressed, and the signal line 103
The logic level of the signal line 104 is '0' and the logic level of the signal line 104 is '1'.
", and the logic level of the output signal line l06 of the AND gate 8 becomes "1 degree. As a result, the read address selector 9 for register file 1 and the write address selector 12 for register file 2 are switched, and the output of read address register 4 is selected for both.

In other words, the address where the error was detected in register file 2 is used as the read address in Refsta file 1.
In addition to being specified as the write address, it is also specified as the register fill 2.

Then, correct data is read onto the signal line 107 from the register fill 1 in which no error was detected. Here, the write data selector 14 for the register file 2 selects this signal line 107 because the logic level of the output signal line lO6 is "1°" as described above. Correct data is restored to the address where the error was detected.

At this point, the error correction operation is completed by performing a read operation on the register file 2 and releasing the operation inhibition for the lower-order device. It is clear that the retry rate is improved by performing the above operations.

Also, when an error occurs in the register file 1, the logic level of the signal line 105 becomes "1", and the read address selector 10, write address selector 1
1. The write data selectors 13 are respectively switched, correct data is stored, and error correction operations are similarly performed.

Although the present embodiment has been described with reference to the case where there are two register files serving as storage means, it is clear that the same configuration can be made in the case where there are three or more register files.

Effects of the Invention As explained above, in the present invention, when an error occurs in one of the duplicated register files, the correct data in the other register file with no error is read out and the correct data is read out from the other register file where the error occurred. Error correction by writing to the corresponding address in the register file has the effect of improving the retry rate.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the main parts of an information processing apparatus including an error correction system according to an embodiment of the present invention. Explanation of symbols of main parts 1.2・・・Register file

Claims (1)

[Claims] (1) An error correction system that corrects errors in each data in first and second storage means in which the same data is stored at the same address, the system corrects errors in data respectively read from the storage means. an error detection means for detecting, and when an error is detected in the data read in response to a read command to the first storage means, the error detection means sets the read address of the first storage means to the first storage means; addressing means for setting the read address of the second storage means; and writing data from the second storage means specified and read by the addressing means to the same address as the read address of the first storage means. 1. An error correction system characterized in that the error correction system has: