JPS63279348A - Check system for memory - Google Patents

Abstract

PURPOSE:To accurately detect the illegal read data by using 1st and 2nd read data registers, and comparing the contents of the 2nd read data register with a check bit for check of the read data. CONSTITUTION:A 1st read data register 12 is provided together with a 2nd read data register 13. The read data given from a memory array 10 is held and a part of this data output is sent to a CPU 32. While the another part of said output is sent to the CPU 32 via a correction circuit 16 after correction of a 1-bit error if produced for selection of the read data, the corrected data or the input data received from the CPU 32. In a reading state, the read data is selected and used for generation of a check bit. This produced check bit is compared with another check bit produced from the read data by an ECC check circuit 15. The result of this comparison is sent to the CPU 32. Thus it is possible to check easily and accurately the discordance of data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a storage device used in an information processing device, and particularly to failure detection thereof.

(Prior Art) Various methods have been proposed for improving the access time, which indicates the performance, of storage devices used in information processing devices.

One of these methods is to speed up the memory elements that make up the storage device, from dynamic RAM to static RAM.
Changes have been made to AM, and peripheral circuits have been changed to LSI and larger in size. For storage devices in small devices, the cost cannot be increased, so TTL elements and standard dynamic RAM are used.
Since it uses 100K, the access time is slower than that of large machine storage devices. Therefore, attempts have been made to improve the access time by changing the circuit configuration.

FIG. 2 is a block diagram showing an example of a read data section of a storage device according to the prior art. In Figure 2, 10
0 is a memory array, 101 is a first read data register, 102 is a second read data register, 103 is a parity generation circuit, 104 is an ECC check circuit, 11g
is a correction circuit for 1-bit error correction, 106 is a data register, 107 is a parity register, 108 to 11
1 is a drive gate for sending data to the CPUI 12, and 112 is a CPU.

The data system circuit in FIG. 2 accesses read data from the memory array 100 at high speed.Before checking by the KECC check circuit 104, the data system circuitry in FIG. Data is sent to the CPU 112 via the CPU 112. At that time, the signal line 102
The signal line 202 enables the drive gates 108 and 109, and the signal line 202 disables the drive gates 110 and 111. However, the access time can be improved by the ECC error checking time (generally one clock period).

As a result of the check by the ECC check circuit 104, 1
If it is found that there is a bit error, signal line 2
This is notified to the CPU 112 by the SBK signal on 00, and the data is corrected by the correction circuit 105. Thereafter, the corrected data is transferred to the CPU 112 via the data register 106, parity register 10f, and drive gates 110 and 111. At this time, the signal line 201 disables the drive gates 108 and 109, and the signal line 202 enables the drive gates 110 and 111.

In FIG. 2, when the first read data register 101 fails, since there is no error in the data from the memory array 10G, the second read data register 102 and E
The error cannot be detected by the CC check circuit 104. Moreover, the parity is the first read data register 1.
Since the CPU 112 is generated based on the output result of 01, the CPU 112 cannot detect that there is an irregularity in the read data, and the data is garbled.

(Problems to be Solved by the Invention) In the nine conventional storage device checking methods described above, when the first read data register fails, the second read data register is Errors cannot be detected by the ECC check circuit and ECC check circuit. Further, since the parity is generated based on the output result of the first read data register, the CPU cannot detect any irregularity in the read data, which results in garbled data.

An object of the present invention is to hold read data from a memory array, send part of the output to the ecPU, correct the other part via a correction circuit when a 1-bit error occurs, and send the read data to the CPU. , corrected data, or input data sent from the CPU, and when reading, the read data is selected and used to generate check pits, and the check generated by the read data and the ECC check circuit is selected. By comparing the pits with the check pits generated by the generation of the check bits and sending the output to the CPU, the above drawbacks are eliminated and irregularities in the read data can be accurately detected. The purpose of the present invention is to provide a storage device checking method.

(Means for Solving the Problems) A checking method for a storage device according to an example of the present invention includes first and second read data registers, error check and correction means, selection circuit, check pit generation means, and comparison circuit. It is constructed by comprising the following.

wLl and the second read data register are for holding read data from the memory array.

The error check and correction means is for correcting and outputting corrected data when a one-pit error occurs in the contents of the second read data register.

The selection circuit is for selecting the contents of the first read data register, corrected data, or input data sent from the arithmetic processing unit.

The check bit generating means is for generating a check bit by selecting the output of the first read data register by a selection circuit during reading.

The comparison circuit is for checking the read data by comparing the contents of the second read data register with the check bit.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a storage device checking method according to the present invention.

In FIG. 1, 10 is a memory array, 11 is a buffer gate, 12 is a first read data register, 13 is a second read data register, 14 is a parity generation circuit,
15 is an FCC check circuit, 16 is a correction circuit, 17 is an output data register, 1st is a parity register, 19-2
2 are drive data), 23 and 24 are input gates, 25 are data registers that store input data and parity, 26 are partial write data selection circuits, 27
is an input data parity check circuit, 2B is a comparison circuit,
29 is an ECG generation circuit, 30 is a write data register,
31 is a write data output gate, and 32 is a CPU.

The comparison circuit 28 includes a check pit corresponding to the output of the second read data register 13 not generated by the FCC check circuit 1s and a check pit corresponding to the output of the first read data register 12 generated by the ECG generation circuit 29. Compare with pit. Drive gates 19, 21. The drive gates 20 and 22 have a 'fired OR' logic, and one of them is selected by the signal on the signal line 50 and 51. The signal line 52 is a 1-bit error signal line indicating that a 1-bit error has occurred, and the signal line 53 is a data match error signal line indicating that a data match error has occurred.

Data read from the memory array 10 is stored in the first read data register 12 and the second read data register 13 via the buffer 11e. The output of the first read data register 12 is immediately applied to the parity generation circuit 14, where parity is generated, and the output of the first read data register 12 is sent to the CPU 32 together with the parity via the drive gate 19.20. be done.

During this time, the data stored in the first read data register 13 is sent to the FCC check circuit 15 and checked.

As a result, if a 1-bit error is detected, the correction circuit 16 corrects the data and the CPU 3
2, a 1-bit error signal indicating the occurrence of a 1-bit error is notified via signal #52ft. The corrected data is stored in the output data register 1f, and a parity pit for the data is generated by the FCC check circuit ISK and stored in the parity register 18. These data and parity are sent to the CPU 32 via the drive gates 21 and 22 by a clock after IT of the clock to which the output of the first read data register 12 is sent.

At this time, the signal line 50 is in a non-selected state and the signal line S1 is in a selected state. If a 1-bit error does not occur, the output of the first read data register 12 becomes valid and the CPU 32 executes the process.

The output of the first read data register 12 is sent to a partial write data selection circuit 26, which is configured to select the data in the read mode. During partial writing, the selection circuit 26 selects the output of the input data register 2S for bytes for which the write instruction byte signal is set, and stores corrected data for bytes for which the write instruction byte signal is not set. The output of the output data register 17 is selected. In the read mode, the output of the first read data register 12 is selected for all bytes and sent to the ECG generation circuit 29. The ECG generation circuit 29 generates check pits for the output data.

The FCC check circuit 15 performs ECC on data other than the check bit of the second read data register 13.
Those skilled in the art can easily guess that the matrix calculation results are output.

This calculation result is the same as the check bit calculation formula generated by the ECG generation circuit 11I29. Therefore, the output of the ECG generation circuit 29 based on the output of the first read data register 12 and the ECC check circuit 1
The output result of the output of the second read data register 13 by the partial circuit No. 5 will be the same if the stored results of the first read data register 12 and the second read data register 13 are the same. By comparing the check bits by the comparison circuit 28, it is possible to check for data mismatch. By notifying the CPU 32 of the comparison result via the t-signal line 53, serious data corruption can be avoided.

(Effects of the Invention) As explained above, the present invention holds read data from a memory array, sends a part of the output to the CPU,
When a 1-bit error occurs, the other part is corrected and sent to the CPU via a correction circuit, and read data, corrected data, or input data sent from the CPU is selected, and when reading, it is read out. Select the data and use it to generate a check bit, compare the check bit f′ generated by the read data and the FCC check circuit with the check bit generated by the generation of the check bit, and send it to the CPU. This has the advantage that data inconsistency can be checked more easily and accurately.

[Brief explanation of the drawing]

FIG. 1 is a four-dimensional diagram showing an embodiment of the storage device checking method according to the present invention. FIG. 2 is a block diagram showing an example of implementing a storage device checking method according to the prior art. 10.100...-Memory array 11...Buffer gate 12.13.17.25.30,101. 102.106・FistΦ・・Data register 14.103
...Parity generation circuit 15.104...ECC check circuit 16.108.
・・Correction circuit 111.1 (1・Fist・Parity register 19 to 22.1
08~111e・-Drive gate 23.24---Manual gate 26...Selection circuit 27...Parity check circuit 28...Comparison circuit 29...ECG generation circuit 31...Output gate 32.112 ...processing equipment

Claims (1)

[Claims] The first one for holding read data from the memory array.
and a second read data register, an error check and correction means for correcting and outputting corrected data when a 1-bit error occurs in the contents of the second read data register, and the first read data register. a selection circuit for selecting the content of the data, the corrected data, or input data sent from the arithmetic processing unit, and at the time of reading, the selection circuit selects the output of the first read data register and sets a check bit. and a comparison circuit for comparing the contents of the second read data register and the check bit to check the read data. Circuit check method.