JPH0520215A - Information processor - Google Patents

Abstract

PURPOSE:To detect a 2-bit error and to detect a failure in an error correcting circuit or the like by executing normal operation at the same time as the case of no error correction. CONSTITUTION:An output from an error correction code forming circuit 9 is written in an SPM 4 with the delay of one step from data written from a data register 2 to an SPM 1. An error correction code is read out from the SPM 4 with the delay of one step from the data read out from the SPM 1. An output from a data register 3 is checked by a parity checking circuit 8, and if an error is present on the output, an error correcting circuit 7 corrects the error and stores the corrected data in data registers 3, 6, 2. The contents of the register 2 are written in the SPM 1, the formed error correction code is stored in a data register 5 and then the output of the register 5 is written in the SPM 4 to complete the error correction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a memory error correction system.

[0002]

2. Description of the Related Art Generally, in an information processing apparatus of this type, a scratch pad memory (hereinafter referred to as SPM) is used by a firmware to directly store and read operation data and when swapping data, and therefore read and write at high speed. There is a need to do. But since SPM is a memory,
The speed of reading and writing is slower than that of general registers, and in order to write with the clock of the arithmetic unit, it is necessary to write directly from the register. Further, in general, since the arithmetic unit is directly connected to the preceding stage of the register for SPM writing, there is no delay margin.

FIG. 4 is a block diagram showing an example of a conventional information processing apparatus. In the case of writing to the SPM in FIG. 4, the data stored in the data register 102 is sent to the data register 103, and the error correction code creating circuit 108 creates an error correction code and stores it in the data register 104. Data register 103, 1
The data 04 is written in the SPM 101 by the write address of the address register 109. In the case of reading from the SPM, the data registers 105 and 106 are read by the write address of the address register 110. When an error is detected by the error detection / correction circuit 107, error correction is performed and the data registers 103, 10
Corrected data is stored in 4, 105, 106, and then SPM
The write error correction processing ends at 101.

FIG. 5 is a block diagram showing another example of a conventional information processing apparatus. In the case of writing to the SPM in FIG. 5, the data stored in the data register 153 is transferred to the SPM 15 by the write address of the address register 159.
Written to 1. When reading from the SPM, the data register 155 is read by the read address of the address register 160. Parity check circuit 15
When an error is found by 7, it is regarded as a failure and the function stops.

[0005]

In the configuration of an example of the above-mentioned conventional information processing apparatus, the error correction code is created by the output of the data register 102, and the data register 10 is generated.
Since it is written in the SPM 101 after being received once in 3, 104, the data is stored in the data register 102 before the S
It takes two steps to write to the PM 101. When the error correction code creating circuit 108 fails,
There is a drawback that it may not be found until the same address is read again. In addition, the configuration of another example has a drawback in that when an error is found in the parity check circuit 157, a failure occurs and the function stops.

An object of the present invention is to provide an information processing apparatus capable of performing SPM writing / reading, error correction, and early detection of a failure of an error correction circuit in a shorter time.

[0007]

An information processing apparatus according to the present invention is an information processing apparatus having a memory for holding data with a parity bit, which stores a first memory and data to be written in the first memory. A first data storage means, an error correction code creating means for creating an error correction code from the output of the first data storing means, and a second data storing means for storing the error correction code created by the error correction code creating means. Data storage means, a second memory for writing the contents of the second data storage means, third and fourth data storage means for storing data read from the first and second memories, and the second memory A parity check means for performing a parity check on the output of the third data storage means, and an error report from the parity check means for the third and fourth data check means. Comprises error correction means for performing error correction of the data storage means output, said first, and re-writing means for re-writing to the second memory.

Then, instead of the fifth data storage means for storing the output of the fourth data storage means and the error correction means, error detection and error correction of the outputs of the third and fifth data storage means are performed. And a sixth data storage means for storing the error correction code portion of the error correction means or the output of the error detection and correction means, the output of the error correction code generation means, and the It may be provided with a comparison check means for comparing the output of the sixth data storage means.

[0009]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the information processing apparatus of the present invention. In the first embodiment, an SPM1 which is a first memory, a data register 2 which is a first data storage means, an address register 12 which stores a write address whose output is written in the SPM1, and a read address which is read from the SPM1 are provided. Address register 10 to store
An error correction circuit 7 which is an error correction means, a selector 15 which selects the output thereof and the output of the SPM 1, a data register 3 which is a third data storage means which stores the output, and a parity check of the output. A parity check circuit 8 to perform, an error correction code creation circuit 9 that creates an error correction code from the output of the data register 2, a data register 5 that is the second data storage means that stores the output, and a first output that writes the output. 2 memory S
PM4, an address register 13 for storing a write address for writing the output of the data register 5 to the SPM4,
The address register 11 that stores the read address read from the SPM 4, the output of the error correction circuit 7, and the SPM 4
A selector 16 for selecting the output of the data register, a data register 6 as a fourth data storage means for storing the output, and an error correction circuit 7 as an error correction means for performing error correction from the output and the output of the data register 3. , SPM write data c as data from the arithmetic unit and the error correction circuit 7
Of the SPM write address e and the output of the address register 11, and an address control 1 for controlling the selector 17.
8 and.

Next, the operation of this embodiment will be described.
Normally, the selector 14 selects the SPM write data c,
The data register 2 stores the SPM write data c. In the next step, the output of the data register 2 is written in the SPM 1 according to the write address of the address register 12. At the same time, the error correction code creating circuit 9 creates an error correction code, and the output is the data register 5
Stored in. In the next step, the output of the data register 5 is SPM4 according to the write address of the address register 13 storing the write address of the address register 12.
Written in. That is, the error correction code corresponding to the data of SPM1 is written in SPM4 one step later than SPM1. In the case of reading, first the SPM 1 is read according to the read address of the address register 10. The selector 15 normally selects read data from the SPM 1, and this read data is written in the data register 3. Address register 1 in the next step
The error correction code is read from the SPM 4 according to the read address of the address register 11 storing the read address of 0. This error correction code corresponds to the data read from the SPM 1 one step before. This error correction code is stored in the data register 6 through the selector 16. At the same time, the output of the data register 3 is checked by the parity check circuit 8, and the output of the data register 3 is sent to a computing unit or the like. When a parity error is found by the parity check circuit 8, the data register 3 is held by the error hold signal b, and the address control 18 and the error correction circuit 7 are notified of the error. In the next step, the error correction circuit 7 performs error correction from the output data of the data register 3 and the data register 6, and the corrected data is selected by the selectors 15 and 16 and stored in the data register 3 and the data register 6, It is also selected by the selector 14 and stored in the data register 2. Address control 18 is selector 1
7 is switched and the output of the address register 11 is stored in the address register 12. In the next step, the contents of the data register 2 are written into the SPM 1 according to the write address of the address register 12, and at the same time, the error correction code creating circuit 9 creates an error correction code in the output of the data register 2 and stores it in the data register 5. In the next step, the output of the data register 5 is the address register 1
According to the write address of 3, the SPM 4 is written, the error correction is completed, and the error hold signal b is released. Therefore, with such a configuration, error correction can be performed, and normal operation can be performed with the same number of steps as in the case of a configuration without error correction.

FIG. 2 is a block diagram showing a second embodiment of the information processing apparatus of the present invention, mainly showing parts different from the first embodiment. A data register 33, which is a fifth data storage means, is added, and instead of the error correction circuit 7 shown in FIG. 1, an error detection / correction circuit 3 which is error detection / correction means.
7 is provided. The error detection / correction circuit 37 is a circuit having a 1-bit error correction / 2-bit error detection mechanism. The data register 3 is checked by the parity check circuit 8 and stored in the data register 33. Even if no error is found in the parity check circuit 8, an error is detected from the output of the data register 33 and the output of the data register 6 in the next step. Here, if there is a 2-bit error that is not found in the parity check circuit 8, this is detected and regarded as a failure. The difference from the first embodiment is that the parity check circuit 8 can detect only a 1-bit error. Therefore, even in the case of a 2-bit error that cannot be detected by the parity check circuit 8, the data register 3
3, the data register 6 and the error detection / correction circuit 37 always detect a 2-bit error, so that the error detection rate is further improved.

FIG. 3 is a block diagram showing a third embodiment of the information processing apparatus of the present invention, and mainly shows parts different from the first embodiment. A data register 41 as a sixth data storage means and a comparison check circuit 42 as a comparison check means are added. When an error is found by the parity check circuit 8, the data in the data register 3 and the data register 6 are error-corrected by the error correction circuit 7 in the next step, and the data section is stored in the data register 2.
The error correction code part is stored in the data register 41.
In the next step, an error correction code generation circuit 9 generates an error correction code from the output of the data register 2, and the output of the data register 41 and the output of the data register 41 are compared and checked by the comparison check circuit 42. If they do not match, it is considered as a failure. The difference from the first embodiment is that when the error correction code generation circuit 9 and the error correction circuit 7 fail, they can be found only by reading again with the same read address, but the output of the data register 41 and the error correction code generation circuit. By comparing and checking the output of 9 by the comparison check circuit 42, it is possible to detect at the time of rewriting and early detection of a failure can be performed.

[0013]

As described above, according to the information processing apparatus of the present invention, the error correction operation can be performed, and the normal operation can be performed in the same time as when the error correction is not performed. Also,
A 2-bit error can be detected. Further, it is possible to find a failure in the error correction circuit and the error correction code generation circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an information processing apparatus of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the information processing apparatus of the invention.

FIG. 3 is a block diagram showing a third embodiment of the information processing apparatus of the invention.

FIG. 4 is a block diagram showing an example of a conventional information processing apparatus.

FIG. 5 is a block diagram showing another example of a conventional information processing apparatus.

[Explanation of symbols]

1, 4, 101, 151 Scratch pad memory (SPM) 2, 3, 5, 6, 33, 41, 102, 103, 10
4, 105, 106, 153, 155 Data register 7 Error correction circuit 8, 157 Parity check circuit 9, 108 Error correction code generation circuit 10, 11,
12, 13, 109, 110, 159, 160 Address registers 14, 15, 16, 17, 114, 115, 116, 1
17, 118 selector 18 address control 37, 107 error detection / correction circuit 42 comparison check circuit a, h, n SPM read data b error hold signal c, i, p SPM write data e, j, q SPM write address d, k, r SPM read address f, g, l, m failure detection signal

Claims (3)

[Claims] 1. An information processing apparatus having a memory for holding data with a parity bit, comprising: a first memory;
First data storage means for storing data to be written in the first memory, error correction code creation means for creating an error correction code from the output of the first data storage means, and creation by the error correction code creation means Second data storing means for storing the error correction code, a second memory for writing the contents of the second data storing means, and a third for storing the data read from the first and second memories. , A fourth data storage means, a parity check means for performing a parity check of the output of the third data storage means, and an error of the output of the third and fourth data storage means based on an error report from the parity check means. Information processing characterized by comprising error correction means for making a correction and rewriting means for making a rewriting to the first and second memories Location. 2. The information processing apparatus according to claim 1,
Fifth data storage means for storing the output of the fourth data storage means, and error detection and correction for performing error detection and error correction of the outputs of the third and fifth data storage means instead of the error correction means. An information processing apparatus comprising: 3. The information processing apparatus according to claim 1 or 2, wherein a sixth data storage means for storing an error correction code portion of the error correction means or the error detection and correction means output, and the error correction code creation means output An information processing apparatus comprising: a comparison check means for comparing the output of the sixth data storage means.