JPH0553924A - System for testing storage device - Google Patents

Abstract

PURPOSE:To enable the test of a memory array even without a host device and to improve an error detecting rate by adding a memory scan control part, data comparator and shift control part. CONSTITUTION:Test data are set to write data registers 10-13 by using a shift control part 30 and when a memory scan control part 20 is activated, the contents of the registers 10-13 are written in a memory array 40. Afterwards, when the memory scan control part 20 is switched for read and activated, a data comparator 80 compares read data 200 from the memory array 40 with the contents of the write data registers 10-13. The tested result is decided by conditions that no error is detected by an ECC (Error Correction Code) error detecting/correcting circuit 70 or unmatch is not detected at the result of the data comparator 80.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for a storage device, and more particularly to a test method for a storage device which receives data write or read requests from a plurality of request sources.

[0002]

2. Description of the Related Art Conventionally, a test system for this type of storage device is
As shown in FIG. 2, after the write data selector 50 selects write data 0 to 3 from the 0th to 3rd request sources, E
After the CC code is generated by the ECC generation circuit 60, the data is written to the memory array 40, and when the data is read, the data is read from the memory array 40, and the ECC error detection / correction circuit 70 checks the ECC code and corrects the error and reads the data. In the storage device that returns the data 200 to the request source, when the normality test of the memory array 40 is performed,
It is necessary to write and read test data.
The test data is written and read from one of the third request sources.

For example, from the request source (0) to the memory array 40
When the test is performed, the corresponding write data 0
The test data is input to the memory array 40, selected by the write data selector 50, and written to the memory array 40. As the test method, the written test data is stored in the memory array 4
This is performed by reading from 0 and returning read data 200 to the request source, and confirming that the request source does not report an error from the storage device or compares the data with an expected value and that the read data matches. Be done.

[0004]

The above-mentioned conventional storage device test method cannot be tested unless a request source, which is a higher-level device, exists. Therefore, a system operation cannot be performed unless a system request source exists. There is a drawback that the test cannot be performed when the request source is logically / physically separated.

[0005]

According to the test method of the present invention, data is written and read from a plurality of request sources, and the ECC
A memory device having a generation circuit and an error detection / correction circuit has a memory scan control unit, a data comparator and a shift control unit.

[0006]

FIG. 1 is a block diagram showing an embodiment of the present invention. What is different from FIG. 2 is write data registers 10-13.
Of the memory scan controller 20 for writing or reading the contents of the memory array 40 to or from the memory array 40, and a data comparison for comparing the read data 200 from the memory array 40 with the contents of the write data registers 10-13. And a shift controller 30 for setting test data in the write data registers 10 to 13 using a scan path.

The test method is to set the test data in the write data registers 10 to 13 using the shift control unit 30,
By activating the memory scan control unit 20, the contents of the write data registers 10 to 13 are written in the memory array 40. After that, the memory scan control unit 20 is switched for reading and activated, so that the read data 200 from the memory array 40 and the contents of the write data registers 10 to 13 are compared by the data comparator 80.

Judgment of the test result is that no error is detected by the ECC error detection / correction circuit 70 or that no mismatch is detected by the result of the data comparator 80.

[0009]

As described above, according to the present invention, by adding the memory scan control unit, the data comparator and the shift control unit, the memory array can be tested without the host device. Further, by connecting to a plurality of request sources and having a plurality of write data registers, it is possible to set a plurality of types of test data and to increase the error detection rate.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 10 to 13 write data register 20 memory scan control unit 30 shift control unit 40 memory array 50 write data selector 60 ECC generation circuit 70 ECC error detection / correction circuit 80 data comparator 200 read data 300 match signal

Claims (1)

[Claims] 1. Data is written to and read from a memory array from a request source such as a plurality of central processing units, and a write data register corresponding to each request source is provided to store data written in the memory array. On the other hand, ECC (Error) added for error detection and correction
E to generate a Correction Code)
In a test method of a memory device having an ECC error detection / correction circuit that detects whether or not there is an error in the data read from the CC generation circuit and the memory array, and corrects the error if there is an error, ) When writing data to the memory array, when writing and reading the contents of the plurality of write data registers to the memory array, the data is read from the memory array, and the ECC error detection / correction circuit (B) When data is read from the memory array using the memory scan control unit, the read data is compared with the contents of the plurality of write data registers. And a data comparator for detecting whether or not they match each other, and (C) a data path using a scan path for the plurality of write data registers. Test method storage device which comprises a shift control section to set the.