JPH11167497A - Device and method for detecting memory rewrite operation error - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the rewrite time by providing a means such as a rewrite means rewriting an inspection bit output corrected by an inspection bit error correction means to a storage element without through an error correction/ detection circuit. SOLUTION: When data and the inspection bit, which are corrected by error correction circuits 6 and 7, a supplied and stored to/in a read data storage register 202, a selector 3 selects output data of the read data storage register 202 and supplies it to a write data storage register 102. The write data storage register 102 stores output data of the selector 3 and outputs write data and the inspection bit to the memory array 4 at a prescribed timing. Thus, an ECG circuit 2 generating the inspection bit can be bypassed at the time of rewriting by newly providing the error correction circuit 7 to the inspection bit added to read data. Thus, rewriting time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction / detection circuit (ECC circuit: Error Correcting Code, hereinafter referred to as ECC circuit).
In particular, the present invention relates to a memory rewrite operation error detection apparatus and method for correcting an ECC circuit and rewriting a storage element when an error occurs in read data.

[0002]

2. Description of the Related Art Conventionally, a soft error of a memory element (for example, a phenomenon in which stored data is inverted by α rays or the like, but an error which can be completely restored by rewriting)
As a countermeasure, a method of improving the reliability of a storage device by providing an ECC circuit, performing error detection / correction on data read from the storage element, and rewriting the storage element is generally used.

As a conventional technique of this kind, for example, there is one described in Japanese Patent Application Laid-Open No. 07-07114. The invention (rewriting operation to the storage element) described in JP-A-07-073114 will be briefly described with reference to FIG.

FIG. 3 is a block diagram showing a configuration of a conventional memory rewrite operation error detecting device.

[0005] The conventional memory rewrite operation error detecting device shown in FIG.
, An ECC circuit 13, a timing circuit 14, a data register 15, an external input / output buffer 16, an address register 17, a three-state buffer 18, and a write data selection circuit 19.

The main processing unit 11 supplies a read address 301 to the address register 17 and performs a read signal 303 to perform a read operation from the memory 12.
To address register 17, memory 12, ECC circuit 1
3, data register 15, and 3-state buffer 1
8 respectively. The address register 17 supplies the read address 305 to the memory 12.

The data read from the memory 12 is E
After being supplied to the CC circuit 13 and subjected to error correction processing,
The data is stored in the data register 15. ECC circuit 1
3 supplies a rewrite instruction signal 309 to the timing circuit 14 when performing error correction.

The timing circuit 14 to which the rewrite instruction signal 309 has been supplied starts the rewrite operation, and supplies the data stored in the data register 15 to the ECC circuit 18 via the write data selection circuit 19. ECC
The circuit 13 adds check bits to the supplied data, and supplies write data and check bits to the memory 12.

The memory 12 has an address register 1
Then, the data supplied from the ECC circuit 13 is written to the address specified by the read address 305 supplied from.

[0010]

According to the above-mentioned prior art, after error detection / correction of read data is performed, write data is again input to an error detection / correction circuit to generate an error detection / correction check bit. Therefore, there is a problem that it takes a long time to perform a rewrite operation after error detection / correction of read data.

When a failure occurs in a circuit (error detection / correction circuit) for generating a check bit of data to be rewritten to a storage element such as a memory, the rewrite operation is always started, As a result, a correctable error is embedded in the storage element every time writing is performed, and a correctable error is always detected in a read operation from the storage element, and a rewrite operation is necessarily performed. However, there is a problem (defect) that the performance (processing speed and the like) of the device is lowered and desired reliability cannot be obtained by rewriting to the storage element.

An object of the present invention is to provide an ECC circuit as a countermeasure against soft errors in a storage element such as a memory, and to provide a storage control circuit for rewriting the storage element when a correctable error occurs. A memory rewrite operation error detection device that can improve rewrite operation performance (processing speed) and can obtain desired reliability without lowering the performance of a storage device even when a failure occurs in an error detection / correction circuit. And a method.

[0013]

In order to achieve the above object, a memory rewrite operation error detection device according to the present invention includes an error correction / detection circuit as a measure against soft errors in a storage element, When an error occurs in read data, in a memory rewrite operation error detection device having a function of correcting the read data and rewriting the storage element, a test for correcting an error for a check bit added to the read data is performed. Bit error correction means, and rewrite means for rewriting the check bit output corrected by the check bit error correction means to the storage element without passing through the error correction / detection circuit. It is characterized by comprising.

The memory rewrite operation error detection method of the present invention includes an error correction / detection circuit as a countermeasure against a soft error of the storage element. In a memory rewrite operation error detection device having a function of performing a rewrite operation and performing a rewrite operation on a storage element, an error for a check bit added to read data is corrected, and the corrected check bit output is output as the error. It is characterized in that rewriting is performed on the storage element without passing through a correction / detection circuit.

According to the above-mentioned invention, an error correction circuit is provided for a check bit added to data following from the storage element, and the error-corrected check bit is used at the time of rewriting to rewrite the storage element. By bypassing the test bit generation circuit (ECG circuit) that is sometimes added, the time required for the rewrite operation is reduced. In addition, by bypassing the ECG circuit at the time of rewriting, even if a correctable failure occurs in the ECG circuit, the ECG circuit can be rewritten to perform the ECG operation.
Circuit failure can be relieved, and the reliability of the storage device is improved.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory rewrite operation error detecting device according to the present invention.

The memory rewrite operation error detecting device according to the present invention shown in FIG. 1 has a write data storage register 101 to which write data 100 is input, an output data of the write data storage register 101 to be input, and an ECC.
An error detection / correction check bit generation circuit (hereinafter, referred to as an ECG circuit) 2 for generating check bits necessary for realizing the function, and an output data of the ECG circuit 2 and the run-out data storage register 202 are input. A selector 3 for selecting one of them, a write data storage register 102 to which an output of the selector 3 is input, and a memory array 4 for storing output data of the write data storage register 102
, A read data storage register 201 to which read data of the memory array 4 is input, and an input of output data of the read data storage register 201 to detect and correct a plurality of bits of errors by a preset ECC function. If there is an error, an error detection circuit 5 that outputs the error information, and an error for the data that receives the error information of the error detection circuit 5 and corrects read data or check bits based on the error information. Correction circuit 8
And an error correction circuit 7 for check bits, and a read data storage register 202 which receives output data of the error correction circuits 8 and 7 and outputs read data 200.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 2 is a timing chart for explaining the operation of the memory rewrite operation error detecting device according to the present invention. Note that the timing chart shown in FIG. 2 shows the operation of the memory rewrite operation error detecting device of the present invention when the check bit read from the storage element has a correctable error. In addition, since the purpose of the present invention is a rewrite operation to a storage element, description of a normal write operation and a normal read operation is omitted.

First, read data and check bits read from the memory array 4 are stored in the read data storage register 201. Error detection circuit 5
Detects whether there is an error in the read data and the check bit which are the output data of the read data storage register 201 by a predetermined ECC function,
Error information is sent to the data error correction circuit 6 and the check bit error correction circuit 7, respectively. In the present embodiment, the case where the check bit has a correctable error has been discussed, so that only the check bit error correction circuit 7 is supplied with error information.

The data error correction circuit 6 and the check bit error correction circuit 7 correct errors based on the error information supplied from the error detection circuit 5, and output the corrected data and check bits to store the data. Supply to register 202. Finally, the read data storage register 202 outputs the output data as read data 200 to a host device such as a central processing unit (not shown). Thereby, the read operation from the memory array 4 is completed.

Next, the rewrite operation will be described. As described above, the read data storage register 202 is supplied with the corrected read data and the check bit from the error correction circuits 6 and 7, and outputs the output data as the read data 200, such as a central processing unit (not shown). In this case, when the corrected data and check bits are supplied and stored by the error correction circuits 6 and 7 to the read data storage register 202, the selector 3 The output data of the read data storage register 202 is selected and supplied to the write data storage register 102.

After storing the output data of the selector 3, the write data storage register 102 outputs the write data and the check bit to the memory array 4 at a predetermined timing. Upon completion of the read operation and the write operation, a series of rewrite operations to the storage element is completed.

The point of the present invention is that the error correction is performed only on the data in the prior art, whereas the error correction circuit 7 for the check bits added to the data is provided in the present invention, The point is that error correction is performed on the check bits.

Originally, the storage device improves the reliability of the storage device by adding a check bit to the write data transmitted from the host device and further having an error detection / correction function. Therefore, it is sufficient for the read data to be output to the host device to correct the error only in the data portion, and the check bits added to the read data are corrected even though they have an error detection function. Since there is no need, the error information of the check bit has not been effectively used.

However, according to the present invention, the rewriting time can be shortened by effectively utilizing the error information of the check bit, providing the error correction circuit 7 for the check bit, and bypassing the ECG circuit 2 at the time of rewriting. Can be achieved.

Further, in the present invention, even if a correctable fault occurs in the ECG circuit 2, the fault can be removed by performing a rewrite operation. That is, EC
Assuming that a correctable fault has occurred in the G circuit 2, in a write operation from a higher-level device to a storage element, an ECC
In order to realize the function, it always passes through the ECG circuit 2 and generates a check bit added to write data. At this time, the ECG circuit 2 in which the correctable fault has occurred writes the correctable fault data to the memory array 4 to generate (output) write data (including a check bit) in which the correctable fault is latent. become.

In this state, when the rewrite operation is started, the correctable fault is corrected once in the prior art.
At the time of rewriting, the data is passed through the ECG circuit again.
Array 4 will be written. Therefore, no matter how many times the rewrite operation is started, it is impossible to recover the correctable failure data (correct data is written), whereby the rewrite operation is always started, and the storage is performed. In addition to causing a decrease in device performance, if another correctable fault occurs (a soft error of a storage element can also be one cause of failure), an uncorrectable fault occurs, and in the worst case, the storage device cannot be used. The nature also occurs.

On the other hand, if a rewrite operation is performed to bypass the ECG circuit 2 according to the present invention, the error-corrected read data is used as the rewrite data.
Correct data is written to the memory array 4 in one rewrite operation, and it is not necessary to start the rewrite operation unless another correctable failure occurs, and it is possible to prevent a decrease in storage device performance. Further, the reliability can be improved.

In general, a rewrite operation to a storage element is started only when a correctable failure occurs during a read operation in order to prevent the performance of the storage device from deteriorating.

[0032]

As described above, according to the present invention, as a countermeasure against a soft error of a storage element, an error correction /
In a storage device including a detection circuit and having a function of correcting read-out data and rewriting data to the storage element when an error occurs in data read from the storage element, an inspection added to the read data is performed. By newly providing an error correction circuit for bits, it is possible to bypass a circuit (ECG circuit) for generating a check bit for write data required at the time of rewriting, thereby shortening the rewriting time. it can.

Even when a failure occurs in the check bit generation circuit added to the write data, the ECG circuit is first provided by an upper device by providing an error correction circuit for the check bit added to the read data. It only passes when it is written to the storage element,
Even if an error correctable error is written to the storage element at this point, the correctable error is removed by the rewriting operation, and the corrected correct data is rewritten to the storage element. Since the degradation can be minimized and the ECG circuit in which a correctable failure has occurred can be bypassed, the reliability of the storage device can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a memory rewrite operation error detection device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the memory rewrite operation error detection device of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional memory rewrite operation error detection device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Storage device 2 ECG circuit 3 Selector 4 Memory array 5 Error detection circuit 6 Error correction circuit for data 7 Error correction circuit for check bits 11 Main operation part 12 Memory 13 Error detection / correction (ECC) circuit 14 Timing circuit 15 Data register Reference Signs List 16 external input / output buffer 17 address register 18 3-state buffer 19 write data selection circuit 100 write data 101 write data storage register 102 write data storage register 200 read data 201 read data storage register 202 read data storage register

Claims (12)

[Claims] An error correction / detection circuit is provided as a measure against soft errors in a storage element. When an error occurs in data read from the storage element, the read data is corrected and rewriting to the storage element is performed. In a memory rewrite operation error detection device having a function of performing a check bit error correction means for performing error correction on a check bit added to read data, and a check bit output corrected by the check bit error correction means, A memory rewriting operation error detection device, comprising: rewriting means for rewriting the storage element. 2. The memory rewriting device according to claim 1, wherein said rewriting means rewrites said check bit output to said storage element without passing through said error correction / detection circuit. Operation error detection device. 3. A storage device having an error correction / detection circuit as a countermeasure against soft errors, wherein when an error occurs in data read from the storage element, the read data is corrected and rewriting to the storage element is performed. A memory rewrite operation error detection device having a function of performing a first write data storage register to which write data from a higher-level device is input, and an ECC function to receive output data of the first write data storage register as input. An error detection / correction check bit generation circuit for generating check bits required for realization; and an error detection / correction check bit generation circuit and output data of a second read data storage register. A selector for selecting one of them, and a second write data storage register for storing write data of the selector output A memory array that stores output data of the second write data storage register; and a first array that receives data from the memory array.
And the output data of the first read data storage register is input, and a plurality of bits of error are detected by a preset ECC function. And an error detection circuit that outputs error information of the error detection circuit, corrects read data or check bits based on the error information, and outputs the corrected read data and check bit output to a higher-level device. For the data to be output to the second read data storage register for outputting the read data of
A memory rewrite operation error detection device, comprising: a check bit error correction circuit; 4. The data / check bit error correction circuit outputs the data read from the storage element and the check bit output from the error detection circuit detecting an error according to a predetermined ECC function. 4. The memory rewrite operation error detecting device according to claim 3, wherein the error of the check bit is corrected based on the error information of the check bit to be performed, and the corrected error is transmitted as a check bit output. 5. The data and check bits read from the storage element according to a predetermined ECC function.
4. The memory rewriting operation according to claim 3, further comprising a check bit error correction circuit for correcting an error of the check bit based on error information of the check bit output from the error detection circuit for detecting an error. Error detection device. 6. A rewrite check bit output circuit for outputting a check bit output from the data / check bit error correction circuit so as to bypass the error detection / correction check bit generation circuit. The memory rewrite operation error detecting device according to claim 3, wherein the device is selected as: 7. As a measure against soft errors in a storage element, an error correction / detection circuit is provided, and when an error occurs in read data from the storage element, the read data is corrected and rewriting to the storage element is performed. A memory rewrite operation error detection device having a function of performing an error correction for a check bit added to read data, and rewriting the corrected check bit output to the storage element. Memory rewrite operation error detection method. 8. The memory rewrite operation error detecting method according to claim 7, wherein the check bit output is rewritten to the storage element without passing through the error correction / detection circuit. 9. As a measure against soft errors in the storage element, an error correction / detection circuit is provided, and when an error occurs in data read from the storage element, the read data is corrected and rewriting to the storage element is performed. Inputting write data from a higher-level device to a first write data storage register; receiving an output data of the first write data storage register as an input; Generating a check bit required to realize the above by an error detection / correction check bit generation circuit; and inputting the error detection / correction check bit generation circuit and output data of a second read data storage register. Selecting one of them by a selector; and writing data of the selector output. Is stored in a second write data storage register; the output data of the second write data storage register is stored in a memory array; Inputting the data to a storage register; inputting the output data of the first read data storage register as input; performing error detection of a plurality of bits by a preset ECC function; Outputting information from an error detection circuit; inputting error information of the error detection circuit, and correcting read data or check bits in a data / check bit error correction circuit based on the error information. Outputting the corrected read data and check bits; Receiving the output data of the bit error correction circuit as input, and outputting read data to a higher-level device via the second read data storage register. Method. 10. The data / check bit error correction circuit outputs the data read from the storage element and the check bit output from the error detection circuit that detects an error according to a predetermined ECC function. 10. The memory rewrite operation error detecting method according to claim 9, wherein an error of the check bit is corrected based on the error information of the check bit to be performed, and the corrected error is transmitted as a check bit output. 11. The method according to claim 1, wherein the data and the check bits read from the storage element are checked in accordance with a predetermined ECC function based on error information of the check bits output from an error detection circuit for detecting an error. The method according to claim 9, wherein an error of the check bit is corrected by an error correction circuit. 12. The selector according to claim 1, wherein said selector outputs a check bit output sent from said data / check bit error correction circuit.
11. The memory rewrite operation error detection method according to claim 9, wherein the rewrite check bit is selected so as to bypass the error detection / correction check bit generation circuit.