JPS63753A - Test system for memory error checking and correcting circuit - Google Patents

Test system for memory error checking and correcting circuit

Info

Publication number
JPS63753A
JPS63753A JP61144321A JP14432186A JPS63753A JP S63753 A JPS63753 A JP S63753A JP 61144321 A JP61144321 A JP 61144321A JP 14432186 A JP14432186 A JP 14432186A JP S63753 A JPS63753 A JP S63753A
Authority
JP
Japan
Prior art keywords
data
memory
check bit
test
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61144321A
Other languages
Japanese (ja)
Inventor
Akiko Masaki
Yozo Igi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61144321A priority Critical patent/JPS63753A/en
Publication of JPS63753A publication Critical patent/JPS63753A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To conduct a test for normality of a memory error checking/correcting ECC circuit by inhibiting the writing of a check bit received from the ECC circuit to write data to a memory when a register is set for test of the normality of the ECC circuit and writing data in a memory and then reading out said data and comparing the check bit corresponding to other data stored in the memory to compare them with each other.
CONSTITUTION: Write data is added to an ECC circuit 102 to produce a check bit of this data and then the write data and the check bit are written in a memory 101. Then a register 103 is set under a test mode and data different from that written previously is given to the circuit 102. Thus the data of the memory 101 is rewritten by said data and this rewritten data is read out of the memory 101. At the same time, the previous check bit is read out of the memory 101. Then these read out data and check bit are compared with each other. If abnormality is detected said comparison, the normality of the circuit 102 is decided.
COPYRIGHT: (C)1988,JPO&Japio
JP61144321A 1986-06-20 1986-06-20 Test system for memory error checking and correcting circuit Pending JPS63753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61144321A JPS63753A (en) 1986-06-20 1986-06-20 Test system for memory error checking and correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61144321A JPS63753A (en) 1986-06-20 1986-06-20 Test system for memory error checking and correcting circuit

Publications (1)

Publication Number Publication Date
JPS63753A true JPS63753A (en) 1988-01-05

Family

ID=15359375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61144321A Pending JPS63753A (en) 1986-06-20 1986-06-20 Test system for memory error checking and correcting circuit

Country Status (1)

Country Link
JP (1) JPS63753A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011227646A (en) * 2010-04-19 2011-11-10 Mitsubishi Electric Corp Computer diagnosis device and diagnosis method
CN106528359A (en) * 2016-11-29 2017-03-22 北京时代民芯科技有限公司 Observability method for external memory check bits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011227646A (en) * 2010-04-19 2011-11-10 Mitsubishi Electric Corp Computer diagnosis device and diagnosis method
CN106528359A (en) * 2016-11-29 2017-03-22 北京时代民芯科技有限公司 Observability method for external memory check bits
CN106528359B (en) * 2016-11-29 2019-07-23 北京时代民芯科技有限公司 A kind of observability method of external memory check bit

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