JPS63753A - Test system for memory error checking and correcting circuit - Google Patents

Abstract

PURPOSE:To conduct a test for normality of a memory error checking/correcting ECC circuit by inhibiting the writing of a check bit received from the ECC circuit to write data to a memory when a register is set for test of the normality of the ECC circuit and writing data in a memory and then reading out said data and comparing the check bit corresponding to other data stored in the memory to compare them with each other. CONSTITUTION:Write data is added to an ECC circuit 102 to produce a check bit of this data and then the write data and the check bit are written in a memory 101. Then a register 103 is set under a test mode and data different from that written previously is given to the circuit 102. Thus the data of the memory 101 is rewritten by said data and this rewritten data is read out of the memory 101. At the same time, the previous check bit is read out of the memory 101. Then these read out data and check bit are compared with each other. If abnormality is detected said comparison, the normality of the circuit 102 is decided.

Description

[Detailed Description of the Invention] [Summary] Memory error correction and
In a system having a detection circuit (hereinafter abbreviated as ECC circuit), a register is provided that is set when testing the normality of the ECC circuit, and when this register is set, the ECC
Write data to the memory by prohibiting writing of check bits from the circuit, read this data and check bits for different data recorded in the memory, and determine the normality of the ECC circuit based on the relative softness result. .

[Industrial application field]

The present invention relates to a test method for memory error correction/detection circuits (hereinafter abbreviated as ECC circuits); in particular, the present invention relates to a test method for ECC circuits that allows testing of ECC circuits without requiring an external tester, etc. It is related to.

Many systems have an ECC circuit in the main memory and check the normality of data written to and read from the main memory, but in this case it is of course necessary that the ECC circuit itself is normal. Therefore, it is necessary to test the normality of the ECC circuit. As a test method for ECC circuits, it is desired that there is no need to use a special test machine or the like during testing, and that the test method can be operated online.

The present invention aims to provide an ECC circuit testing method that meets these demands.

[Conventional technology]

FIG. 3 shows an example of the configuration of a conventional ECC circuit testing method. In the figure, 1 is a communication control unit (CC) of the exchange, 2 is a data buffer, 3 is an ECC circuit, and 4 is a communication control unit (CC) of the exchange.
1, 42, 43, and 44 are tristate circuits. 5
is a main memory, 5I is a data area of the main memory 5, and 52 is a check bit area. Further, 6 is another data buffer, 7 is a tester, and 8 is a memory control circuit.

When writing to memory in the normal mode of the ECC circuit 3, 16-bit data from the communication control device 1 is applied to the ECC circuit 3 via the data buffer 2, and error detection and error correction are performed for a 1-bit error, for example. Then, a 6-bit check bit is generated that can detect a 2-bit error. The memory control circuit 8 outputs a write signal in response to a signal given via a control line, and the main memory device 5 enters a write state by being given the write signal, and stores 16-bit data, for example, "5" in hexadecimal notation.
555" is written to the data area 5 of the specified address in the main memory 5 through the tri-state circuit 4), and the 6-bit check bit in the ECC circuit 3, for example "27" in hexadecimal notation, is in the on state. The data is written to the check bit area 52 of the main memory device 5 via the tri-state circuit 43.

On the other hand, at the time of memory reading, the main memory device 5 is placed in a reading state by a read signal from the memory control circuit 8, and data, for example "5555", read from the data area 51 is applied to the ECC circuit 3 via the tri-state circuit 42. Also, the check bit “27” read from the check bit area is passed through the tri-state circuit 44 to the E
The data is added to the CC circuit 3, and the ECC circuit 3 compares both data. If the comparison result is abnormal, there is an error in the read data, and an error signal ERR indicating this is sent to the communication control device 1.

When testing the normality of the ECC circuit 3, a signal ECCTH that puts the ECC circuit 3 in through mode is applied from the tester 7 connected to the communication control device 1, and at the same time, data such as "5554" is sent to the data buffer 2. Give after a while. E
The CC circuit 3 receives data “55” without performing a check operation.
54" is written into the data area 5. However, at this time, the tristate circuit 43 is turned off by the signal ECCTH, so no output is generated for the check bit area 52. At the same time, the tristate circuit 43 is turned on by the signal ECCTH. The check bit "27" is written into the check bit area 52 via the data buffer 6 that is being checked.

Next, turn off the signal ECCTH to cancel the through mode, read data “5554” from the data area 5I,
When the check bit "27" is read out from the check bit area 52 and compared, a 1-bit error is determined, so an error signal ERR is output, and the communication control device 1 can confirm the normality of the ECC circuit 3 by this. can.

Furthermore, even if the data and check bits have a 2-bit error, the ECC circuit 3
It is possible to check the normality of the

[Problem that the invention seeks to solve]

As described above, the conventional ECC circuit test circuit requires a special test machine to test the normality of the ECC circuit.

Furthermore, since it is necessary to input test data from such a testing machine, there is a problem in that the normality test of the ECC circuit cannot be conducted online.

[Means for solving problems]

In order to solve the problems of the prior art, the present invention has the following points:
It has the basic configuration shown in FIG.

Reference numeral 101 denotes a memory constituting a main storage device.

102 is a memory error correction/detection circuit which generates a check bit from memory write data and writes it into the memory 101 together with the write data;
It has a function of comparing the data read from memory 101 with the check bit read from memory 101, and detecting and correcting errors in the read data based on the comparison results.

A register 103 is set in the test mode, and its output inhibits writing of check bits in the memory 101.

[For production]

In the configuration shown in FIG. 1, when testing the normality of the memory error correction/detection circuit 102, first, write data is added to the memory error correction/detection circuit 102, a check bit for this data is generated, and the write data is Write data and check bits to memory 101.

Next, the register 103 is put into test mode, and data different from the previously written data is added to the memory error correction/detection circuit 102, thereby rewriting the data in the memory 101 with this data.

At this time, the check data in the memory 101 is not rewritten.

Next, the rewritten data in the memory 101 is read out, and the previous check bit stored in the memory 101 is read out and compared.

If it is a comparison testicular abnormality, memory error correction/detection circuit 1
The normality of 02 is determined.

[Example] Figure 2 shows an example of the present invention.
The same parts as in the figures are indicated by the same numbers, and their operations are also similar. 9 is a register (F/F), which is set by software, for example. 10 is a gate circuit.

In the normal mode, the register 9 is reset and the gate circuit 10 is open, so the memory control circuit 8 outputs a write or read signal according to the signal on the control line. , reading is performed.

Further, data writing and reading in the normal mode by the ECC circuit 3 and checking of the normality of the data by the ECC circuit 3 at that time are performed in the same manner as in the conventional circuit shown in FIG.

When checking the normality of the ECC circuit 3, the ECC circuit 3 is first set to normal mode, the register 9 is reset, the memory control circuit 8 is set to the write state, and the communication control device 1 is turned on.
16-bit data, for example "5555", is supplied to the ECC circuit 3 via the data buffer 2. As a result, data "5555" is written from the ECC circuit 3 into the data area 51 of the main memory 5, and a check bit, for example "27°," is written into the check bit area 52.

Next, the test mode is set, and the register 9 is set by part of the 16-bit data given from the communication control device 1. At this time, data from the communication control device 1, for example, 55
54'' is written through the data buffer 2, it is written through the ECC circuit 3 and the data area 51 is written.
data is rewritten to "5554". However, since the write signal is prohibited by the gate circuit 10, the check bit area 52 cannot be rewritten.

Next, the memory control circuit 8 is put into a read state, and the data area 5. At the same time as the data "5554" is read out, the check bit '27' is read out from the check bit area 52 and compared.
54'' is different by 1 bit, so a 1-bit error is determined. The ECC circuit 3 outputs an error signal ERR, and the communication control device 1 can determine whether the ECC circuit 3 is normal based on this.

In this case, register 9 is controlled by using a part of the address space of the processor so that register 9 is operated via the output of decoder 11 when that address is specified. , controlled by software.

In the conventional circuit shown in FIG. 3, in the through mode, even if 16-bit data is written from the communication control device 1, the EC
Since no check bit is output from the C circuit 3, it is necessary to write 6-bit data from the tester 7 to the check bit area. Therefore, it was impossible to check the normality of the ECC circuit in an online state, but with the circuit of the present invention, there is no need to separately create a check bit for testing the ECC circuit, so there is no need for a tester, and therefore, there is no need for a tester. It becomes possible to check the normality of the ECC circuit.

〔Effect of the invention〕

As explained above, according to the present invention, a separate testing machine is not required when testing the normality of an ECC circuit, and
There is an advantage to being able to take the exam online.

[Brief explanation of the drawing]

FIG. 3 is a diagram showing a conventional ECC circuit test circuit. 1--Communication control device (CC) of the exchange 2-Data buffer 3-E CC circuit 5-Main storage device 5F--The above 1. Data area 52 of device a 5 Check bit area 8 of main memory 5 Memory control circuit 9 Register (F/F) 10 Gate circuit 11 Decoder

Claims (1)

[Claims] A check bit is generated from memory write data and written into the memory (101) together with the data, and the read data is compared with the check bit to correct errors in the read data. In the memory error correction/detection circuit (102) that performs the detection, a register (103) is provided which is set in the test mode and whose output inhibits writing of check bits in the memory (101), and the register (103) is configured to prohibit writing of check bits in the memory (101). check bits for the memory (101
), the register (103) is set to test mode, the write data in the memory (101) is rewritten with data different from this, and then the rewritten data in the memory (101) and A memory error characterized in that the normality of the memory error correction/detection circuit (102) is tested by reading out and comparing the unrewritten check bits stored in the memory (101). Test method for correction/detection circuits.