JPH01205357A - System for testing memory error detecting circuit - Google Patents

Abstract

PURPOSE:To test a memory error circuit by reading data corresponding respectively to the data part and the check bit part of a memory unit, and detecting the presence of the error of both read data. CONSTITUTION:When the optional data is written by the address of a testing area and testing data desired to write in the check bit part 12 is outputted to a write data line, it is selected by a data selecting part 7, and inputted to the bit part 12. In this state, a memory control part 10 controls a control line C so as to make the memory unit 1 perform a write operation, and writes the optional data in the data part 11 and the bit part 12. Then, by reading the data from the unit 1, the error informing function of a data checking part 3 and the data correcting function of a data correcting part 4 can be checked for all data patterns.

Description

[Detailed Description of the Invention] [(Already Required)] The present invention relates to a memory error detection circuit test method for testing an error detection circuit that detects errors in data stored in a memory unit. The purpose of the present invention is to provide a method for testing a circuit that detects memory errors by making it possible to write memory errors. a memory unit comprising means for inhibiting writing of data input to the data section by a write inhibit signal;
a data selection section that selects a part of the data input to the data section of the memory unit and check data of the input data generated by the check bit generation section and outputs the selected data to the check bit section; and a data section of the memory unit. and the corresponding data in the check bit section,
and a data check unit that detects whether or not there is an error in both read data.

[Industrial application field]

The present invention relates to a memory error detection circuit test method for testing an error detection circuit that detects errors in data stored in a memory unit.

The data stored in the memory unit is the program of the data processing device, input/output data, intermediate data of processing, etc., and the occurrence of an error in the memory unit is
The reliability of processed data in a data processing device is lost.

Therefore, ECC (Error Check and '
Correct) + Or a parity check is performed to detect errors.

If these check circuits do not function satisfactorily, the reliability of the data stored in the memory unit cannot be guaranteed, so the check circuits are required to always ensure reliable functionality.

[Conventional technology]

FIG. 3 is a diagram illustrating a conventional method of testing a memory error detection circuit.

Below, we will first explain the process by which errors in memory data are repaired (ignoring the check data register 5 and data selection section 6 in FIG. 3, the output of the check bit section 12 of the memory unit 1 ).

As shown in FIG. 3, the memory unit 1 includes a data section 11.
and a check bit section 12. When write data of, for example, 16 bits is input, it is written to the data section 11 and is also sent to the check bit generating section 2, for example, ECC.
In the case of a circuit, 6-bit redundant data for 16-bit input data is generated as check data.

Then, it is stored in the check bit section 12 of the memory unit 1.

When data stored in a memory unit is read out,
When the data is checked by the data check section 3 and an error is detected, the data check section 3 generates an error signal and notifies an error processing section (not shown), and sends error correction information to the data correction section 4.

Even if a 1-bit error occurs in the data sold by S, the data correction section 4 repairs the data based on the error correction information sent from the data check section 3.

Next, a method of testing this error detection circuit will be explained.

As shown in FIG. 3, the check data register 5 and the data selection section 6 are connected.

Then, when testing the data check section 3, the data selection section 6 selects arbitrary data stored in the check data register 5, and selects the data read from the data section 11 of the memory unit 1 and the check data register 6. The read check data is sent to the data check section 3.

The data check section 3 is a data section 1 of the memory unit l.
The compatibility between the data input from 1 and the data input from the data selection section 6 is checked, and the detection function of the detection circuit is confirmed.

[Problem to be solved by the invention]

In this conventional method, a check data register and a data selection section are added, which increases the complexity of the circuit, and the timing of reading data from the memory unit and the timing of reading data from the check data register are usually within limits. Therefore, it is difficult to match this timing.

Moreover, controlling the added check data register and data selection section is cumbersome.

The present invention was created in view of the above points, and an object of the present invention is to provide a method for testing a circuit that detects memory errors by allowing arbitrary test data to be written in a memory unit. It is said that

[Means to solve the problem]

In order to achieve the above object, a memory unit includes a data section for storing memory data and a check bit section, and has a means for prohibiting manual data writing to the data section, and a part of data to be input; It consists of a data selection section that selects and outputs the check data generated by the check bit generation section, and a memory control section that controls a memory unit, and checks the compatibility of data in the data section read from the memory unit and the check data section. Compare and check in the data check section.

[For production]

One piece of data in a memory unit can be accessed from two address areas: an address area for normal program processing (program area) and an address area for test data (test area).

When writing data using a program area address, a program area selection signal is sent by the program area/test area decoding circuit, and the data to be written is written to the data area in the memory unit.
Check data corresponding to the data written in the data section is written into the check bit section.

When writing data in the test area used for testing the error detection circuit, the program area/test area decoding circuit sends out a test area selection signal, and the data area is not written to due to the write prohibition signal, and data is not written in the program area. Although the written data remains unchanged, it is possible to write any data to the check bit section corresponding to that data.

Through such operations, arbitrary data can be written to all pits in the data section and check bit section within the memory unit. When test data is read out from this memory unit in a test, the control program of the memory control section makes it possible to check in detail and easily the operation of the data check section through which the read data passes.

〔Example〕

FIG. 1 is a block diagram showing the configuration of an embodiment of the memory error detection circuit test method of the present invention, and FIG. 2 is a diagram illustrating writing/reading of a memory unit.

Note that the same reference numerals indicate the same objects throughout the figures.

The memory unit 1 can access the same data using addresses in the program area and test area.

When an address to be accessed from the double-headed area is input to the memory unit 1, the program area/test area decoding circuit distinguishes whether the address is a program area or a test area and outputs a program area selection signal P or a test area selection signal T. Memory control section 10 via OR circuit 8
Send to.

For addresses from the test area, this test area selection signal T becomes a write inhibit signal for the memory unit 1.

When writing arbitrary data at the address of the program area, the data (DBOO to D
B15) Output 16 bits to the write data line [see FIG. 2 (al)].

The data is directly entered into the data section 11 of the memory unit l.

On the other hand, for the same data, the check pit generator 2 generates 6 bits of check data (CBO to CB5), the data selector 7 selects this check data, and inputs it to the check bit section 12 of the memory unit 1.

That is, in this state, the memory control section 10 controls the control line C to perform a write operation in the memory unit 1, and the write inhibit signal line is set to "0", and the data section 11
will be written to.

Next, when writing arbitrary data at the address of the test area, output the test data (DBOO to DBO5) that you want to write to the check bit section 12 to the write data line, it will be selected by the data selection section 7, and the check bit section 12 [see Figure 2 (C1)].

In this state, the memory control section 10 controls the control line C to cause the memory unit 1 to perform a write operation.

However, the write inhibit signal line is set to "1" and nothing is written to the data section 11, the original data remains and is written only to the check bit section 12.

As described above, arbitrary data can be written to both the data section 11 and the check bit section 12 of the memory unit 1.

- Then, by selling the data from the memory unit 1, the error notification function of the data checking section 3 and the data correction function of the data correction section 4 can check all data patterns. Figure (b
)].

The data check section 3 includes an FCC and a parity check, but in the case of a parity check without a data correction function, the data correction section 4 is not connected.

Also, the OR circuit 8 allows the memory control unit 10 to receive either the program area selection signal or the test area selection signal.
is driven.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a sufficient test effect of the error detection circuit with a small amount of additional circuitry by using the control program executed by the memory control unit, and furthermore, the number of test steps can be reduced, and the hardware It has a remarkable effect on improving reliability, and is extremely useful industrially.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the memory error detection circuit test method of the present invention, FIG. 2 is a diagram explaining writing/reading of a memory unit, and FIG. 3 is a diagram of a conventional memory error extraction circuit. It is a figure explaining a test method. In the figure, 2 is a memory unit, 2 is a check bit generation section, 3 is a data check section, 7 is a data selection section, 10 is a memory control section, 1 is a data section, and 12 is a check bit section. (a) Sweating with kudzu (b) Scratching customers and WiZ diagram

Claims (1)

[Claims] A data section (11) that stores memory data, and a check bit section (11) that stores check data corresponding to the data.
12), the memory unit (1) has means for inhibiting writing of data input to the data section (11) by a write inhibit signal, and the memory unit (1)
), a data selection section ( 7) and the memory unit (
A data check unit (3) reads the corresponding data of the data section (11) and check bit section (12) of 1) and detects whether or not there is an error in both of the read data.
A memory error detection circuit test method comprising: