JPH0752398B2 - Check circuit diagnostic device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device in an information processing device, and more particularly to a circuit diagnostic device for checking an error.

[Prior Art] In a storage device of an information processing device, when a failure occurs in a storage element (hereinafter referred to as a memory) or a data transfer path, a parity check or ECC is performed to detect or correct a data error due to the failure. (Error Correcting Code) is generally used. In these methods, the inspection information generated from the write data is written in the memory together with the data at the time of writing the data, and the error detection or the error detection / correction is performed at the time of the reading to improve the reliability of the storage device.

FIG. 3 shows an example of the configuration of a memory device having an error detection circuit based on the parity check method. In the figure, 5 is a parity generator, 6 is a parity bit,
Reference numeral 8 is a memory, 9 is a parity checker, 10 is write data, 11 is read data, and 12 is an error detection signal.

At the time of writing, the parity bit 6 generated by the parity generator based on the write data 10 is written in the memory 8 together with the write data 10 as inspection information. At the time of reading, the parity checker 9 checks for a 1-bit error. The parity is "1" included in the data.
The number of "1" included in the data and the parity bit 6 is reflected so that the parity bit 6
The case of generating and checking is called an odd parity method.
The same applies to the even parity method.

In the storage device using the parity check method as shown in FIG. 3, an error in the memory 8 occurs only rarely due to an alpha ray failure. Therefore, in order to diagnose the check circuit itself, it is necessary to have means for inputting erroneous data or inspection information to the check circuit to generate a pseudo error. More reliable than parity method
Similarly in the ECC system, in order to diagnose the error detection and correction circuit, it is necessary to input erroneous data or inspection information to the error detection and correction circuit.

As a method of diagnosing the error detecting circuit or the error detecting / correcting circuit in the conventional apparatus, as described in JP-A-57-146349, erroneous data 10 or inspection information is stored in the memory 8.
There is a method of providing a diagnostic write command to be written in the CPU (central processing unit). FIG. 4 shows a configuration for executing this method. In the figure, 4 is an inspection information change command signal,
7 is an inspection information changing circuit, 13 is a CPU (central processing unit), 17
Is an inspection information generation circuit, 18 is a check circuit, and 19 is an inspection information signal. When the CPU 13 executes the diagnostic write command, the inspection information change command signal 4 is output, and the inspection information generated by the inspection information generation circuit 17 is changed from the write data 10 to the incorrect inspection information by the inspection information change circuit 7. It is written in the memory 8. When the address written by the above-described diagnostic write command is read, erroneous inspection information is read from the memory 8 and erroneous inspection information is input to the check circuit 18, so that the operation of the check circuit 18 is diagnosed. can do. In the case of the parity method, the check information generation circuit 17 corresponds to the parity generator 5 and the check circuit 18 corresponds to the parity checker 9.

Further, in JP-A-61-23242, by providing a means for giving an address different from the address given to the memory 8 for storing data to the memory for storing the inspection information,
A method for inspecting the check circuit 18 is described.
FIG. 5 shows a configuration for executing this method, and FIG. 6 shows an explanatory diagram for explaining the operation. In FIG. 5, the data memory 16 for storing data is connected to address lines A0 to A9 output by the CPU 13, and the inspection information memory 15 for storing inspection information is connected to the address lines A0 to A9 for output of the CPU 13. A8 and the OR gate 14 connect signals obtained by ORing A9 and A10.

FIG. 6 shows a memory map in the circuit of FIG. In the above circuit, the address areas shown by A and B in FIG. 6 are assigned as ordinary memory addresses. In the figure, the memories in the address areas indicated by A and B can also read and write from the image areas indicated by A'and B ', respectively. That is, FIG. 7A is an example of the memory map of the data memory 16.
It shows that the same memory address is assigned as an image every 400H (H indicates a hexadecimal number). FIG. 6B shows an example of a memory map of the inspection information memory 15. However, since the address given to the inspection information memory 15 is different from the address given to the data memory 16 as shown in FIG. It is shown that the memory address assigned as an image to the 5FFH address is different from the memory map of the data memory 16. Therefore, if data and inspection information different from the previous data are written in address 400H after writing data and its inspection information in address 0, the data in memory address 0 is updated. ,
The inspection information of the address is not updated. Therefore, if reading from the address is performed after such writing,
Incorrect inspection information can be input to the check circuit, and the check circuit can be diagnosed.

[Problems to be Solved by the Invention] In the conventional example shown in FIG. 4, since erroneous test information can be easily written to an arbitrary address by a diagnostic write instruction, a diagnostic write instruction and a read instruction can be written. It is excellent in that the check circuit 7 can be diagnosed only by executing the two instructions. However, it is necessary to provide special instructions to the CPU13, and a general-purpose microprocessor
It cannot be implemented by the information processing device used as 3.

Further, the conventional example shown in FIG. 5 is excellent in that erroneous inspection information can be written in the memory 8 with simple hardware, but the data memory 16 and the inspection information memory 15 are composed of individual elements. There is a problem that data and inspection information cannot be stored in the same memory device in order to reduce the number of memory devices.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a check circuit diagnosing device which solves the above-mentioned problems of the prior art and can easily perform error detection and error detection / correction circuit diagnosis of a memory device.

[Means for Solving Problems] In order to achieve the above object, the first invention of the present application adds inspection information to data and writes the same in a memory, and an error of data read from the memory is corrected by the inspection information. A check circuit diagnostic device for checking based on the above, wherein a memory to which a first address area is assigned and an address signal of the first address area are received to generate a selection signal for the memory. Address decoder for receiving the address signal of the second address area other than the address area for generating the memory selection signal and the change command signal, and the write data for the memory. Inspection information generating means for outputting inspection information to the second address area, and a change instruction signal from the address decoder based on the write instruction to the second address area, Write data or changing means for changing the write data to the check information obtained by the check information generating means; and data read from the memory based on a read command of the first address area. And a check circuit for detecting an error in the data based on the inspection information corresponding to the data.

A second invention of the present application is a diagnostic device for a check circuit, which adds inspection information to data, writes it in a memory, and checks an error of data read from the memory based on the inspection information. Receiving the address signal of the first address area and the memory to which the address area of the first address area is assigned, generating the selection signal of the memory, and receiving the address signal of the second address area other than the first address area. An address decoder for generating a selection signal for the memory and a change command signal, and a test information generating means for outputting test information for data written in the memory based on a write command for the first address area. And a change command signal from the address decoder based on the read command of the second address area, and the data read from the memory. Data or the inspection information corresponding to the data, and the data read based on the data read from the memory and one of which has been changed by the changing means and the inspection information corresponding to the data. And a check circuit for detecting the error.

[Operation] The storage device is substantially allocated with a normal address area which is a normal storage target and a diagnostic address area in which the inspection information is changed to incorrect information for writing. The address decoding circuit decodes a write address when data is written to the storage device and determines whether the address is a diagnostic address area for determining whether it is a normal address area or a diagnostic address area. The inspection information change command signal 4 is output from the address decoding circuit, and the inspection information change circuit 7 changes the inspection information according to the command signal.
Wrong inspection information is written in the memory 8 together with the data.

If the data written by the above-described method is read in the normal address area, erroneous inspection information is read from the memory 8, so that the check circuit 9 can be diagnosed.

The data may be written in the storage device as usual, and the inspection information may be changed using the diagnostic address at the time of reading. Further, the data may be changed instead of the inspection information.

[Embodiment] <First Embodiment> A first embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 2 shows an address area assigned to the storage device. FIG. 1 is a block diagram of a memory device for carrying out the present invention, in which 2 is an address decoding circuit and 3 is a memory selection signal. The other blocks having the same functions as those shown in FIGS. 3 and 4 are designated by the same reference numerals.

As shown in FIG. 2, an address area of 0000H to 07FFH is assigned to the storage device, of which 0000H to 03FFFH is a normal address area and 04000H to 07FFFH is a check circuit diagnostic area.

In FIG. 1, the parity generator 5 is the write data.
The parity bit 6 is generated from 10 as the check information. When the writing is performed in the diagnostic area, the address decoder 2 to which at least the above-mentioned 3 bits A14, A13, A12 of all 14 bits of A0 to A14 of the address signal 1 are input
The inspection information change command signal 4 is output from the device, and the above-mentioned parity bit 6 is inverted by the inspection information change circuit 7 to indicate an incorrect value. Inverted parity bit 6
Are written in the memory 8 together with the write data 10. Since the signal given to the memory 8 among the address signals 1 input to the memory 8 is 14 bits of A0 to A13, when writing to the diagnostic area, the memory address obtained by subtracting 4000H, that is, Normally written in the address area.

In order to check the parity checker 9 in the storage device described above, it is only necessary to write to an arbitrary address in the diagnostic area and then read the address obtained by subtracting 4000H from the address. If the error detection signal 12 is output during reading, the parity generator 5,
The inspection information changing circuit 7 and the parity checker 9 can be determined to be normal.

<Second Embodiment> FIG. 7 shows another embodiment of the present invention. In this embodiment,
When the correct parity bit is always written in the memory and read from the diagnostic area, the read parity bit is inverted by the inspection information changing circuit 7 and input to the parity checker 9. Therefore, the inspection information changing circuit 7 is moved from the front stage to the rear stage of the memory 8. In the configuration of the present embodiment, the parity generator 5, the inspection information changing circuit 7, and the parity information generator 5 are used in the same manner as the method described in the first embodiment except that the address of the diagnostic area is used when reading the memory 8 instead of when writing. The parity checker 9 can be diagnosed.

<Modification> In the above embodiments, the storage device that performs the error detection by the parity method has been described as an example, but the same can be applied to the storage device that detects and corrects the error by the ECC method. The data may be changed instead of the inspection information.

Although the present invention requires an address area as a diagnostic area, it does not pose a problem in recent microprocessors and the like because the address space is very wide, from several M to several GB.

According to the present invention, the error detection or the error detection / correction circuit can be easily diagnosed without being limited to the configuration of the memory element used for the storage device and without providing the CPU with a special instruction. There is an effect. Also, since it is determined whether the access is for diagnosis only by the access address to the memory,
It is not necessary to newly provide a mode dedicated to diagnosis, and it is not necessary to secure an I / O register for setting whether or not the mode is the diagnosis mode and an address for the I / O register. Therefore, the storage device having the diagnostic function according to the present invention is
It is not necessary to change the use of I / O registers or to add signal lines for adding I / O register functions to the storage device, and can easily replace the conventional storage device. Further, even during normal operation, accessing an area deviating from the correct address area of the storage device can surely generate an error as accessing the diagnostic area, and improve the reliability of the information processing device. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a memory map in the embodiment shown in FIG. 1, and FIG.
FIG. 4 is a block diagram showing the configuration of a memory device having an error detection circuit, FIGS. 4 and 5 are block diagrams showing the configuration of a conventional device, and FIG. 6 is a memory map in the conventional example shown in FIG. FIG. 7 is a block diagram showing the configuration of another embodiment of the present invention. 1 ... Address signal 2 ... Address decoder 4 ... Inspection information change command signal 5 ... Parity generator 7 ... Inspection information change circuit 8 ... Memory 9 ... Parity checker 10 ... Write data 11 ... Read data 12 …… Error detection signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hajime Yamagami 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref., Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Inventor Atsushi Masuko Totsuka-ku, Yokohama-shi, Kanagawa 292 Yoshida-cho, Nippon Video Engineering Co., Ltd. (72) Inventor, Hitoshi Kobayashi, 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Japan (72) In-house, Naruo Kobayashi, 1 Horiyamashita, Hadano, Kanagawa Hiritsu Manufacturing Co., Ltd. Kanagawa Plant (72) Inventor Kazuhiko Komori 1 Horiyamashita, Hadano City, Kanagawa Prefecture Hiritsu Manufacturing Co., Ltd. Kanagawa Plant (56) Reference JP-A-62-84342 (JP, A) JP-A-SHO 62-210547 (JP, A) JP-B-55-28159 (JP, B2)

Claims (2)

[Claims] 1. A diagnostic device of a check circuit for adding inspection information to data, writing the same in a memory, and checking an error of data read from the memory based on the inspection information, wherein the first address area is The selection signal for the memory is generated in response to the assigned memory and the address signal in the first address area, and the address signal in the second address area other than the first address area is received to generate the first signal. An address decoder for generating a selection signal for the memory and a change command signal for selecting the same storage area as the storage area on the memory selected by the selection signal generated in the address area of Inspection information generating means for receiving the write data and outputting inspection information for the write data, and based on the write command to the second address area, Changing means for receiving a change command signal from the address decoder and changing the write data or the check information obtained by the check information generating means for the write data; and a read instruction for the first address area. And a check circuit for detecting an error in the data based on the data read from the memory and the inspection information corresponding to the data. 2. A diagnostic device of a check circuit for adding inspection information to data, writing the same in a memory, and checking an error of the data read from the memory based on the inspection information, wherein the first address area is The selection signal for the memory is generated in response to the assigned memory and the address signal in the first address area, and the address signal in the second address area other than the first address area is received to generate the first signal. An address decoder for generating a selection signal for the memory and a change command signal for selecting the same storage area as the storage area on the memory selected by the selection signal generated in the address area, Inspection information generating means for outputting inspection information for write data to the memory based on a write command to the address area, and the second address area The change command signal from the address decoder on the basis of the read command to change the data read from the memory or the inspection information corresponding to the data, and the change means read from the memory. A check circuit diagnosing device comprising: a check circuit that detects an error in the data based on the data and the inspection information corresponding to the data, one of which has been changed by the means.