JPS60258662A - Register file - Google Patents

Abstract

PURPOSE:To detect a bit error of a storage means in a normal use state by comparing a readout address or its complement with the select signal of a storage means, or the select signal of the storage means or its complement with the readout address. CONSTITUTION:Readout data (f) is read out of the data dedicated bits of a memory part 1 according to a readout address decoded signal (e) outputted from a readout address decoding latch part 3 corresponding to the readout address (d). At the same time, an address signal (i) is read out of the address dedicated bits. The parity of the readout data (f) is checked by a readout data parity check part 9. A comparing check part 7 compares the readout address (d) with the address signal (i) when the number of ''1''s of the readout data (d) is even or compares the complement (d) of the readout address with the analog signal (i) when odd, and a trouble detection signal (k) is generated when they do not coincide with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a register file used in an information processing device. In particular, the present invention relates to a register file that separates a write address from a subsequent address and can detect a failure in a memory unit during use.

[Conventional technology]

A conventional register file consists of a continuous address decode latch section that outputs a write address decode signal according to a write address, a successive address decode launch section that outputs a successive address decode signal according to a read address, and a successive address decode latch section that outputs a successive address decode signal according to a read address. and a memory section for writing and storing the data at the address indicated by the write address decode signal and outputting successive data read from the address indicated by the successive address decode signal.

Conventional register files like this are used when a problem occurs in the write address system or successive address system.
Write data may be written to an address different from the original write address, or subsequent data may be read from an address different from the original read address. Further, this conventional register file, in which write data is written or read incorrectly when a problem occurs in the memory section, will be described with reference to the drawings.

FIG. 2 is a block diagram of a conventional register file. The register file shown in FIG. 2 includes a memory section 1, a write address decode latch section 2, and a successive address decode latch section 3, and write data a is stored in a write address decode latch according to a write address b. Data f is written into the memory unit 1 according to the write address decode signal C output from the unit 2, and read data f from the memory unit 1 according to the successive address decode signal e output from the read address decode latch unit 3 in accordance with the successive address d. It is read as .

In this case, write data a is written to the write address output - (a malfunction occurs in the latch unit 2 or the read address decode launch unit 3, and the address is different from the write address b), or the write data a is written to the subsequent address d. The successive data f is read from an address different from that of
Read data f may be different from write data a. In order to detect these defects, after writing the write data a into the memory section 1 using the write address b, read the read data f using the same subsequent address d as the write address b, and read this read data f. Although it is necessary to compare f and write data a, there is a drawback that this cannot be detected under normal usage conditions.

FIG. 3 is a block diagram of another conventional register file, which is used as a register file for detecting the above-mentioned address system problems during normal use [Patent Application No. 1982-10].
It has been previously filed as No. 0406J.

This register file includes a memory section 1, a write address decode latch section 2, a read address decode launch section 3, and a comparison check section 7'. A malfunction in the write address decode launch section 2 and the subsequent address decode launch section 3 is detected. However, there was a drawback that a malfunction in the memory section 1 could not be detected.

[Problem that the invention seeks to solve]

SUMMARY OF THE INVENTION An object of the present invention is to provide a register file that can detect bit errors in a register file memory section under normal use and that requires less hardware.

[Means for solving problems]

The first invention includes a write address decode latch means for outputting a write address decode signal corresponding to an input write address, and a successive address decode latch means for outputting a successive address decode signal corresponding to a successive address to be input. , a register file comprising storage means for storing input write data at an address indicated by the write address decode signal and outputting successive data from an address indicated by the successive address decode signal; a first complement generation means for inputting a write address and outputting its complement; a write data parity check means for inputting the input write data and performing a parity check; write address selection means for selecting either the write address or the complement of the L write address based on the output signal and outputting a selection signal; at an address indicated by the write address decode signal, and outputs the selection signal from the address indicated by the successive address decode signal, further inputting the successive address and outputting its complement. a second complement generating means for inputting the successive data and performing a parity check thereon; and a read data parity check means for inputting the successive data and performing a parity check thereon; and a fault detection signal terminal connected to the output of the comparison check means.

The second invention includes write address decode launch means for outputting a write address decode signal corresponding to an input write address, and successive address decode launch means for outputting a successive address decode signal corresponding to a successive address to be input. , a register file comprising storage means for storing input write data at an address designated by a first write address decode signal and outputting successive data from an address designated by the successive address decode signal; , a first complement generating means for inputting the write address and outputting its complement; a write data parity check means for inputting the input write data and checking its parity; write address selection means for selecting either the write address or the complement of the write address based on the output signal of the check means and outputting a selection signal; Write the signal above at 1. - ST: includes means for storing the selection signal at an address indicated by the 1-F signal and outputting the selection signal from the address indicated by the successive address decode signal, further manually inputting the selection signal from the storage means, A third complement generating means outputs the complement, a read data parity check means inputs the read data and performs a parity check, and an output control signal of the successive data parity check means;
1. Comparison check means for selecting either the selection signal from the storage means and its complement and comparing it with the successive data, and a failure detection signal terminal to which the output of the comparison check means is connected. It is characterized by being equipped.

[For production]

The first invention performs a parity check on the write data, and in response to the odd number of "1" in the write data, the write address or the complement of the write address is selected and stored in the storage means together with the write data. be done. At the time of reading, the parity of the read data is checked, and the read address or the complement of the successive address is selected in accordance with the odd number of "1" in the successive data, and compared with the selection signal stored in the storage means, the error is detected. Detect. If the write data and the read data differ by an odd number of 11'', the comparison result will be inconsistent and a fault will be detected, thereby making it possible to detect a bit error in the storage means under normal usage conditions.

The second invention is that in the first invention, either the successive at 1/s or its complement is selected depending on the odd number of "l" in the read data and compared with the selection signal from the storage means. By selecting either the selection signal from the storage means or its complement and comparing it with the read address, a bit error in the storage means is detected under normal usage conditions.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a register file according to an embodiment of the present invention. In FIG. 1, write data a is connected to the memory section 1 from outside the figure. A write address b is connected to the write address decode launch section 2 from outside the figure, and a write address decode signal G is sent from the write address decode latch section 2.
is connected to the memory section 1, and write data a is stored in the data-dedicated bit of the memory section l. A read address d from outside the figure is connected to the successive address decode launch section 3, and a read address decode signal C from the successive address decode latch section 3 is connected to the memory section 1. Read data f is output from the memory section outside the figure.

Here, the feature of the present invention is an odd bit error detection section surrounded by a dashed dotted line. Of course, the write address b is branched and connected to the comparator L check section 7 and the complement generation section 5. The complement of the write address from the complement generator 5 is connected to the write address selector 4. Write data a is branched and connected to write data parity check section 6,
The output signal g of the write data parity check section 6 is connected to the control input of the write address selection section 4. An output signal from the write address selection section 4 is connected to the memory section 1, and the write address b or the complement of the write address is written to the address dedicated bit. Furthermore, the successive address d is connected to the comparison check section 7 and the complement light 1 section 8, and the complement d of the successive address is connected from the complement generation section 8 to the comparison check section 7. Further, an address signal i from the memory section 1 is connected to the comparison check section 7. The successive data f is branched and connected to the successive data parity check section 9, and the output signal j of the successive data parity check section 9 is connected to the control input of the comparison check section 7. A fault detection signal k from the comparison check section 7 is connected to a fault detection signal terminal 1o.

The operation of the register file having such a configuration will be explained. In FIG. 1, when write data a is written to the memory section 1, the write data a is data according to the write address decode signal C output from the write address decode launch section 2 in accordance with the write address b. Written to dedicated bits. At the same time, the write data parity check section 7 checks the parity of the write data a, and if the write data a has an even number of "1"s, the write address selection section 4 selects the write address b. When write data a has an odd number of "1"s, the complement of write address b is selected and written to the address dedicated bit.

Next, when the read data f is read out from the data-only bits of the memory section 1 in accordance with the successive address decode signal e output from the read address decode latch section 3 in response to the read-out signal d, the read data f is simultaneously read out from the address-only bits. Address signal i is read. At this time, the parity of the successive data f is checked by the read data parity check unit 8, and if the successive data f has an even number of "1"s,
The comparison check unit 7 compares the successive address d and the address signal i, and when the successive data f is an odd number, the comparison check unit 7 compares the complement d of the successive address and the analysis signal j, and it is determined that they match. If not, a failure detection signal k is generated.

Next, the operation when a fault is detected in the memory section 1 according to the embodiment shown in FIG. 1 will be described.

Assume now that the register file shown in FIG. 1 has an 8-bit, 4-word configuration. Write data a is rio i.

In 1010J, the data with an even number of 1's was changed from write address b to address 2 (r
i OJ) but is written to address 3 ("1゜1"), at the same time rl, as write address b,
OJ is also written, and when reading the data at address 3, rLO
J is read out as address signal 1 and compared with "1°1" as the subsequent address d, and since they do not match, a fault detection signal k is output and the fault is found.

Also, the above write data a is correctly written to address 2 (“1°0”).
is written to 0 due to a defect in the read decode latch section 3.
When address (ro, OJ) is read, address 2 (rl,
r as the address signal i when OJ) is read out.
l, OJ are compared with rO, OJ as the successive address d, and since they do not match, a fault detection signal k is output and a fault is found.

In addition, the write data ar1010]010J was written to address 2 (rl, OJ), and the successive data f read out at the successive address (II, OJ) due to a defect in the memory section 1.
is rlololooo, +(7), the successive address d (rl
, OJ) is compared with the complement of J (ro, IJ) and the subsequent address d (N, 0-1'), and since they do not match, a fault detection output 'k' is output and the fault is found.

As described above, in order to detect a failure in the address system, the write address b to be written to the memory unit 1 is set to "1" of the write data a.
Bit errors in the memory unit 1 can be detected by using the write address b as it is when ``1'' is an even number, and by using the complement of the write address when ``1'' is an odd number.

In the above explanation, write data a and read data f are "
The even number and odd number of "1" may be reversed. Further, the complement of the write address and the complement of the output address may be two's complement. FIG. 4 is a block diagram of a register file according to another embodiment of the present invention, and the address signal i or the complement i of the address signal may be compared with the subsequent address d.

〔Effect of the invention〕

As explained above, the present invention has the excellent effect of being able to detect bit/node errors in the memory section under normal usage conditions by adding some circuitry to the register file where address system failures are detected. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a register file according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional register file. FIG. 3 is a block diagram of another conventional register file. FIG. 4 is a block diagram of a register file according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Memory unit, 2-way write address decode latch unit, 3...Continuous address decode launch unit, 4...Write address selection unit 2.5.8.8'...Complement generation unit,
6...Write data parity check section, 7.7'...
・Comparison check unit, 9... Successive data parity check unit, 10... Failure detection signal terminal, a... Write data, b... Write address, C... Write address decode Shingetsu , d... Read address, e... Successive address decode signal, f... Read data, g... Output signal of write data parity check section, h... Output signal of write address selection section. , i...address signal, j...
・Output signal of successive data parity check section, k...
Failure Detection Patent Applicant NEC Corporation Representative Patent Attorney Nao Takaichi Ide 1 Figure 1 Figure 2 Tail 4 Figure

Claims (2)

[Claims] (1) A write address decode launch means for outputting a write address decode signal corresponding to an input write address; a read address decode launch means for outputting a read address decode signal corresponding to a subsequent manually input address; A register file comprising storage means for storing write data at an address designated by the write address decode signal and outputting successive data from an address designated by the read address decode signal. a first complement generation means for inputting the input data and outputting its complement; a write data parity check means for inputting the manually input write data and performing a parity check; and an output signal of the write data parity check means. write address selection means for selecting either the write address or the complement of the write address based on the write address and outputting a selection signal, the storage means decoding the selection signal to the write address. a second complement generation means for storing the selection signal at an address indicated by the signal and outputting the selection signal from the address indicated by the successive address decode signal, and further inputting the successive address and outputting its complement. means for inputting the successive data and performing a parity check on the successive data, and determining which of the successive addresses and the complement of the successive addresses based on the output signal of the successive data parity checking means. 1. A register file comprising: a comparison check means for selecting one of the selected signals and comparing it with a selection signal from the storage means; and a fault detection signal terminal connected to an output of the comparison check means. (2) Write address decode latch means for outputting a write address decode signal corresponding to the input write address; and read address decode latch means for outputting the successive address decode signal corresponding to the successive address to be input. , a register file comprising ↑α means for storing input write data at an address indicated by the write address decode signal and outputting successive data from an address indicated by the successive address decode signal, a first complement generating means for inputting the write address and outputting its complement; a write data parity check means for inputting the manually-generated write data and performing a parity check; write address selection means for selecting either the write address or the complement of the write address based on the output signal of the data parity check means and outputting a selection signal; further comprising means for storing a selection signal at an address designated by the write address decode signal and outputting the selection signal from an address designated by the successive address decode signal, and further inputting the selection signal from the storage means. and a third complement generation means for outputting the complement thereof; a successive data parity check means for inputting the successive data and performing a parity check; A register file comprising a comparison check means for selecting one of the selection signal and its complement and comparing it with the successive data, and a failure detection signal terminal connected to the output of the comparison check means. .