JPH0683718A - Fault detecting circuit - Google Patents

Abstract

PURPOSE:To detect even an address fault in addition to a data fault at the time of detecting faults in a storage circuit. CONSTITUTION:At the time of writing data in the storage circuit 1, data obtained by finding out exclusive OR between a part of writing data and the parity of the writing data by a writing data EX-OR circuit 2 and writing data which are not used for exclusive OR operation are together written in the circuit 1. At the time of reading out data from the circuit 1, exclusive OR data obtained between a part of data read out from the circuit 1 and the parity of writing data through a reading EX-OR circuit 3 and data which are not used for exclusive OR operation are together read out as reading data. The parity check of the reading data is executed by a parity checking circuit 4 to detect the presence of a fault.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault detection circuit,
In particular, the present invention relates to a failure detection circuit that detects a failure by checking read data with parity from a storage circuit with a parity check circuit.

[0002]

2. Description of the Related Art A conventional fault detection circuit of this type is, for example, a circuit shown in FIG. In FIG. 4, the memory circuit 1 is supplied with write data (4 bits + parity), a write address (2 bits) and a read address (2 bits). The write data is written in the memory circuit 1 by the write address and read from the memory circuit 1 by the read address. While the read data is used as read data,
The parity is checked by the parity check circuit 2, and if there is more than that, an error signal is transmitted (a failure is detected).

[0003]

However, in the conventional fault detection circuit shown in FIG. 4 described above, when a fault occurs in the data itself, the fault is detected.
When a failure occurs in the write address and the read address, the failure is not detected, and there is a drawback that the data is written to the wrong address or the data is read from the wrong address.

[0004]

According to a first aspect of the present invention, there is provided a fault detection circuit for detecting a fault by checking read data with parity from a storage circuit by a parity check circuit. A first EX-OR circuit that takes an exclusive OR of a part or all of read data and a parity bit of data read advice from the storage circuit; and the first EX
The output of the OR circuit and the first of the read data
The read check data is not input to the EX-OR circuit and the parity check circuit is included.

The fault detection circuit of the second invention is the first invention.
The fault detection circuit of the second aspect includes a second EX-OR circuit that performs an exclusive OR of a part or all of write data to the storage circuit and a parity bit of a data write address to the storage circuit, The data of the output of the second EX-OR circuit and the write data of the write data that is not input to the second EX-OR circuit is configured as the write data of the storage circuit.

[0006]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a fault detection circuit according to an embodiment of the present invention.

In FIG. 1, 1 is a memory circuit for writing data in a word indicated by a write address and reading data from a word indicated by a read address. 2 is an odd parity of read data. A parity check circuit 3 for sending an error signal, 3 is an EX-OR circuit for write data, the exclusive OR of the parity of the write data and the parity of the write address is taken and the output thereof is used as the parity of the write data to the storage circuit 1, Reference numeral 4 is an EX-OR circuit for read data, which takes the exclusive OR of the parity of the read data from the storage circuit 1 and the parity of the read address.

FIG. 2 is a diagram showing the relationship between the write address, write data and stored data of FIG. 1 of the present embodiment, and FIG. 3 shows the relationship of the read address, stored data and read data of FIG. 1 of the present embodiment. FIG.

Next, the operation of the present invention will be described.

In FIG. 1, the write address "00: 1"("
Data bit: parity "), write data" 111 "
When 1: 1 "is supplied," 0 "is stored in word 0 and parity of storage circuit 1, and" 11 "is stored in word 0 and bits 0-3.
11 "is stored (see FIG. 2). Further, when the write address" 01: 0 "and the write data" 1010: 1 "are supplied," 1 "is stored in the storage circuit 1 and the parity is stored in the word 1 "1010" is stored in bits 0 to 3 (see FIG. 2).

In this state, the read address "00: 1"
Is supplied, word 0 of the memory circuit 1 and parity ″
0 "and" 1111 "are read from the word 0 and bits 0 to 3, and" 1111: 1 "is output as the read data (see FIG. 3). The read data is also an odd number in the parity check circuit 2. The parity is checked, but no abnormality (fault) is detected and no error signal is output.When the read address "01:01" is further supplied, "1" is read from the word 1 parity of the memory circuit 1 and the word is read. 1
"1010" is read from bits 0 to 3, and "1010: 1" is output as read data (see FIG. 3). The read data is simultaneously subjected to an odd parity check by the parity check circuit 2, but no abnormality (fault) is detected and no error signal is output.

Next, a case where a failure occurs in the read address will be described.

In the above state, the read address "00: 1"
Should be supplied, but bit 1 failed in the middle
When 01: 1 "is supplied," 1 "is obtained from the word 1 parity of the memory circuit 1, and" 1 "is obtained from the word bits 0 to 3.
1010 ″ is read, and the read data is “1010:
0 ″ is output. The read data is simultaneously subjected to odd parity check by the parity check circuit 2, but an abnormality (fault) is detected and an error signal is output.

Next, the case where a write address failure occurs will be described.

In the above state, the write address "00: 1"
Should be supplied, but bit 1 failed in the middle
When 01: 1 "is supplied as the write address and" 1111: 1 "is supplied as the write data," 0 "is stored in the word 1 parity of the memory circuit and word 1 is stored in the bit 1 bit 0
In “3”, “1111” is stored.

In this state, the read address "01: 0"
Is supplied, "0" is read from the word 1 / parity of the memory circuit 1, and "111" from the word 1 / bits 0 to 3.
1 "is read and read data is output as" 1111: 0. "The read data is simultaneously subjected to an odd parity check by the parity check circuit 2, but an abnormality (fault) is detected and an error signal is output. .

In this embodiment, the memory circuit 1 has separate write addresses and read addresses, but there is no problem even if they are the same. In addition, although the write data and the read data of the memory circuit 1 are different, there is no problem in this case even if they are made the same by using a three-state element. Further, in the present embodiment, the EX- for write data is
The OR circuit 3 and the read data EX-OR circuit 4 take the exclusive OR of only the parity of the data, and take the exclusive OR of only 1 bit respectively, but the bit of the data is other than the parity. Other bits may be used, and there is no problem in taking the exclusive OR with the parity of the address for a plurality of data.

[0019]

As described above, the fault detection circuit of the present invention takes the exclusive OR of part or all of the read data from the memory circuit and the data read advice from the memory circuit, and the memory circuit. Only when a failure occurs in the data itself without increasing the number of bits in the memory circuit by taking the exclusive OR of part or all of the data written to memory and the parity bit of the data write address to the memory circuit. Not only that, even when a failure occurs in the write address and the read address, the failure can be detected, and the data error due to the failure occurrence can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a fault detection circuit of the present invention.

FIG. 2 is an explanatory diagram showing a relationship among a write address, write data, and stored data in the fault detection circuit shown in FIG.

3 is a diagram showing a relationship between a read address, stored data, and read data in the fault detection circuit shown in FIG.

FIG. 4 is a block diagram showing a conventional fault detection circuit.

[Explanation of symbols]

 1 Storage Circuit 2 Parity Check Circuit 3 EX-OR Circuit for Write Data 4 EX-OR Circuit for Read Data

Claims (2)

[Claims] 1. A fault detection circuit for detecting a fault by checking read data with parity from a storage circuit by a parity check circuit, and part or all of read data from the storage circuit and data from the storage circuit. A first EX-OR circuit that takes an exclusive OR with the parity bit of the read advice, and a read of the output of the first EX-OR circuit and the read data that is not input to the first EX-OR circuit A fault detection circuit comprising a parity check circuit for performing a parity check on data and detecting a fault. 2. The fault detection circuit according to claim 1,
A second EX-OR circuit is provided that takes the exclusive OR of part or all of the write data to the storage circuit and the parity bit of the write address to the storage circuit. A fault detection circuit, wherein data obtained by combining output and write data that is not input to the second EX-OR circuit among the write data is used as write data for the storage circuit.