JPH0561777A - Memory control circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Randomly switches between odd parity and even parity added to the data in the data storage circuit. [Structure] A data storage circuit 11, an odd parity generation check circuit 12, and an even parity generation check circuit 13 are connected to a data bus 14, and a parity storage circuit 16 connected to an address bus 15 is connected to the data storage circuit 11,
Further, it is connected to the data parity selection circuit 17, the parity error holding circuit 18, the odd parity generation check circuit 12, and the even parity generation check circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage control circuit which protects data by performing a parity check when transferring stored data onto a bus.

[0002]

2. Description of the Related Art In a conventional storage control circuit such as an information processing system, data is preserved by adding an odd parity bit or an even parity bit to transfer data and transferring the data to perform a parity check.

[0003]

In the conventional storage control circuit, since the parity check function is fixed to one of odd parity and even parity, when a data error which meets the condition of odd parity or even parity occurs. However, for a while, there was a drawback that errors could not be detected.

Therefore, an object of the present invention is to provide a storage control circuit that randomly switches the parity of a data storage circuit between odd parity and even parity.

[0005]

According to a first aspect of the present invention, storage means connected to a data bus and an address bus for outputting data to which a parity bit is added to the data bus and an odd parity and an even parity are alternately arranged. A parity selecting means for selecting and outputting, a parity storing means for storing the output of the parity selecting means and outputting an odd parity bit or an even parity bit to be added to the data of the storing means, and the parity storing means for storing the parity storing means. A check means for checking the parity of the data output from the storage means by the parity is provided.

According to the second aspect of the invention, the parity bit selecting means switches between odd parity and even parity each time a specific bit of the address bus has a predetermined significant polarity.

According to the third aspect of the invention, when the predetermined parity of the predetermined significant polarity of all the bits of the address bus is detected, the alternate selection between the odd parity and the even parity is switched.

[0008]

That is, according to the first aspect of the present invention, the odd parity bit and the even parity bit are switched and added to the write data, which is stored, and the parity of the read data is checked.

According to the second aspect of the present invention, every time the address is transferred to the address bus, the odd number parity and the even number parity are switched when the specific bit has a predetermined significant polarity.

According to the third aspect of the present invention, every time an address is transferred to the address bus, if a predetermined parity due to a predetermined significant polarity of all bits on the address bus is detected, odd and even parity are alternately selected. Switch.

[0011]

Embodiments of the storage control circuit according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows a first embodiment of the present invention. In the storage control circuit 10, the data storage circuit 1
The 1 / odd parity generation check circuit 12 and the even parity generation check circuit 13 are connected to the data bus 14. The parity storage circuit 16 connected to the address bus 15 is connected to the data storage circuit 11, and also includes a data parity selection circuit 17, a parity error holding circuit 18,
It is connected to the odd parity generation check circuit 12 and the even parity generation check circuit 13. The odd parity generation check circuit 12 and the even parity generation check circuit 13 are connected to the parity bit selection circuit 17.

The odd parity generation check circuit 12 and the even parity generation check circuit 13 are connected to the data bus 14.
When inputting the data of and writing process, each circuit
The data parity selection circuit 17 generates an odd parity bit and an even parity bit to be added to the data.
Output to. The data parity selection circuit 17 inputs the odd or even parity data stored in the parity storage circuit 16 during the read processing of the data storage circuit 11, checks the data according to its regularity, and if there is a parity error, This is the parity bit error holding circuit 1
Output to 8.

The data parity selection circuit 17 includes a specific bit on the address bus 15, for example, the least significant bit 20.
, And switches between odd and even parity selection when it is of significant polarity, "1" (or "0"). Then, in the writing process, one of the odd parity bit and the even parity bit input from the odd parity generation check circuit 12 and the even parity generation check circuit 13 is selected and output to the parity storage circuit 16. In the reading process, when an odd number parity error and an even number parity error are input, they are output to the parity bit error holding circuit 18. The parity error holding circuit 18 stores the parity error.

The parity storage circuit 16 has a common address with the data storage circuit 11, and when the address of the data storage circuit 11 is output to the address bus 15, an odd parity bit input from the data parity selection circuit 17 or The even parity bit is stored and output to the data storage circuit 11. The stored odd or even parity is output to the odd parity generation check circuit 12 and the even parity generation check circuit 13.

The data storage circuit 11 receives the address and the parity bit 22 from the parity storage circuit 16. When the address of its own circuit is output, in the write processing, the data input from the data bus 14 is added with an odd parity bit or an even parity bit and stored. In the read process, the parity data is output to the data bus 14.

The operation of the storage control circuit 10 will be described. The odd parity bit and the even parity bit added to the data of the data storage circuit 11 are determined by the parity selection of the data parity selection circuit 17. The parity is switched to the random selection because the address is output onto the address bus 15 and the parity selection is switched every time the least significant bit 20 thereof has a predetermined significant polarity. In reading the stored data, the odd parity generation check circuit 12 and the even parity generation check circuit 13 input the odd parity bits and the even parity bits stored in the parity storage circuit 16 to check the parity bits. When an error occurs, it is stored in the parity error holding circuit 18 as an odd parity bit and an even parity bit error. As mentioned above, since the odd parity bit and the even parity bit are switched at random,
A parity bit error that cannot be detected by one of the checks can be detected early.

FIG. 2 shows a second embodiment.
The storage control circuit 30 of FIG. 2 is obtained by adding an address parity bit generation circuit 32 to the storage control circuit 10 of FIG. The address parity bit generation circuit 32 is connected to the address bus 15 and outputs a selection pulse to the data parity selection circuit 1 when a predetermined significant pole of all address bits is an odd (or even) parity each time an address appears.
Output to 7. Since the data parity selection circuit 17 switches the selection of parity each time a selection pulse is input, it is possible to detect a failure even in a regular data error such as when the address bus and the data bus are short-circuited.

[0019]

As described above, according to the invention described in claims 1 to 3, the parity added to the storage data is alternately switched to the odd number and the even number, so that the conventional parity check fixed to one side is performed. The advantage is that errors can be detected quickly.

According to the second aspect of the present invention, since the switching of the parity is performed by the specific polarity of the specific bit of the address bus, there is an advantage that the switching of odd and even parity becomes close to random selection.

According to the third aspect of the present invention, since the data parity is switched by one of the odd number parity and the even number parity of all the address bits of the address bus, there are more options than the second aspect, and there is an advantage that it is closer to random selection. is there.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a configuration of a storage control circuit according to a first exemplary embodiment of the present invention.

FIG. 2 is a schematic configuration diagram showing a configuration of a storage control circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 10, 30 Storage control circuit 11 Data storage circuit 12 Odd parity generation check circuit 13 Even parity generation check circuit 14 Data bus 15 Address bus 16 Parity storage circuit 17 Data parity selection circuit 18 Parity error holding circuit 32 Address parity bit generation circuit

Claims (3)

[Claims] 1. A storage means connected to a data bus and an address bus for outputting data to which a parity bit is added to the data bus, and parity selecting means for alternately outputting odd parity and even parity, and outputting the parity. Parity storage means for storing the output of the selection means and outputting odd parity bits or even parity bits to be added to the data of the storage means, and the parity of the data output by the storage means by the parity stored by the parity storage means. And a check means for checking the storage control circuit. 2. The parity bit selection means is arranged such that each time a specific bit of the address bus has a predetermined significant polarity,
The storage control circuit according to claim 1, wherein the odd parity and the even parity are switched. 3. The storage control circuit according to claim 1, wherein when a predetermined parity of a predetermined significant polarity of all bits of the address bus is detected, odd parity and even parity are switched.