JPS6327940A - Storage controller - Google Patents

Abstract

PURPOSE:To improve the processing efficiency by recording only the first error out of correctable errors having the same syndrome of errors, which occur in a certain address range, in an error log and regarding errors having the same syndrome, which occur after said first error, as information of redundancy. CONSTITUTION:The address for read of a storage device 1 is temporarily stored in an address register 7 of a recording controller 2, and a read digital signal including an error correction code ECC is inputted to an ECC circuit 6. If an error is detected by the circuit 6, the syndrome of this error is inputted to a syndrome register 9. The syndrome related to each error is stored in a syn drome backup register 9a, and prescribed correctable bits of contents of the register 7 are stored in an address backup register 7a. Contents of registers 7a and 9a are compared with each other by a comparing circuit 11 and only recording of the first error out of frequently occurring errors is left, thus improv ing the processing efficiency.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention detects a code error (hereinafter referred to as an error) of 1 in data read from a storage device by a storage control device of a data processing device.
Regarding processing when it is detected that there is a 1-bit error in the read data,
When there is an error of 2 bits or more, ECC (
This relates to processing when an error correcting code (error correcting code) is added.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional storage control device. In the figure, (1) is a storage device, (2) is a storage control device, (3) is a processing device, (4) is a control circuit, and (5) is a storage device.
is an address generation circuit, (6) is an ECC circuit, (7) is an address register, (8) is a data register, (9) is a syndrome register, and (1O) is an error detection signal.

When writing data (in this specification, data includes instructions) to the storage device (1), the data to be written is sent from the processing device (3) to the data register (8).
), and the logical address of the storage device to which the data is to be written is set in the address register (7).

The data set in the data register (8) is input to the ECC circuit (6), an ECC bit is added thereto, and the data is sent to the storage device (1). On the other hand, the logical address set in the address register (7) is converted into a physical address of the storage device (1) by the control circuit (4) and the address generation circuit (5), and the physical address of the storage device (1) is converted to a physical address of the storage device (1). access and write the ECC-added data to that address location.

Next, when reading data from the storage device fi+, the storage device (1) is accessed using the output of the address generation circuit (5), and the ECC-added data read from the storage device (1) is processed through the ECC circuit. In step (6), the presence or absence of an error is checked, and the data portion thereof is set in the data register (8). The ECC added to data when writing can automatically correct a 1-bit error, and can detect the existence of a 2-bit or more error. Assume that it is configured as follows.

The test result of the ECC circuit (6) for the read signal is a) No error. (b)) Errors exist but can be corrected. H There is an uncorrectable error.

It is classified into three types. If there is no error (b), the contents of the data register (8) are output as is to the processing device (3), and if there is an uncorrectable error (c), processing for the uncorrectable error is executed. However,
In the case of A) and H, there is no difference between the operation in the conventional device and the operation in the device of the present invention, and therefore, there is no direct relationship to the present invention, so the explanation thereof will be omitted.

(If the error exists but is correctable, i.e., it is a 1-bit error in the above example, the ECC circuit (6) determines in which bit the error exists,
This is stored in the syndrome register (9), the error bit in the data register (8) is corrected, and the error detection signal (10) is output (that is, the signal (lO
] makes the logic significant).

In this case, the contents of the data register (8) have already been corrected and can be used as is in the processing device (3), but in conventional devices, the error that has occurred is analyzed and the overall reliability is determined. In order to improve performance, records of errors that occurred were kept. That is, the error detection signal (lO)
When this is output, the processing device (3) starts an error processing program, and stores the address value and the contents of the syndrome register (9) at that time in a file as an error log.

[Problem that the invention seeks to solve]

As described above, in conventional devices, the error handling program is always executed even though the contents of the data register (8) have already been corrected and are correct, which reduces the efficiency of the processing device (3). This causes a decrease in In order to avoid this, the error processing program is not executed in response to an error detection signal that indicates the occurrence of a correctable error. There was a problem with it being missed.

This invention was made to solve the above-mentioned problems (1).Errors that need to be recorded in the error log can be recorded without fail, and redundant records can be automatically omitted. The purpose is to obtain a storage control device that can

[Means for solving problems]

Considering the configuration of the storage device, there is a high probability that the syndrome of errors that occur within a certain address range will be the same. Therefore, in the device of this invention, correctable errors of the same syndrome occur within a certain address range. In this case, only the first error that occurred was recorded in the error log, and errors with the same syndrome that occurred twice were omitted from being recorded as redundant information.

[Effect]

This invention provides a syndrome backup register that temporarily stores the value of the previous syndrome register, and an address backup register that temporarily stores the upper bits of the address when the syndrome of the contents of the syndrome backup register occurs. A comparison circuit is provided to compare the bit patterns of a first signal in which the contents of the register and the contents of the address backup register are concatenated, and a second signal in which the contents of the syndrome register and the upper bits of the address register are concatenated. We decided to record the contents of the syndrome register and the upper bits of the address register only when the output of the circuit indicates a mismatch between the bit patterns of both inputs.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, the same symbols as in Figure 2 indicate the same or equivalent parts, and (7a) stores the upper bits of a predetermined number of bits of the contents of the address register corresponding to the correctable error that occurred one time before. This is an address backup register. For example, as a memory element of the memory device (1), 256
If we use a bit/chip element for the
= 256x2), and if the total number of bits of the address signal is 22 bits, then 22
-18 = 4 is the number of upper bits. Therefore, there are cases where the number of upper bits is zero. In this case, there is no need for the backup address register (7a), but in this invention, even when the number of upper bits is zero, it is stored in the address backup register (7a) for convenience. do. (9a)
a syndrome backup register that stores syndromes related to correctable errors that have occurred;
(10a) is an error processing signal, and (11) is a comparison circuit. The comparison circuit (11) registers the address backup register (7a) when the error detection signal (lO) is set.
) contents and syndrome backup register (9a)
The first signal concatenated with the contents of address register (7
) is compared with a second signal which is a concatenation of the contents of the syndrome register (9), and only when the bit patterns of the two do not match, the error processing signal (10
a).

Next, the operation of the apparatus shown in FIG. 1 will be explained.

The operation when writing data to the storage device (1), the operation when the data read from the storage device (1) is determined to be error-free by the inspection of the ECC circuit (6), and the operation from the storage device (1) The operation when it is determined that the read data has an uncorrectable error by checking the ECC circuit (6) is the same for the device shown in FIG. 1 and the device shown in FIG. 2, so a description thereof will be given below. Omitted.

Next, the contents of the address backup register (7a) and syndrome backup register (9a) are saved at the initialization stage as a precautionary measure in case a correctable error exists in the data read from the storage device (1). Reset it.

As explained with reference to FIG. 2, when the ECC circuit (6) detects a correctable error, the error detection signal (1
0), corrects the error bit in the data register (8), and sets information indicating the position of the error bit in the syndrome register (9).

When the error detection signal (10) is output, the comparison circuit (11)
) is a first signal in which the contents of the address backup register (7a) and syndrome backup register (9a) are concatenated, and a second signal in which the upper bits of the address register (7) and the contents of the syndrome register (9) are concatenated.
Compare the bit pattern with the signal. Since the registers (7, a) and (9a) are reset at the initialization stage, the comparison result of the comparator circuit (11) becomes inconsistent when the first error detection signal (10) is output, and error processing is performed. A signal (10a) is output.

Processing device by error processing signal (10a)! (3) starts an error handling program. After the error processing signal is issued, the upper bit of the address register (7) is set to the address backup register (7a), and the contents of the syndrome register (9) are set to the syndrome backup register (9a).

@If the error detection signal (10) is output for the second time,
If the comparison result in the comparison circuit (11) shows a match, the error processing signal (10a) is not output and the processing device (3) only uses the corrected data on the data register (8). , the error handling program does not start. This is because errors of the same syndrome within the same address range are considered to be caused by a failure of the same memory element, and it is sufficient to leave a quota for one piece of error data.

When a new type of error with a different address area or a different syndrome occurs, the comparison result by the comparator circuit (11) indicates a mismatch, and this new type of error is recorded.

〔Effect of the invention〕

As described above, according to the present invention, when the same type of error occurs frequently, it is possible to leave a record of only the error that occurs first, so that the processing device can be efficiently used to record redundant information. This has the effect that there is no need to reduce the

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional device. Fil is a storage device, (2) is a storage control device, (3) is a processing device, (6) is an ECC circuit, (7) is an address register, (7a) is an address backup register, (8)
is the data register, (9) is the syndrome register, (
9a) is the syndrome backup register, (10)
is an error detection signal, (10a) is an error processing signal, (1
1) is a comparison circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] When writing a digital signal to a storage device, an error correction code (hereinafter referred to as ECC) is added that can check for errors and correct them if the error is a 1-bit error. When a digital signal is read from the storage device, the read digital signal is checked for an error using the ECC, and if the error is a 1-bit error, it is corrected and output. In a storage control device, an address register temporarily stores an address signal for reading out the storage device, an ECC circuit to which a digital signal including ECC read from the storage device is input, and a correctable error in the ECC circuit. an error detection signal that is output when the error is detected; a syndrome register into which the syndrome of the error is input and temporarily stored when the ECC circuit detects the error; and a syndrome register that stores the syndrome related to the correctable error that occurred the previous time. a syndrome backup register; an address backup register that stores a predetermined number of high-order bits of the contents of the address register corresponding to the correctable error that occurred one time before; the contents of this address backup register and the syndrome backup register; means for resetting at the time of initialization, a signal which concatenates the upper bits of the address register and the contents of the syndrome register, and the contents of the address backup register and the syndrome backup register while the error detection signal is output. a comparison circuit that compares the connected signals; outputs an error processing signal when the output of this comparison circuit indicates a comparison mismatch; and inputs the upper bits of the contents of the address register to the address backup register; A storage control device comprising: means for inputting the contents of the syndrome register into a syndrome backup register; and means for activating an error processing program in response to the error processing signal.