JPH05165734A - Fixed fault diagnostic device for main storage device - Google Patents

Abstract

PURPOSE:To generate a diagnostic program detecting the fixed fault of a redundant data memory part without considering complicated correction logic by providing a redundant data inversion circuit for the input/output part of a redundant data memory. CONSTITUTION:A redundant data generation circuit 2 generates redundant data written into the redundant memory 3 from write data written into a main storage data memory 1. A redundant data inversion flag 6 is directly set by a central processing unit and the outputs of selectors 5a and 5c are selected by the signal state of the flag 6. Thus, redundant data is logic-operated by logic inverting it by a NOT circuit 5b and writing it into the redundant data memory 3 or by writing it in a logical state as it is. Furthermore, a signal obtained by logic-inversion in a NOT circuit 5d or a signal as it is selected in the selector 5c by the signal state of the flag 6, and it is outputted to an error detection/correction circuit 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fixed failure diagnosis method for a main memory device, and more particularly to a fixed failure diagnosis device for a main memory device for diagnosing a fixed failure of a redundant component provided in the main memory device.

[0002]

2. Description of the Related Art An ECC (Error checking a) which detects a bit error of read data due to a hardware error of a read / write memory directly accessible from a central processing unit and carries out a redundancy check for correcting the error.
Although there has been a main memory device with a redundant configuration unit including an nd correction) circuit and the like, there are the following two diagnostic methods for detecting a fixed fault due to a circuit failure or the like of the redundant configuration unit.

The first method considers the correction logic of an error detection / correction circuit, which is hardware, and creates data such that the data in the redundant configuration section changes according to a diagnostic program, and uses the data to create the redundant configuration section. This is a method of detecting the fixed fault of.

The second method is to directly change the data in the redundant part by allocating an independent main memory space so that the central processing unit can directly access the redundant part, thereby fixing a fixed fault in the redundant part. It is a method of diagnosis.

[0005]

However, in the above-mentioned first method in which the correction logic is considered in the diagnostic program, the diagnostic program depends on the correction logic of the hardware. Therefore, when the correction logic is changed by the change of the hardware. In addition, the diagnostic program must be changed accordingly. The work of changing the diagnostic program that only detects the fixed fault in the redundant component is an additional work in the system design stage, and the change is very troublesome.

Further, in the above-mentioned second method of allocating the main memory space of the independent central processing unit, it is necessary to reserve a limited main memory space only for the diagnosis of the redundant constituent parts, and in the normal system operating state. In addition to reducing the accessible memory space of the central processing unit, it also has the drawback that the data of the redundant component may be accidentally rewritten by an external factor during system operation.

[0007]

The redundant component of the present invention comprises a circuit for inverting the stored data according to an instruction from software. The diagnostic program first writes / reads the main memory without inverting the redundant part and then inverts the redundant part to write / read the same data in the main memory. This operation changes the data in the redundant component.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to FIG.
FIG. 1 is a block diagram of a read / write main memory device and circuits associated therewith according to an embodiment of the present invention. A data bus is connected to the data input / output terminal of the main memory data memory 1 so that the write data can be directly written to the main memory data memory 1, and the data read from the main memory data memory 1 is used for error detection / It is also connected so as to be input to the correction circuit 4. The output terminal of the error detection / correction circuit 4 is connected to the data bus and is connected to the data input / output terminal of the central processing unit (not shown). Further, the data bus is connected to the redundant data creating circuit 2.
The output of the redundant data creating circuit 2 is input to the NOT circuit 5b of the redundant data inverting circuit 5 and one input terminal of the selector 5a, and the output terminal of the NOT circuit 5b is input to the other input terminal of the selector 5a. It is connected. The output terminal of the selector 5a is connected to the redundant data memory 3 as a write data signal to the redundant data memory 3. Further, the data read from the redundant data memory 3 is connected so as to be input to the NOT circuit 5d of the redundant data inverting circuit 5 and one input terminal of the selector 5c, respectively, and the output terminal of the NOT circuit 5d is It is connected to the other input terminal of the selector 5c.
Then, the output of the selector 5c is the error detection / correction circuit 4
Has been entered in. The select terminals of the selectors 5a and 5c are connected so that the signal from the redundant data inversion flag 6 is input, and each selector selects one of the two input signals according to the signal of the redundant data inversion flag 6. Select or output.

In the above configuration, the redundant data memory 3
The redundant data written in the redundant memory is written by the redundant data creating circuit 2 from the write data written in the main memory data memory 1. The redundant data is subjected to the following processing in the redundant data inverting circuit 5. The redundant data inversion flag 6 is directly set by the central processing unit, and the outputs of the selectors 5a and 5c are selected by the signal state of the flag 6 as described above.
The redundant data memory 3 is logically inverted by the T circuit 5b.
, Or is written in the logical state as it is.

The read data read from the main memory data memory 1 is corrected for errors only when the error detection / correction circuit 4 detects an error from the contents of the main memory data memory 1 and the redundant data memory 3. Is output,
The redundant data read from the redundant data memory 3 in this case is either a signal logically inverted by the NOT circuit 5d in the selector 5c or a signal that is not subjected to logical operation depending on the signal state of the flag 6. It is selected and output from the error detection / correction circuit 4. In other words, the inverting circuit 5 performs a logical operation that is completely opposite to that at the time of writing the redundant data and outputs it to the error detecting / correcting circuit 4. This means that the operations performed by the NOT circuit 5b and the selector 5a are reversed.

FIG. 2 shows an example of the flow of a diagnostic program for detecting a fixed failure in the main memory data memory and the redundant data memory portion of the main memory device shown in FIG. All main memory data Main memory data is obtained by writing once all data with "0" or "1" to memory 1 and reading again to identify whether the read data is different from the write data. The fixed failure of the memory 1 can be detected. Also, after confirming that there is no fixed fault by the fixed fault check by writing / reading data to / from the main memory data memory 1, the redundant data inversion flag 6 is changed so that the redundant data to be written in the redundant data memory 3 can be written. The data is intentionally converted, and is inversely converted again at the time of reading. As a result, if there is a fixed fault in the redundant data memory 3, the output data from the faulty portion is always fixed to a fixed value. Therefore, by changing only this write redundant data, it is fixed in the redundant data memory 3. It can be determined whether there is a fault.

[0012]

As described above, according to the present invention, it is possible to create a diagnostic program without allocating a main memory space for diagnosing a redundant component and without considering a complicated correction logic. In addition, even if the correction logic is changed, there is an effect that it does not affect the diagnosis program. Therefore, even when the hardware has to be changed due to various circuit factors, the diagnostic program created in the past can be used as it is, so that more rapid hardware check can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of hardware according to an embodiment of the present invention.

FIG. 2 is a flow chart of a diagnostic program for the hardware shown in FIG.

Claims (1)

[Claims] 1. A read / write storage device, a redundant data creating circuit for creating redundant data for bit error correction of the write data by using write data to the read / write storage device, and the read / write storage device. In a fixed fault diagnosis device of a main memory device having an error detection / correction circuit having a bit error correction function for read data, the redundant data created by the redundant data creation circuit is logically operated and is not operated logically. A first selection circuit for selecting one of the redundant data and writing it in the redundant data memory area secured in the read / write storage device; and after writing to the redundant data memory, output from the redundant data memory Logical operation is not performed on the redundant data that has been subjected to the logical operation that is the reverse of the logical operation of the first selection circuit. Redundant data inversion circuit composed of a second selection circuit for selecting long data and outputting it to the error detection / correction circuit, and a redundant data inversion flag for giving a selection instruction to the first and second selection circuits. A fixed failure diagnosis apparatus for a main storage device, comprising: