JPH06301604A - Storage reproducing system - Google Patents

Abstract

PURPOSE:To provide a storage reproducing system capable of detecting an address error by a comparatively compact circuit without being influenced by the size of address information. CONSTITUTION:This memory reproducing system is provided with a memory 1, a data register 2, an ECC register 3, an address register 4, an 11 ECC generating circuit 5, an ECC check correcting circuit 6, a parity generating circuit 7 for generating a parity from the address value of the register 4, an EOR circuit 8 for executing the inversion/noninversion of write data, an EOR circuit 10 for inverting an address parity outputted from circuit 7 in accordance with the checked result of the circuit 6, and an EOR circuit 9 for executing the inversion/non-inversion of read data in accordance with the address parity and constituted so as to verify an address error by inverting/non-inverting writing data in accordance with the address parity, and at the time of reading out the inverted/non-inverted data from the memory 1, inverting/non-inverting the data in accordance with the address parity and an ECC check result, thin, verifying the address error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage / reproduction technique,
In particular, the present invention relates to a technique effective in improving the reliability of operation in a storage device using a semiconductor memory.

[0002]

2. Description of the Related Art For example, in a storage device using a semiconductor memory device as a storage medium, verification of an address associated with input / output of data is important from the viewpoint of improving operation reliability. Conventionally, as a technique for verifying such an address, for example, the technique disclosed in Japanese Patent Laid-Open No. 55-8617 has been known. That is, in this technique, when the error correction code is generated, the address information and the stored data are paired to generate the error correction code, and when the data is read, it is detected that an error corresponding to the address information exists, and the address error is detected. It is a notification.

[0003]

In the above prior art, the error correction code is generated by combining the address information and the stored data. However, when only a part of the address information is used, all the addresses in the memory are No address error can be detected for space. That is, when it is necessary to detect an address error in the entire address space of the memory, the error correction code must be generated using all the address information.

Therefore, there is a problem that the scale of the logic circuit for detecting the address error increases in proportion to the size of the address information.

An object of the present invention is to provide a storage / reproduction technique capable of detecting an address error with a relatively small circuit without being affected by the size of address information.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the present invention, a memory, a data register for temporarily holding input / output data for the memory, an address register for temporarily holding an address of a memory to be accessed, and an error correction code for the input / output data. An error correction code generation circuit that generates the error correction code, an error correction code register that temporarily holds the generated error correction code, and an error check correction circuit that checks and corrects errors in input / output data based on the error correction code. In a storage / reproduction system including a memory, a parity generating unit that generates a parity of an address of a memory to be accessed, and data that performs an inversion operation or a non-inversion operation of input / output data based on at least one of a parity and a processing result in an error check correction circuit Equipped with reversing means, And detects the error address from the check result and accessed parity value of the address of the memory to be output from the click correction circuit.

[0009]

The above-described storage / reproduction system of the present invention operates as follows as an example.

First, at the time of writing, after an error correction code is generated from the data, an inversion operation or a non-inversion operation is performed on a part or all of the data according to the parity value generated from the write address information of the data. Giving,
Write to memory with error correction code.

At this time, the parity to be generated may be either odd parity or even parity. When only a specific part of the data is inverted, the number of bits of the inverted part must be a value exceeding the error correction capability of the error correction code.

Due to such a write operation, non-inverted data and inverted data corresponding to the parity of the address information exist in the memory.

On the other hand, when reading data, first, a parity is generated from the read address information, and the read data is subjected to an inversion operation or a non-inversion operation according to the value of the parity, and then, together with the data. An error check is executed using the read error correction code. At this time, if there is no error, the data is output as it is, and if the error can be corrected by the error correction code, it is corrected as an error of the read data. If the data cannot be corrected, the data inversion operation is unconditionally performed, and the error check is performed again using the error correction code. As a result, if no data error can be detected,
An address error has been detected. When an error in the data is detected, it means that an error in the data that cannot be corrected is detected.

As described above, according to the present invention, it is possible to detect a 1-bit error of an address due to noise or the like from the parity of the address information and the error check result of the error correction code of the data, which is necessary as the address information increases. It is not necessary to increase the circuit scale more than that.

Further, when the data is read, if the inverted data and the non-inverted data are generated at the same time from the data and the above-mentioned error check using the error correction code is executed in parallel, the data error and the address error are further improved. The speed can be increased.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A storage / playback system according to an embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of the storage / reproduction system of this embodiment, and FIG. 2 is a conceptual diagram showing an example of its operation. 3 and 4 are flowcharts showing an example of the operation.

The storage / reproduction system according to the present embodiment includes, for example, a memory 1 including a storage medium such as a semiconductor memory,
A data register 2 in which data input / output to / from the memory 1 is stored, and an error correction code (ECC: Error) generated from the data stored in the data register 2 and input / output to / from the memory 1 together with the data. Correcti
ng Code) and an ECC register 3 for holding the read / write address of the target data in the memory 1.

The ECC register 3 includes a data register 2
The ECC generation circuit 5 for generating an error correction code from the write data set to the read data read from the memory 1 via the data register 2 and the ECC register 3 and the error correction code corresponding to the read data. An ECC check / correction circuit 6 for executing error check and error correction of read data is connected.

In this case, the memory 1 of the address register 4
A parity generation circuit 7 that generates parity from the address set in the address register 4 is connected to the output side of the parity register 7. The output from the parity generation circuit 7 is an input / output path for write data to the data register 2. It is one of the inputs of an EOR (exclusive OR) circuit 8 interposed between the two. And the write data is EOR
When passing through the circuit 8, it is inverted or non-inverted according to the parity of the write address set in the address register 4 and held in the data register 2.

The address parity output from the parity generation circuit 7 is input via the EOR circuit 10 to the input of the EOR circuit 9 provided on the read data path from the data register 2 to the ECC check correction circuit 6. Has become. The other input terminal of the address parity in the EOR circuit 10 is connected to the E in the ECC check correction circuit 6.
A parity inversion signal output when uncorrectable by CC is detected is input, and the read data inversion operation in the EOR circuit 9 operates so as to be the reverse of the normal address parity inversion operation.

An example of the operation of this embodiment will be described below.

Writing of data to the memory 1 is performed as follows. First, the parity generation circuit 7 generates an address parity from the memory address set in the address register 4. Next, the address parity and the write data are calculated by the EOR circuit 8, and the inversion operation or non-inversion operation (for example, parity = 1: inversion, parity = 0: non-inversion) of the write data according to the address parity is executed. After that, the data is set in the data register 2. At the same time, the ECC generation circuit 5 generates an ECC of the write data before undergoing the inversion or non-inversion operation, and sets it in the ECC register 3. After that, the write data set in the data register 2 and the ECC set in the ECC register 3 are written as a pair to the address of the memory 1 designated by the address register 4. The data write operation as described above is shown in the flowchart of FIG.

On the other hand, the reading of data from the memory 1 is performed as follows. First, the memory 1 designated by the read address set in the address register 4
After reading the data and the corresponding ECC from the address of 1 and storing them in the data register 2 and the ECC register 3, respectively, the parity and the data of the read address generated by the parity generation circuit 7 are calculated by the EOR circuit 9, and the data After the inversion or non-inversion processing, the ECC check / correction circuit 6 checks and corrects the data to obtain read data.

The detection of the address error or the data error is performed by the ECC check correction circuit 6 when the data is read from the memory 1. The data stored in the memory 1 is stored in the inverted or non-inverted state corresponding to the parity of the address, as illustrated in FIG.
In this state, assuming that a 1-bit error has occurred in the read address "011", the address error is detected as "111", "0" as an incorrect address value.
There are three cases of "01" and "010", and read data is read from one of these three addresses.

The data read corresponding to these three incorrect addresses are all non-inverted data as illustrated in FIG. 2, but the correct read address "011" of the data set in the address register 4 is set. In accordance with the parity value of "", the EOR circuit 9 performs the inversion process, and the ECC check correction circuit 6 checks the error.

As a result of this check, when an uncorrectable ECC error is detected, the parity inversion signal is output to the EOR circuit 10 and the parity input to the EOR circuit 9 is inverted. Due to the inversion of the parity, the data read from any of the above-mentioned three erroneous addresses is inverted again, and is checked again by the ECC check correction circuit 6. If no data error is detected as a result of this second check, it means that a 1-bit error in the address has been detected and an address error is output. At this time, if another data error is detected, it means that an uncorrectable error of the data itself is detected, and the data error is output. The above data read operation is shown in the flowchart of FIG.

An address error at the time of writing can be detected at the time of reading because the parity of the address in the memory 1 does not match the inverted or non-inverted state of the data read at the address.

It goes without saying that the data error can be detected by a general ECC detecting method.

As described above, according to the storage / reproduction system of the present embodiment, it is possible to detect a 1-bit error in the address of the memory 1 with a relatively small circuit configuration. In addition, as in the prior art, the EC is paired with address information and data.
Since it is not necessary to generate C, an address error can be detected by using a general-purpose ECC generation / correction circuit for data lengths such as 32 bits, 64 bits, and 128 bits. Further, the ECC generation / correction circuit can be simplified even when the address length is relatively long with respect to the data length.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

[0032]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the storage / reproduction system of the present invention, it is possible to detect an address error with a relatively small circuit without being affected by the size of the address information.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of a storage / reproduction system that is an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an example of the operation.

FIG. 3 is a flowchart showing an example of the operation.

FIG. 4 is a flowchart showing an example of the operation.

[Explanation of symbols]

 1 memory 2 data register 3 ECC register 4 address register 5 ECC generation circuit 6 ECC check correction circuit 7 parity generation circuit (parity generation means) 8 EOR circuit (data inversion means) 9 EOR circuit (data inversion means) 10 EOR circuit (data (Reversing means)

Claims (1)

[Claims] 1. A memory, a data register for temporarily holding input / output data for the memory, an address register for temporarily holding an address of the memory to be accessed, and an error correction code for the input / output data. Error correction code generation circuit, an error correction code register that temporarily holds the generated error correction code, and an error check correction circuit that checks and corrects errors in the input / output data based on the error correction code And a parity generation means for generating a parity of an address of the memory to be accessed, and an inversion operation of the input / output data based on at least one of the parity and a processing result in the error check correction circuit. Or a data inversion means for performing non-inversion operation A storage / reproduction system comprising: a check result output from the error check / correction circuit and an address error detected from a parity value of an address of the accessed memory.