JP2001202793A - Error correction encoding method in semiconductor storage, device and semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which the number of correctable errors can be increased without increasing ECC codes. SOLUTION: At the time of recording, a data region of one page is divided into first and second regions, first and second error correction codes are generated and added to data depending on the first or the second regions respectively, the third error correction code is generated and added to data in a whole region of one page. Syndrome of the first and the second regions are obtained from data read out from the first and the second regions at the time of read-out and reproduced data of the first and the second error correction codes generated and added for the first and the second regions respectively, further, the number of errors is judged from reproduced data read out from a whole region of one page and reproduced data of the third error correction code, error states in the first region and the second region are judged by the first and the second syndrome and the number of errors, and error correction processing is performed, and connection of two bits error data can be performed as far as an error of one bit is generated in each region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ECC (Error
The present invention relates to an error correction coding method and a semiconductor memory device in a semiconductor memory device which add a Correcting Code to address a memory cell defect.
The present invention relates to a technique for improving the error correction capability without increasing the number of bits of a CC code.

[0002]

2. Description of the Related Art In a flash memory, when erasing / rewriting is repeated, cell defects occur randomly due to deterioration of an oxide film. Therefore, the use of ECC has been used to improve reliability.

That is, at the time of recording, arithmetic processing is performed on data of a predetermined unit to generate an ECC code,
An ECC code is added to the recording data, and writing to the memory cell is performed. At the time of reading, arithmetic processing is performed from the data read from the memory cells and the ECC code, the presence or absence of an error and the position of the error are detected, and if correction is possible, error correction is performed.

In a NAND flash memory, a plurality of memory cells having floating gates are cascaded to form a NAND memory string. The gates of the memory cells arranged in the row direction are connected to a common word line to form a page. The size of one page is, for example, 512 bytes. Data writing / reading is performed in page units.

[0005] As shown in FIG. 5, the most common configuration of the NAND type flash memory at present is to store one page in 5 pages.
12-byte data area and 1 that entrusts usage to the user
And a 6-byte spare area. Since the data area is 512 bytes, 512 = 2 ⁹ and if there are eight I / O buses, there are nine address buses.

[0006] In the NAND flash memory having such a configuration, the ECC code of each page is stored in the 16 bytes of the spare area in addition to the management area information of each page. As an ECC method, a method in which three bytes are assigned to an ECC code and which can perform one-bit correction and two-bit detection is used.

1-bit correction, 2-bit detectable ECC
The code is generated as shown in FIGS.

(1) Code generation in the row direction R0B = {addition of modulo 2 to all data whose address "A0" is "0" (see FIG. 6) R0N = {all of address "A0" is "1" R1B = {addition of modulo 2 of all data whose address "A1" is "0"} (see FIG. 8) R1N = {address "A1" is "1" R8B = {addition of modulo 2 for all data with address "A8" of "0" R8N = {addition of modulo 2 for all data with address "A8" of "1" (2) Code generation in column direction C0B = {addition of modulo 2 to all data of I / O0, 2, 4, and 6} (see FIG. 10) C0N = {I / O1, 3, 5 and 7 modulo 2 of all data Addition (see FIG. 11) C1B = {modulo 2 addition of all data of I / O0, 1, 4, 5} (see FIG. 12) C1N = {all data of I / O2, 3, 6, 7 C2B = {modulo 2 addition of all data of I / O0, 1, 2, and 3} (see FIG. 14) C2N = {I / O4, 5, 6, 7 (Modulo 2 addition of all data) (see FIG. 15) From the above, the capacity required for the ECC code is 2 × 9 + 2 × 3 = 24 bits = 3 bytes. The generated ECC code is also written together. The features of this ECC code are "R0B, R0N",
"R1B, R1N", ... "R8B, R8N", "C0
B, C0N "," C1B, C1N "," C2B, C2
N ”is always included in one operation. This feature makes it easy to specify the number of errors and the position of the error at the time of reading.

At the time of reading, a syndrome is obtained as follows.

(1) Generation of syndrome in the row direction S0B = ｛R0B, modulo 2 addition of all data with address “A0” of “0”｝ S0N = ｛R0N, all of address “A0” with “1” S1B = ２R1B, modulo 2 addition of all data whose address “A1” is “0”｝ S1N = ｛R1N, modulo addition of all data whose address “A1” is “1” Addition of 2｝ S8B = モ ジ ュ R8B, modulo 2 addition of all data whose address “A8” is “0”｝ S8N = ｛R3N, modulo of all data whose address “A8” is “1” Addition of 2｝ (2) Code generation in column direction D0B = {C0B, I / O0, 2, 4 and 6 modulo 2 addition｝ D0N = ｛C0N, I / O1, 3, 5, 7 Of all data Addition of Juro 2１ D1B = ｛Modulo 2 addition of all data of C1B, I / O 0, 1, 4, 5｝ D1N = ｛Modulo 2 of all data of C1N, I / O 2, 3, 6, 7 D2B = {addition of modulo 2 of all data of C2B, I / O 0, 1, 2, 3} D2N = {addition of modulo 2 of all data of C2N, I / O 4, 5, 6, 7} ｝ Here, if no error has occurred, the syndromes S0B to S8B, S0N to S8N, D0B to D2B,
D0N to D2N are all "0".

If there is a one-bit defect, the defective cells are "S0B, S0N", "S1B, S1N",.
"S8B, S8N", "D0B, D0N", "D1B,
D1N "and" D2B, D2N "are always included in one operation, and therefore, one of each pair always becomes" 1 "due to the inversion of the data of the defective cell.

For example, the "I / O" of the address "15A"
If an error has occurred in “3”, the address “15”
"A" is "A8 = 1", "A7 = 0", "A6 = 1",
“A5 = 0”, “A4 = 1”, “A3 = 1”, “A2 =
0, “A1 = 1”, and “A0 = 0”, so “S8
N "," S7B "," S6N "," S5B "," S4
N "," S3N "," S2B "," S1N "," S0
B is set to “1”, and “S8B”, “S7N”, “S6”
B "," S5N "," S4B "," S3B "," S2
“0” stands for “N”, “S1B”, and “S0N”.

Here, S8N × 2 ⁸ + S7N × 2 ⁷ + S6N × 2 ⁶ + S5N ×
^{2 5 + S4N × 2 4 +} S3N × 2 3 + S2N × 2 2 + S
Calculating the ^{1N × 2 1 + S0N × 2} 0, "1 1010 binary indication 010
"1", which is "15A" in hexadecimal, which indicates that there is an error at the address "15A".

Also, since there is an error in "I / O3",
“1” stands for “D2B”, “D1N”, and “D0N”, and “0” stands for “D2N”, “D1B”, and “D0B”.

Then, when D2N × 2 ² + D1N × 2 ¹ + D0N × 2 ⁰ is calculated, it becomes “3”, and I, in which an error has occurred, is obtained.
/ O is found to be "I / O3", and when outputting data at address "1A5" at the time of data output,
By inverting and outputting "/ O3", correct data can be output.

If there is a 2-bit defect, for example, defect 1: I / O3 at address "15A" defect 2: if I / O7 at address "15A" has a defect, paying attention to "D2B, D2N"
Since the defect 1 is included in the calculation of “D2B” and the defect 2 is included in the calculation of “D2N”, “D2B, D2N” is “1,1”. If both are "1" in this pair, it is recognized that there is a 2-bit defect.

Although it is recognized that there is a 2-bit defect,
Since a Hamming code cannot correct a defect of 2 bits or more, it merely indicates that the system has a 2-bit defect.

When an error occurs only in the ECC code, for example, when a defect occurs only in “ROB”,
"1" stands only for "S0B", and all become "0" thereafter. In this case, that is, when only one “1” is set, it is determined that the error code is defective, and the data is output as it is.

[0019]

As described above, in the conventional method, one page is 3 bytes for 512 bytes of data.
When ECC processing is performed by allocating a byte ECC code, one error correction processing is possible. However, if you try to have more error correction capabilities,
This time, the ECC code becomes redundant and the circuit scale increases.

It is therefore an object of the present invention to provide an error correction encoding method and a semiconductor memory device in a semiconductor memory device which can increase the number of errors that can be corrected without increasing the number of ECC codes.

[0021]

SUMMARY OF THE INVENTION According to the present invention, a semiconductor memory in which memory cells arranged in a row direction are connected to a common word line and writing / reading is performed in units of pages composed of the memory cells connected to the common word line. In an error correction method in an apparatus, a data area of one page is set to a first data area during recording.
And a second area, a first error correction code is generated and added by the first area, and a second error correction code is generated and added by the second area. A third error correction code is generated and added according to the area, and at the time of reading, from the data read from the first area and the reproduction data of the first error correction code generated and added to the first area. The syndrome of the first area is obtained, and the syndrome of the second area is obtained from the data read from the second area and the reproduction data of the second error correction code generated and added to the second area. Further, the number of errors is determined from the reproduction data read from the entire area of one page and the reproduction data of the third error correction code, and the number of errors is determined based on the first and second syndromes and the number of errors. , To determine the error condition in the first region and the second region, the error correction coding method in the semiconductor memory device to perform the error correction process.

According to the present invention, in a semiconductor memory device in which memory cells arranged in a row direction are connected to a common word line and writing / reading is performed in units of pages composed of memory cells connected to the common word line, Means for dividing a data area of one page into a first area and a second area, generating and adding a first error correction code using the first area, and generating a second error correction code using the second area Adding means for generating and adding a third error correction code using the entire area of one page, and generating and adding to the data read from the first area and the first area at the time of reading. Means for obtaining a syndrome in the first area from the reproduced data of the first error correction code, and a second error correction generated and added to the data read from the second area and the second area. Means for determining the syndrome of the second area from the reproduced data of the code, and means for determining the number of errors from the reproduced data read from the entire area of one page and the reproduced data of the third error correction code. , First
And a means for performing an error correction process by determining an error state in the first area and the second area based on the syndrome and the second syndrome, and the number of errors.

The data of one page is divided into two areas,
An ECC code of a Hamming code is generated and added to each area, and modulo 2 is added to all the areas. As a result, error data can be corrected only when an error of one bit occurs in each area. In this case, if the data of one page is divided into an area smaller than half the number of data of one page and an area larger than half the number of data of one page, the number of bits allocated to the ECC code does not increase.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. As described above, one page is a 512-byte NAND flash memory and E
Conventionally, when a CC is added, a 3-byte ECC code is added to one page of 512-byte data. In this case, one-bit error can be corrected in one page.

On the other hand, in the embodiment of the present invention, similarly to the conventional example, a 3-byte ECC code is added to 512-byte 1-page data, and although there is a condition, the Correction of two-bit errors is enabled.

Hereinafter, generation of ECC in a NAND flash memory to which the present invention is applied will be described in detail.

In the embodiment of the present invention, a Hamming code is used as the ECC system. The Hamming code is such that each column of the parity check matrix has all different m-dimensional 2
This code is composed of the original column vector, and single error correction is possible.

In the Hamming code, the relationship between the number of data bits and the number of ECC code bits is as follows.

Number of data bits ECC code ---------------------------------------------------------- (512) to 1013 10 bits ~ (1024) ~ 2036 11 bits ~ (2048) ~ 4083 12 bits ~ (4096) ~ 8178 13 bits.

From the above relationship, when an ECC code by a Hamming code is added to 512-byte data for one page, 512 bytes = 4096 bits, so that a 13-bit ECC code is added. It will be good. However, if the ECC code is added to the data of one page using the Hamming code,
Only one-bit error correction can be performed.

Therefore, in the embodiment of the present invention, FIG.
A, one page of data is stored in two areas AR1.
And AR2, as shown in FIGS. 1B and 1C,
For each area AR1 and AR2, an EC using a Hamming code
C code E _A and E _B are to generate added.
Further, as shown in FIG. 1D, an ECC code E _C is generated and added to the data of the entire area of one page.

In FIG. 1, the data area of one page is
It is 512 bytes. This 512-byte data is
192 byte area AR1 and 320 byte area AR
It is divided into two. The ECC code E _A is obtained from the data of the area AR1 of 192 bytes by the Hamming code. Further, the ECC code E _B determined by Hamming code from the data of 320-byte area AR2. 512
The ECC code E _C is obtained from the data of the entire area of one page of bytes. These, ECC code E _A, E _B,
The ECC code E _C is provided in the ECC area AR3.

ECC code E _A generated in area AR1
Is a Hamming code, and since the number of data in the area AR1 is 192 bytes = 1536 bits, the ECC code E _A is 11 bits from the above table.

ECC code E _B generated in area AR2
Is Hamming code, the number of data in the area AR2 is because it is 320 bytes = 2560 bits, from the above table, ECC code E _B is 12 bits.

EC generated in all areas AR1 and AR2
The C code E _C is obtained by modulo 2 addition (exclusive OR) of all data. The number of bits of this ECC code E _C is 1 bit.

Therefore, the ECC added in this case is
The total number of codes is 11 + 12 + 1 = 24 bits = 3 bytes. This is the same as in the above-described conventional example.

As described above, when this 512-byte data is divided into a 192-byte area AR1 and a 320-byte area AR2, for each of the areas AR1 and AR2,
One-bit error correction is possible. Therefore, the area A
When a one-bit error has occurred in each of R1 and area AR2, error correction is possible.

In this example, the data of one page of 512 bytes is not divided equally into 256 bytes, and 192 bytes are not divided.
It is divided into a byte area AR1 and a 320-byte area AR2. In this way, the area is divided into an area smaller than 256 bytes and an area
By generating and adding a C code, the number of bits can be reduced.

That is, if one page data of 512 bytes is equally divided into 256 bytes, 256 bytes = 2048 bits. Therefore, it is necessary to provide 12 bits of ECC code in each area. Is 12 + 12 + 1 = 25, which is larger than 3 bytes.

As described above, when the area of one page is divided into two areas AR1 and AR2, and an ECC code based on a Hamming code is generated and added to each area AR1 and AR2,
There is a condition that a 1-bit error occurs in each of the areas AR1 and AR2, but 2-bit error correction is possible.

[0041] At the time of reading, the syndrome S obtained by the reproduction data of the area AR1 and the reproduction ECC code E _A
A , the reproduction data of the area AR2 and the reproduction ECC code E _B
A syndrome S _B obtained by the, from the syndrome S _C obtained by the reproduction ECC code E _C and data of all areas, as follows, the error is determined.

Since the syndrome S _C is obtained by adding modulo 2 to the data of the entire area of the ECC code E _C, if the number of errors is “0”, it becomes “0”. If an error occurs, the error number is "0" if the number is even and "1" if the error number is odd, indicating whether the number of errors is even or odd. Here, the hamming code is an error correction method adopted for an extremely low error occurrence rate. Therefore, if an error of 3 bits or more does not occur, an even number of errors is defined as an error number. Is assumed to be "2" and the number of errors is odd because the number of errors is assumed to be "1", and the determination process is simplified. In this example, it is assumed that no error of 3 bits or more occurs.

(1) S _A = 0, S _B = 0, S _C = 0 In this case, the syndromes S _A and S _B are “0” and the syndrome S _C is “0”. 2
As shown in A, no error has occurred in both the area AR1 and the area AR2.

(2) S _A = 0, S _B = 0, S _C = 1 In this case, since the syndromes S _A and S _B are “0”, as shown in FIG. Also, no error has occurred in the area AR2. In this case, since the syndrome S _C is "1", as shown in FIG. 2B, but there may be an error in the ECC code,
There is no problem with the data.

(3) S _A = 0, S _B ≠ 0, S _C = 0 In this case, since the syndrome S _A is “0”,
No error has occurred in the area AR1. Since the syndrome S _B is not "0", an error occurs in the area AR2. Since the syndrome S _C is “0”, the number of errors is “2” (the number of errors is an even number, but here, the number of errors is “2” since the number of errors is 3 or less).
Individual). Therefore, as shown in FIG.
When two errors occur in R2 (Case 1)
And one error has occurred in the area AR2, and the ECC
It is considered that an error occurs in the code E _C (case 2). In case 2, since there is one error, the error can be corrected, but either case 1 or case 2 cannot be determined. Therefore, in this case, it cannot be corrected.

(4) S _A = 0, S _B ≠ 0, S _C = 1 In this case, since the syndrome S _A is “0”,
No error has occurred in the area AR1. Since the syndrome S _B is not "0", an error occurs in the area AR2. Since the syndrome S _C is “1”, the number of errors is “1” (the number of errors is an odd number,
Here, since the number of errors is less than “3”, it is “1”.) Therefore, as shown in FIG. 2D,
It can be determined that one error has occurred in the area AR2. In this case, since there is one error in the area AR2, it can be corrected.

(5) S _A ≠ 0, S _B = 0, S _C = 0 In this case, since the syndrome S _B is “0”,
No error has occurred in the area AR2. Since the syndrome S _A is not “0”, an error has occurred in the area AR1. Since the syndrome S _C is "0", the number of errors is "2" number. Accordingly, as shown in FIG. 2E, a case (case 1) that occurred two errors in the area AR1, have one error in the area AR1 is generated, an error occurs in the ECC code E _C (Case 2). In case 2, since there is one error, the error can be corrected, but either case 1 or case 2 cannot be determined. Therefore, in this case, it cannot be corrected.

(6) S _A ≠ 0, S _B = 0, S _C = 1 In this case, since the syndrome S _B is “0”,
No error has occurred in the area AR2. Since the syndrome S _A is not “0”, an error has occurred in the area AR1. Since the syndrome S _C is "1", the number of errors is "1" number. Therefore, as shown in FIG. 2F, it can be determined that one error has occurred in the area AR1. In this case, since there is one error in the area AR1, the error can be corrected.

(7) S _A ≠ 0, S _B ≠ 0, S _C = 0 In this case, the syndrome S _A is not “0” and the syndrome S _B is not “0”.
An error has occurred in both R2. Syndrome S
_{Since C} is “0”, the number of errors is “2”. Therefore, as shown in FIG.
Errors have occurred, and it can be determined that one error has occurred in the area AR2. In this case, since there is one error in the area AR1 and one error in the area AR2, both can be corrected.

(8) S _A ≠ 0, S _B ≠ 0, S _C = 1 In this case, the syndrome S _A is not “0” and the syndrome S _B is not “0”.
An error has occurred in both R2. Syndrome S
_{Since C} is “1”, the number of errors is an odd number. However, if an error occurs in both the area AR1 and the area AR2, the number of errors is two or more and three bits or more. Is assumed not to occur, and if the number of errors is three, it is inconsistent with the premise. Therefore, this cannot happen.

[0051] Thus, the syndrome S obtained by the reproduction data of the area AR1 and the reproduction ECC code E _A
And _A, the reproduced data and the syndrome S _B obtained by the reproduction CC code E _B area AR2, when using the syndrome S _C obtained by the reproduction ECC code E _C and data of all areas, to the region AR1 and the region AR2 If an error occurs one by one (in the case of (7)), a two-bit error occurs in one page, but correction is possible.

FIG. 3 shows an embodiment of the present invention. In this example, as described above, one page of 512 bytes is divided into an area smaller than 256 bytes and an area larger than 256 bytes, and an ECC code based on a Hamming code is added to each area, and the entire area is ECC is performed by adding an ECC code to which modulo 2 has been added.

In FIG. 3, memory cell array 1 includes cascade-connected memory cell transistors MT0 and MT
Memory cell transistors M cascaded with 1,...
, And a select-type gate transistor SG1 connected to the drain side of T0, MT1,..., And a select-type transistor SG2 connected to the source side of the cascade-connected memory cell transistors. .

The drain of the select gate transistor SG1 is connected to the bit lines BL0, BL1, BL in the data area.
2,... And bit lines BLS0, BL in the spare area
Are connected to S1,. Select gate transistor SG
2 are connected to the source line Vs.

Memory cell transistors MT arranged in the row direction
The gates of 0, MT1,... Are connected to the word lines WL0, WL
1, ... are connected in common. Select gate transistor S
G1 is connected to the control signal line DSG, and the select gate transistor SG2 is connected to the control signal line SSG.

A page is formed by the memory cell transistors connected to the same word lines WL0, WL1,. The word lines WL0, WL1,... And the control signal lines DSG and SSG of the selection gate are connected to a decoder (not shown), and data is read / written in page units.

Bit lines BL0, BL1, BL2,...
The latch circuits L0, BLS0, BLS1,.
, LS0, LS1,... Are provided. The latch circuits L0, L1, L2,... Are connected to the I / O bus 2. Bit lines BLS0, BLS1, ...
Is connected to the bus 3.

In this example, one page consists of, for example, a data area of 512 bytes and a spare area of 16 bytes. The latch circuits L0, L1, L2,... Are latch circuits for the data area, and the latch circuits LS0, LS
1,... Are latch circuits for the spare area.

As shown in FIG. 1, one page data of 512 bytes is divided into an area AR1 of 192 bytes and an area AR2 of 320 bytes. Then, the area AR1
11 bit ECC code E _A by Hamming code
There is produced, the ECC code E _B of 12 bits by Hamming code from the area AR2 is generated. Further, the ECC code E _C is obtained by adding modulo 2 to the entire data of one page of 512 bytes. These ECC codes E _A , E _B , and E _C are stored in a spare area.

In this example, the ECC operation circuit 11 and the EC
A C operation circuit 12 and an ECC operation circuit 13 are provided;
The ECC operation circuit 11 performs an ECC operation on a 192 byte area AR1. ECC operation circuit 1
No. 2 performs ECC calculation on the 320-byte area AR2. The ECC operation circuit 13 performs modulo 2 addition for all areas.

A transfer gate 13 is provided before the ECC operation circuit 11. The ECC operation circuit 12
Is provided with a transfer gate 14 at the preceding stage. The transfer gate 13 gates 192 bytes of data in the area AR1. Transfer gate 14
Is to gate the data of the area AR2 of 320 bytes.

NAND gate G1, NAND gate G
2. The inverter IV1 and the inverter IV2 constitute a decoder for detecting whether the column address has reached "191" and controlling the transfer gates 13 and 14. The column addresses A6 and A7 are supplied to the NAND gate G2, and the inverter IV1 receives the column addresses A6 and A7.
The column address A8 is supplied. NAND gate G2
Is supplied to the NAND gate G1. The output of inverter IV1 is supplied to NAND gate G1. NA
The output CNT1 of the ND gate G1 is at a low level when the column address is "0" to "191". When the column address becomes “192”, the output CN of the NAND gate G1 continues until the column address becomes “511”.
T1 becomes high level.

When the column address is "0" to "191", the transfer gate 13 is opened by the output CNT1 of the NAND gate G1, and the data via the IO bus 2 is supplied to the ECC operation circuit 11. At this time,
The transfer gate 14 is closed and the ECC operation circuit 1
2, no data is supplied.

The column address is "192" to "511"
In this case, the transfer gate 14 is opened by the output CNT1 of the NAND gate G1, and the data via the IO bus 2 is supplied to the ECC operation circuit 12. At this time, the transfer gate 13 is closed, and no data is supplied to the ECC operation circuit 11.

As described above, the ECC operation circuit 11
The data in the area AR1 is supplied from the O bus 2 via the transfer gate 13. The ECC operation circuit 12 is supplied with data in the area AR2 from the IO bus 2 via the transfer gate 14. The ECC operation circuit 13 is supplied with data of the entire area AR1 and area AR2 from the IO bus 2.

The latch circuits LS0, LS1,... Receive the ECC code of the spare area. Playback E
The CC code E _A is supplied to the ECC operation circuit 11 via the bus 3. Play ECC code E _B via the data bus 3 is supplied to the ECC arithmetic circuit 12. The reproduced ECC code E _C is transmitted via the data bus 3
It is supplied to the ECC operation circuit 13.

The reproduced data in the area AR1 having the column address of “0” to “191” is calculated by the ECC operation circuit 11,
The syndrome S _A is obtained from the reproduced ECC code E _A. By the ECC operation circuit 12, the reproduction data of the area AR2 having the column address of “192” to “511”,
From the reproduced ECC code E _B , the sync dome S _B is obtained. The ECC calculation circuit 13, a reproduction data area AR1 and the region AR2, and a playback code E _C, the syndrome S _C is obtained.

Outputs of the ECC operation circuits 11, 12, and 13 are supplied to latch circuits 21, 22, and 23, respectively. 512
When the transfer of the data of one page of the byte is completed, the syndromes S _A , S _B , and S _C are latched by the latch circuits 21, 22, and 23.

The NAND gates G11, G12, G13,
The NOR gate G14 and the inverter IV11 detect whether or not the column address has reached the last "511" of one page, and when the column address has reached "511", the latch circuits 21, 22, and 23 perform the ECC operation. Circuits 11, 1
It operates as a decoder that controls so as to take in outputs 2 and 13.

The column addresses A6, A7, A8 are supplied to the NAND gate G11. NAND gate G1
2 is supplied with column addresses A3, A4 and A5. The NAND gate G13 has a column address A0,
A1 and A2 are supplied. NAND gates G11, G1
2. The output of G13 is supplied to NOR gate G14.
The output of the NOR gate G14 is supplied to the latch circuits 21 to 23 via the inverter IV11.

When the column address is other than "511", the output CNT2 of the inverter IV11 is at the high level. When the column address becomes “511”, the output CNT2 of the inverter IV11 becomes low level and the ECC
The outputs of the arithmetic circuits 11, 12, and 13 are output from the latch circuits 21, 2,
2, 23.

The outputs of the latch circuits 21, 22, and 23 are supplied to the decision circuit 31. The determination circuit 31 determines an error state based on the syndrome S _A from the ECC operation circuit 11, the syndrome S _B from the ECC operation circuit 12, and the syndrome S _C from the ECC operation circuit 13. It is to make corrections. The method of determining the error state and the method of correcting the error are described in the above (1) to (1).
This is as shown in (8).

FIG. 4 shows a time chart of the configuration shown in FIG. As shown in FIG. 4B, before a column address for serially transferring data is input, the control signals XLDA, XLDB, and XLDC go low, and the ECC operation circuit 11, the ECC operation circuit 12,
Reproduction ECC codes E _A , E _B , and E _C are taken into the ECC operation circuit 13 via the bus 3, respectively.

When the column address is "0" to "191", the control signal CNT1 goes low as shown in FIG. 4C, and the ECC operation circuit 11 takes in the reproduced data of the area AR1. ECC arithmetic circuit 11, the reproduction data in this area AR1, performs syndrome calculation from the reproduction ECC code E _A, calculates the syndrome S _A.

The column address is "192" to "511"
4C, the control signal CNT1 goes high, and the ECC operation circuit 12
Playback data is captured. The ECC operation circuit 12
The reproduction data of this area AR2 and the reproduction ECC code E _B
Performing syndrome calculation and a, and calculates the syndrome S _B.

[0076] In the ECC arithmetic circuit 13 performs during the address "0" to "511", and the reproduced data, the addition modulo 2 from the reproduction ECC code E _C, calculates a syndrome S _C.

When the column address becomes "511", as shown in FIG. 4D, the control signal CNT2 goes low, and the syndromes S _A , S _B , and S _C from the ECC arithmetic circuits 11, 12, and 13 are latched by the latch circuit 21. , 22, and 23 respectively.

As described above, according to the present invention, one page of data of 512 bytes is stored in the areas AR1 and AR3 of 192 bytes.
Divided into a 20-byte area AR2, generates additional ECC codes E _A Hamming code for the region AR1, and generates additional ECC codes E _B Hamming code for area AR2, relative to the total area , And modulo 2, the ECC code E _C is generated and added. As a result, when a one-bit error exists in the area AR1 and a one-bit error exists in the area AR2, it becomes possible to correct the error.

In this case, one page of data of 512 bytes is divided into an area AR1 of 192 bytes and an area AR2 of 320 bytes. The method of dividing one page is not limited to this.

In the above-described example, the ECC code is arranged in the spare area. However, the ECC code may be arranged in the data area.

[0081]

According to the present invention, one page of data is divided into two areas, and each area is provided with a Hamming code E.
In addition to generating and adding a CC code, an ECC code is generated and added by adding modulo 2 to the entire area.
Thus, error data can be corrected only when an error of one bit occurs in each area. In this case, if the data of one page is divided into an area smaller than half the number of data of one page and an area larger than half the number of data of one page, the number of bits allocated to the ECC code does not increase.

[Brief description of the drawings]

FIG. 1 is a schematic diagram used for describing a page of a flash memory to which the present invention is applied.

FIG. 2 is a schematic diagram used for describing an embodiment of the present invention.

FIG. 3 is a schematic diagram used for describing an embodiment of the present invention.

FIG. 4 is a timing chart used to describe an embodiment of the present invention.

FIG. 5 is a schematic diagram used to describe a page of a conventional flash memory.

FIG. 6 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 7 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 8 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 9 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 10 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 11 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 12 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 13 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 14 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 15 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 16 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 17 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 18 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 19 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 20 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

FIG. 21 is a schematic diagram used for explaining an ECC operation of a conventional flash memory.

[Explanation of symbols]

11, 12, 13 ... ECC operation circuit, 31 ... judgment circuit

Claims (8)

[Claims] 1. An error correction method in a semiconductor memory device in which memory cells arranged in a row direction are connected to a common word line and writing / reading is performed in page units composed of the memory cells connected to the common word line. At the time of recording, the data area of one page is divided into a first area and a second area, a first error correction code is generated and added by the first area, and a second error correction code is generated by the second area. An error correction code is generated and added, and further a third error correction code is generated and added by the entire area of the one page, and at the time of reading, the data read from the first area and the first area , The syndrome of the first area is obtained from the reproduced data of the first error correction code generated and added, and the data read from the second area and the second area are obtained. , The syndrome of the second area is obtained from the reproduction data of the second error correction code generated and added to the reproduction data, and the reproduction data read from the entire area of the one page and the reproduction error of the third error correction code are obtained. Judging the number of errors from the reproduction data; judging the error state in the first area and the second area based on the first syndrome and the second syndrome and the number of the errors; An error correction encoding method in a semiconductor memory device that performs a correction process. 2. The semiconductor memory according to claim 1, wherein the first error correction code generated and added to the first area and the second error correction code generated and added to the second area are Hamming codes. Error correction encoding method in the device. 3. The semiconductor memory device according to claim 1, wherein the third error correction code for generating and adding the third error correction code by the entire area of one page is obtained by adding modulo 2 to all data. Error correction coding method in. 4. The method according to claim 1, wherein the size of the first area is different from the size of the second area. 5. A semiconductor memory device in which memory cells arranged in a row direction are connected to a common word line and writing / reading is performed on a page basis consisting of memory cells connected to the common word line. Means for dividing a data area of one page into a first area and a second area, generating and adding a first error correction code by the first area, and a second error correction code by the second area Means for generating and adding a third error correction code using the entire area of the one page; and, when reading, the data read from the first area and the first area. Means for obtaining a syndrome in the first area from the reproduction data of the first error correction code generated and added to the data read from the second area; Means for obtaining a syndrome in the second area from the added reproduced data of the second error correction code; and further, reproduced data read from the entire area of the one page and reproduced data of the third error correction code. Means for determining the number of errors; determining the error state in the first area and the second area based on the first syndrome and the second syndrome and the number of errors; And a means for performing error correction processing. 6. The semiconductor memory according to claim 5, wherein the first error correction code generated and added to the first area and the second error correction code generated and added to the second area are Hamming codes. apparatus. 7. The semiconductor memory device according to claim 5, wherein the third error correction code for generating and adding the third error correction code by the entire area of one page is obtained by adding modulo 2 to all data. . 8. The semiconductor memory device according to claim 5, wherein a size of said first region is different from a size of said second region.