TW202038248A - Memory with error correction circuit - Google Patents

Abstract

A memory with an error correction circuit, including: a first error correction circuit performs error correction on the first portion of data to generate a first partial write data or a first partial read data; a second error correction circuit performs error correction on the second portion of data to generate a second portion of the data or a second portion of the data; in the write mode, the plurality of sensing drive circuits respectively receives a plurality of first partial write bytes of the first partial write data, and a plurality of second partial write bytes of the second partial write data, and each sensing drive circuit combines the corresponding first partial write byte and the second partial write byte to write in a corresponding memory cell row; in the read mode, the plurality of sensing driving circuits respectively sense the stored data of the plurality of memory cells to generate the plurality of first partial read data and the second partial read data.

Description

Memory with error correction circuit

The invention relates to a memory circuit, and more particularly to a memory with an error correction circuit.

Error-correcting code (ECC) circuits are integrated on a dynamic random access memory (Dynamic Random Access Memory, DRAM) chip. Since the error correction coding circuit with the two-bit error correction capability requires a larger circuit area and a longer error correction time, most of the error correction coding circuits with a single-bit error correction capability are used.

Please refer to FIG. 1, the memory 100 includes a first error correction circuit ECC1, a second error correction circuit ECC2, a plurality of memory cell rows MCC, and a plurality of sensing driving circuits SD. Among them, the first error correction circuit ECC1 and the second error correction circuit ECC2 both have a single-bit error correction capability. Each memory cell row MCC includes multiple memory cell blocks MC connected in series, and each memory cell block MC includes multiple memory cells (not shown). The plurality of sensing driving circuits SD are respectively coupled to the plurality of memory cell rows MCC, and each sensing driving circuit SD is coupled to the first error correction circuit ECC1 or the second error correction circuit ECC2. Taking FIG. 1 as an example, a plurality of sensing driving circuits SD located on the left half of the memory 100 are coupled to the first error correction circuit ECC1, and a plurality of sensing driving circuits SD located on the right half of the memory 100 are coupled to the first Two error correction circuit ECC2.

When adjacent memory cells fail together, the adjacent memory cells that have failed are coupled to the same error correction circuit, which will make the error correction circuit (for example, the first error correction circuit 110) unable to correctly correct multiple bits. error. In order to avoid the aforementioned problems, in the prior art, those skilled in the art often use spare memory for error correction circuits, which leads to larger circuit area and increased manufacturing costs.

In view of the above-mentioned problems, the present invention proposes a memory with an error correction circuit to cope with the two-bit error condition caused by the failure of adjacent memory cells.

The invention provides a memory with an error correction circuit, which includes a first error correction circuit, a second error correction circuit, a plurality of memory cell rows and a plurality of sensing driving circuits. Wherein, the first error correction circuit performs error correction for the first part of data to generate a first part of written data or a first part of read data. The second error correction circuit performs error correction on the second part of the data to generate the second part of the written data or the second part of the read data. The plurality of sensing driving circuits are respectively coupled to the plurality of memory cell rows, and are coupled to the first error correction circuit and the second error correction circuit. In the writing mode, the plurality of sensing driving circuits respectively receive a plurality of first partial writing bits of the first partial writing data, and respectively receiving a plurality of second partial writing bits of the second partial writing data. Each sensing and driving circuit combines the corresponding first part of the write bit and the second part of the write bit to write the corresponding memory cell row. In the read mode, a plurality of sensing drive circuits respectively sense the stored data of a plurality of memory cell rows to generate the plurality of first partial read data and the aforementioned second partial read data.

Based on the above, two adjacent memory cells are respectively coupled to the first error correction circuit and the second error correction circuit. When the aforementioned two adjacent memory cells fail to cause a read error, there will only be one read error for the first error correction circuit, and similarly, for the second error correction circuit, there will only be one read error. The error is read, so that the first error correction circuit and the second error correction circuit can deal with single-bit errors and perform error correction.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Referring to FIG. 2, the memory 200 includes a first error correction circuit ECC1, a second error correction circuit ECC2, a plurality of sensing drive circuits SD, an address decoder ADD, and a memory cell array, wherein the memory cell array consists of a plurality of memory cells The row MCC is composed of a plurality of memory cell rows MCR. Each memory cell row MCC includes a plurality of memory cell blocks MC connected in series, and each memory cell block MC includes a plurality of memory cells M (as shown in FIG. 3). A plurality of memory cell rows MCC are respectively coupled to a plurality of sensing driving circuits SD via an address decoder ADD, and each sensing driving circuit SD is simultaneously coupled to the first error correction circuit ECC1 and the second error correction circuit ECC2. Among them, the first error correction circuit ECC1 and the second error correction circuit ECC2 can correct single-bit errors. The address decoder ADD may include a row decoder (not shown) and a column decoder (not shown).

The memory 200 can allow data D of a specific size to be read or written. In the writing mode of the memory, the data D is split into a first part of data D1 and a second part of data D2. The first error correction circuit ECC1 generates the first part of the written data ECCD1 including the first error correction code according to the first part of the data D1; similarly, the second error correction circuit ECC2 generates the first part of the write data including the second error correction code according to the second part of the data D2. The second part is written into ECCD2. In this embodiment, the size of the data D can be, for example, 256 bits, the size of the first part of the data D1 and the second part of the data D2 is 128 bits, and the first part of the written data ECCD1 and the second part of the written data ECCD2 The size is 136 bits, including 8-bit first error correction code and second error correction code.

Then, the first part of writing data ECCD1 can be divided into a plurality of first part writing bits DB1 (for example, 4 bits in size), and the second part of writing data ECCD2 can be divided into multiple second part writing bits DB2. Each sensing drive circuit SD simultaneously receives the first part of the write bit DB1 and the second part of the write bit DB2, and combines the first part of the write bit DB1 and the second part of the write bit DB2, and then decodes the address The ADD performs address designation and writes the designated address of the corresponding memory cell row MCC.

Taking the sensing driving circuit SD1 as an example, the sensing driving circuit SD1 receives the first part of the write bit DB1 and the second part of the write bit DB2, and the first part of the write bit DB1 and the second part of the write bit DB2 After the combination, the corresponding designated address of MCC1 is written, and this address is designated by the address decoder ADD, for example, the memory cell block MC in the first column of the memory cell row MCC(1) shown in FIG. 3.

Please continue to refer to FIG. 2. In this embodiment, the first error correction code (for example, 8 bits) generated by the first error correction circuit ECC1 and included in the first part of the write data ECCD1 is also divided into two first parts The written bit DB1 (for example, 4 bits) is received by the sensing driving circuit SD (P) and the sensing driving circuit SD (P+1) respectively. Similarly, the second error correction code (for example, 8 bits) generated by the second error correction circuit ECC2 and included in the second part of the write data ECCD2 is divided into two second parts for the write bit DB2 (for example, 4 Bit) and are respectively received by the sensing drive circuit SD(P) and the sensing drive circuit SD(P+1). In other words, the sensing drive circuit SD(P) (referred to as the first error correction code memory cell row) respectively receives part of the first error correction code and part of the second error correction code, and the sensing drive circuit SD(P+ 1) The same (called the second error correction code memory cell line). Then, similarly, the sensing drive circuit SD(P) combines part of the first error correction code with part of the second error correction code and writes the specified address in the corresponding memory cell row MCC(P) to sense The same is true for the drive circuit SD (P+1).

In this embodiment, there are a total of N rows of memory cell rows MCC, wherein the first error correction code memory cell row and the second error correction code memory cell row are respectively located in the Pth row and the P+1th row, and are arranged adjacently (As shown in Figure 2), where P and N are both natural numbers, and 1<P<N. In another embodiment, the first error correction code memory cell row and the second error correction code memory cell row are located at the center of the plurality of memory cell rows MCC. For the convenience of description, the multiple memory cell rows on the left side of the first error correction code memory cell row in the figure are called the first data code memory cell row, and the multiple memory cell rows on the right side of the second error correction code memory cell row in the figure The memory cell line is called the second data code memory cell line.

In the read mode of the memory 200, each sensing drive circuit SD senses and reads data bytes from the designated address (designated by the address decoder ADD) of the corresponding memory cell row MCC, and divides it into the first part The read bit and the second part of the read bit; for the convenience of description, the first part of the read bit and the second part of the read bit are also denoted as DB1 and DB2. Then, the sensing drive circuit SD sends the first part of the read bit DB1 and the second part of the read bit DB2 to the first error correction circuit ECC1 and the second error correction circuit ECC2 for error correction, respectively. Please refer to FIG. 2, a plurality of first part reading bits DB1 are combined to form the first part reading data (including the first error correction code), which is received by the first error correction circuit ECC1; similarly, multiple second part readings The output bit DB2 is combined to form the second part of the read data (including the second error correction code), which is received by the second error correction circuit ECC2.

For the convenience of description, the first part of the read data and the second part of the read data are also denoted as ECCD1 and ECCD2. Then, the first error correction circuit ECC1 performs error correction on the first part of the read data ECCD1 according to the first error correction code in the first part of the read data ECCD1 to generate the first part of the data D1; similarly, the second error correction circuit ECC2 is based on The second part reads the second error correction code in the data ECCD2, performs error correction on the second part read data ECCD2, and generates the second part data D2. Finally, the first part of data D1 and the second part of data D2 are combined and output as data D. In this embodiment, the sizes of the plurality of first part readout bits DB1 and the plurality of second part readout bits DB2 are all 4 bits, and the sizes of the first part readout data and the second part readout data are both 136 bits, and the size of the first error correction code and the second error correction code can both be 8 bits, and finally, the size of the data D is 256 bits.

The following will use FIG. 3 to illustrate the details of each sensing drive circuit SD writing data bytes into the specified address of the corresponding memory cell row MCC, and reading data from the specified address of the corresponding memory cell row MCC The details of the byte. Each memory cell block MC includes a plurality of first memory cell M1, second memory cell M2, sub word line driver SWD, first bit line sensor BLSA1, second bit line sensor BLSA2, and first selection The switch SW1, and the second selection switch SW2. In FIG. 2, only the bit line sensor BLSA is generally called the first bit line sensor BLSA1 and the second bit line sensor BLSA2. In FIG. 3, each first memory cell M1 and each second memory cell M2 includes a transistor T and a capacitor C, wherein the capacitor C is coupled between the transistor T and the reference potential terminal. The control terminal of the transistor T is coupled to the sub word line driver SWD via the word line WL, and is controlled by the sub word line driver SWD. The transistor T is connected in series between the capacitor C and the corresponding bit line. Transistor T (transistor in the first memory cell M1) is coupled to the first bit line sensor BLSA1, or (transistor in the second memory cell M2) is coupled to the second bit line sensor Detector BLSA2. The first bit line sensor BLSA1 senses the stored data of the first memory cell M1 via the first bit line BL1, and the second bit line sensor BLSA2 senses the second memory cell M2 via the second bit line BL2 Of stored data. The first bit line sensor BLSA1 is coupled to the main input/output line MIO via the column switch RSW. Similarly, the second bit line sensor BLSA2 is coupled to the main input/output line MIO via the column switch RSW. For the convenience of description, the bit line BL connected to the first memory cell M1 is referred to as the first bit line BL1, and the bit line BL connected to the second memory cell M2 is referred to as the second bit line BL2. In this embodiment, the transistor T can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and the memory cells M located in the same memory cell row MCR can consist of the same character. Line WL control.

2 and 3 at the same time, in the write mode of the memory 200, it is assumed that the write address specified by the address decoder ADD corresponds to the memory cell block in the first row of the memory cell row MCC(1) ( Marked as MC(11)), then the sensing driver SD(1) turns on the transistors T of all the memory cells M of the memory cell block MC(11) through the sub-line driver SWD. In addition, the sensing driver SD(1) controls the column switch RSW to turn on, and controls the row selection line CSL0 to send a selection signal S to turn on the first selection switch SW1 and the second selection switch SW2 of the memory cell block MC(11), so that The main input and output line MIO is connected to the memory cell block MC(11). Among them, the plurality of first bit line sensors BLSA1 are connected to the plurality of first memory cells M1 via the plurality of first bit lines BL1, and the plurality of second bit line sensors BLSA2 are connected via the plurality of second bit lines. The line BL2 is connected to a plurality of second memory cells M2. Then, the sensing drive circuit SD(1) combines the combined first part of the write bit DB1 and the second part of the write bit DB2, respectively through the first bit line sensor BLSA1 and the second bit line sensor BLSA1 and the second bit line sensor via the main input and output line MIO The binary line sensor BLSA2 writes to a plurality of memory cells M of the memory cell block MC(11).

For the convenience of description, the first bit line BL1 coupled to the turned-on first selection switch SW1 is referred to as the first selected bit line; similarly, the second bit line BL2 coupled to the turned-on second selection switch SW2 It is called the second selected bit line.

In the read mode of the memory 200, assuming that the read address specified by the address decoder ADD corresponds to the memory cell block MC(11), similarly, the sensor driver SD(1) controls the row switch RSW to turn on. And control the row selection line CSL0 to send the selection signal S to turn on the first selection switch SW1 and the second selection switch SW2 of the memory cell block MC(11), so that the main input and output line MIO and the memory cell block MC(11) The first bit line sensor BLSA1 and the second bit line sensor BLSA2 are connected. The plurality of first bit line sensors BLSA1 are connected to the plurality of first memory cells M1 via the plurality of first bit lines BL1, and the plurality of second bit line sensors BLSA2 are via the plurality of second bit lines. BL2 is connected with a plurality of second memory cells M2. Then, the sensing driving circuit SD(1) senses the stored data from the first memory cell M1 of the memory cell block MC(11), and passes the stored data through the first bit line sensor BLSA1 and the main input/output line MIO is sent to the first error correction circuit ECC1. The sensing driving circuit SD(1) senses the stored data from the second memory cell M2 of the memory cell block MC(11), and passes the stored data through the second bit line sensor BLSA2 and the main input/output line MIO, It is sent to the second error correction circuit ECC2. In other words, two adjacent memory cells M in the memory cell block MC correspond to the first error correction circuit ECC1 and the second error correction circuit ECC2, respectively.

When two adjacent memory cells are faulty (for example, the first memory cell M1 and the second memory cell M2 of the memory cell block MC(11) in FIG. 3), which results in storage data errors, the two adjacent memory cells The memory cells M1 and M2 are respectively coupled to the first error correction circuit ECC1 and the second error correction circuit ECC2. Therefore, for the first error correction circuit ECC1, there will only be one read error (for example, the first memory cell M1 Similarly, for the second error correction circuit ECC2, there is only one read error (for example, the read data of the second memory cell M2), and the first error correction circuit ECC1 and the first The two error correction circuit ECC2 can correct single-bit errors. For those skilled in the art, at the same cost, the memory with the error correction circuit of the present invention can obtain a better error correction effect, and can reduce the use of spare memory. In addition, the staggered arrangement of the first memory cell M1 and the second memory cell M2 can reduce mutual electrical interference.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application. [Industrial Utilization]

In the present invention, two adjacent memory cells are respectively coupled to the first error correction circuit and the second error correction circuit. In the case of two adjacent memory cells failing, for the first error correction circuit and the second error correction circuit, only a single bit error needs to be dealt with. Therefore, at the same cost, the memory with the error correction circuit of the present invention can obtain a better error correction effect, and can reduce the use of spare memory.

100: memory 200: memory ADD: address decoder BL: bit line BL1: The first bit line BL2: The second bit line BLSA: bit line sensor BLSA1: The first bit line sensor BLSA2: The second bit line sensor C: Capacitance CSL0, CSL1, CSLN: row selection line D: Information D1: The first part of the information D2: The second part of the information DB1: The first part of write bits or the first part of read bits DB2: The second part of the write bit or the second part of the read bit ECC1: The first error correction circuit ECC2: The second error correction circuit ECCD1: The first part of writing data or the first part of reading data ECCD2: The second part of writing data or the second part of reading data M: memory cell M1: The first memory cell M2: second memory cell MC/MC(11): Memory cell block MCC, MCC(1), MCC(P-1), MCC(P), MCC(P+1), MCC(P+2), MCC(N): memory cell row MCR: memory cell row MIO: main input and output line RSW: column switch SD, SD(1), SD(P-1), SD(P), SD(P+1), SD(P+2), SD(N): sensing drive circuit S: select signal SW1: First selection switch SW2: Second selection switch SWD: Sub word line driver T: Transistor

Figure 1 is a conventional memory with an error correction circuit. FIG. 2 shows a memory with an error correction circuit according to an embodiment of the invention. FIG. 3 is a schematic diagram of the memory cell block in the first column of each memory cell row.

200: memory

D: Information

ADD: address decoder

D1: The first part of the information

BLSA: bit line sensor

D2: The second part of the information

DB1: The first part of write bits or the first part of read bits

DB2: The second part of the write bit or the second part of the read bit

ECC1: The first error correction circuit

ECC2: The second error correction circuit

ECCD1: The first part of writing data or the first part of reading data

ECCD2: The second part of writing data or the second part of reading data

MC: Memory cell block

MCC, MCC(1), MCC(P-1), MCC(P), MCC(P+1), MCC(P+2), MCC(N): memory cell row

MCR: memory cell row

SD, SD(1), SD(P-1), SD(P), SD(P+1), SD(P+2), SD(N): sensing drive circuit

SWD: Sub word line driver

Claims (10)

A memory with error correction circuit, including: A first error correction circuit for performing error correction on a first part of data to generate a first part of written data or a first part of read data; A second error correction circuit for performing error correction on a second part of data to generate a second part of written data or a second part of read data; Multiple memory cell rows; and A plurality of sensing and driving circuits are respectively coupled to the memory cell rows and coupled to the first error correction circuit and the second error correction circuit, Wherein, in a write mode, the sensing drive circuits respectively receive a plurality of first part write bits of the first part of write data, and respectively receive a plurality of second part write bits of the second part of write data Bit-in, each of the sensing and driving circuits combines the corresponding first part of the write bit and the second part of the write bit to write the corresponding memory cell row; and In a read mode, the sensing drive circuits respectively sense the stored data of the memory cell rows to generate the first partial read data and the second partial read data. As for the memory described in claim 1, wherein the memory cell rows include a first error correction code memory cell row and a second error correction code memory cell row, the first error correction code memory cell row and The second error correction code memory cell rows all store a part of a first error correction code in the first part of the written data and a part of a second error correction code in the second part of the written data, and the first The error correction code memory cell rows and the second error correction code memory cell rows are arranged adjacently, wherein the memory cell rows further include a plurality of first data code memory cell rows and a plurality of second data code memory cell rows, the The first data code memory cell rows are arranged adjacently and arranged on a first side of the first error correction code memory cell row, and the second data code memory cells are arranged adjacently and arranged on the second error correction code memory cell row. A second side of the code memory cell row, wherein the first side is opposite to the second side. The memory as described in claim 1, wherein each of the memory cell rows includes a plurality of memory cell blocks coupled in series, and each of the memory cell blocks includes: Multiple memory cells are controlled by a character line; A first bit line sensor coupled to a plurality of first bit lines of a plurality of first memory cells among the memory cells; A plurality of first selection switches, according to a selection signal, so that the plurality of first selected bit lines of the first bit lines are coupled to the corresponding sensing driving circuit; and A second bit line sensor coupled to a plurality of second bit lines of a plurality of second memory cells among the memory cells; and A plurality of second selection switches for coupling a plurality of second selected bit lines among the second bit lines to the corresponding sensing driving circuit according to the selection signal, Wherein, the first memory cells and the second memory cells are arranged alternately. For the memory described in item 3 of the scope of patent application, each of the memory cell blocks further includes: A word line driver is coupled to the word line to generate a word line signal. For example, the memory according to any one of items 1 to 4 of the scope of patent application, wherein the first part of the written data and the second part of the written data have the same number of bits, and the first part of the read data is the same as the second Part of the read data has the same number of bits. Such as the memory described in any one of items 1 to 4 in the scope of patent application, the memory further includes: An address decoding circuit, coupled to the memory cell rows and the sensing driving circuits, the address decoding circuit designating the first partial writing bits and the second partial writing bits in the writing mode The address of the memory cell row corresponding to the element, and the address decoding circuit designates the addresses of the memory cell rows corresponding to the first part of the read data and the second part of the read data in the write mode. The memory as described in item 3 of the scope of patent application, wherein each memory cell includes: A transistor coupled to the first bit line sensor; and A capacitor is coupled between the transistor and a reference potential terminal. The memory according to any one of items 1 to 4 in the scope of patent application, wherein in the read mode, each of the sensing drive circuits senses at least 2 bits of stored data from the corresponding memory cell row. The memory as described in item 8 of the scope of patent application, wherein each of the sensing and driving circuits divides the stored data of at least 2 bits into a first part of at least 1 bit to read data and a second part of at least 1 bit Read the information. In the memory described in item 2 of the scope of patent application, each of the first error correction code and each of the second error correction codes has at least 2 bits.

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