KR102025880B1 - Memory device having error correction function and method of correcting error - Google Patents

Memory device having error correction function and method of correcting error Download PDF

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Publication number
KR102025880B1
KR102025880B1 KR1020150073540A KR20150073540A KR102025880B1 KR 102025880 B1 KR102025880 B1 KR 102025880B1 KR 1020150073540 A KR1020150073540 A KR 1020150073540A KR 20150073540 A KR20150073540 A KR 20150073540A KR 102025880 B1 KR102025880 B1 KR 102025880B1
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South Korea
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error
data
memory
read
row data
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KR1020150073540A
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Korean (ko)
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KR20160139155A (en
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유승주
이태민
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에스케이하이닉스 주식회사
포항공과대학교 산학협력단
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Priority to KR1020150073540A priority Critical patent/KR102025880B1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/024—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/783—Masking faults in memories by using spares or by reconfiguring using programmable devices with refresh of replacement cells, e.g. in DRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G11C29/886—Masking faults in memories by using spares or by reconfiguring with partially good memories combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C2029/1802—Address decoder

Abstract

The present invention provides a memory chip including a plurality of memory banks each comprising a plurality of memory blocks for storing data, and an error detector for detecting an error of data stored in the plurality of memory banks. And a memory controller including an error correction unit correcting an error of the stored data, and when the error detection unit detects an error of the stored data, transmitting the data including the error to the error correction unit. To provide.

Description

Memory device having an error correction function and an error correction method thereof {Memory device having error correction function and method of correcting error}

The present invention relates to a memory device for storing data, and more particularly, to a memory device for detecting and correcting an error of stored data and a method for correcting the error thereof.

In order to correct an error of data in a memory device storing data, a single-error correction and double-error detection (SECDED) method is used. In the SECDED method, matrix multiplication is performed by combining 8 bit parity in addition to a 64-bit data block, and as a result, recovery is possible when one error exists, and when two errors exist, it is detected. There is a number. That is, if one error occurs, normal operation, two restores to a backup point, and if three or more, the memory device will shut down due to malfunction. The SECDED method requires a space used as a parity separately, and performs a matrix operation every time read and write proceeds, thereby increasing the cost.

In order to reduce this cost, if it is left for a long time without SECDED, if there is an error in the data, the error remains uncorrected. Then, when a large number of errors accumulate, the memory device is shut down. Random errors may occur in the memory device due to a mechanism for which the mechanism is not yet identified, and the yield of the memory device is lowered due to the random error. In particular, in a DRAM to which a semiconductor process of 20 [nm] or less is applied, an error of unknown cause frequently occurs due to physical limitations.

As a method for reducing data errors, the patent (Korean Patent Laid-Open Publication No. 1998-0048943) discloses a method for correcting double bit errors. The patent does not use parity, which leads to a complicated calculation process and a long latency.

The present invention provides a memory device for correcting an error of data stored in the memory device and an error correction method thereof.

The present invention to solve the above problems,

A memory chip including a plurality of memory banks each including a plurality of memory blocks for storing data, and an error detector for detecting an error of data stored in the plurality of memory banks; And a memory controller including an error correction unit correcting an error of the stored data, and when the error detection unit detects an error of the stored data, transmitting the data including the error to the error correction unit. To provide.

In order to solve the above problems, the present invention also,

A memory bank in which data is stored, comprising: a data read step of reading specified row data of the memory bank; An error detecting step of detecting an error of the row data; When the error is detected in the error detection step, the row data is transmitted to the outside, and if the error is not detected, a data transmission determination step of not transmitting the row data to the outside provides an error correction method of the memory device.

As described above, according to the present invention, an error occurring in a memory device, for example, a 3D stacked DRAM, which is sensitive to manufacturing costs, may be corrected in an efficient way to reduce the cost while reducing power consumption. That is, the power consumption generated in the process of correcting the data error of the memory device may be reduced, and the error may be corrected without disturbing the read and write operations of the memory device.

Therefore, the overall performance of the memory device is kept stable, and the reliability is improved.

1 is a block diagram illustrating an embodiment of a memory device according to the present invention.
2 is a block diagram illustrating another embodiment of a memory device according to the present invention.
FIG. 3 is a detailed block diagram of an error detector connected to the memory bank shown in FIG. 2.
4 is a detailed block diagram of the memory chip illustrated in FIG. 2.
5 is a block diagram illustrating still another embodiment of a memory device according to the present invention.
6 is a flowchart illustrating an error correction method according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The same reference numerals among the reference numerals shown in each drawing represent the same members.

1 is a block diagram illustrating an embodiment of a memory device according to the present invention. Referring to FIG. 1, the memory device 100 includes a memory chip 105, an error correction unit 130, and a memory controller 140.

The memory chip 105 includes a plurality of memory banks 110 and 120, a global error line GEL, and a global input / output line GIOL.

Since the structures of the plurality of memory banks 110 and 120 are the same, only the first memory bank 110 will be described here for convenience of description. The memory bank 110 includes one memory array 113 and one error detector 115. The memory array 113 is divided into a data storage 112 and a parity storage 111. The data storage 112 is divided into a plurality of memory blocks, and data is stored in the memory blocks. The data storage 112 includes a plurality of word lines (not shown) and a plurality of bit lines (not shown). Memory cells (not shown) are connected to an area where the word lines and the bit lines intersect, and data is stored in the memory cells. The parity storage unit 111 stores parity data including parity bits corresponding to row data among data stored in the data storage unit 112. The parity storage unit is divided into a plurality, and the plurality of parity storage units store parity bits for data stored in each of the plurality of memory blocks. Row data refers to data stored in memory cells connected to the word lines. That is, the row data is output for each word line. For example, if the row data outputted from the data storage unit 112 is 8 bits, the parity bit for the row data may be set to 1 bit. Since the row data corresponds to the word lines, the number of word lines and the number of parity bits of the data storage 112 are set to be the same. Although FIG. 1 illustrates that only two memory banks 111 and 120 are provided in the memory chip 105, the present invention is not limited thereto. That is, the memory chip 105 may have three or more memory banks.

The error detector 115 is disposed in an empty space of the memory bank 110. The error detector 115 checks whether there is an error in the data stored in the data storage 112. That is, the error detector 115 receives the raw data output from the data storage 112, receives the parity bits corresponding to the raw data from the parity storage 111, and receives the raw data and the parity bits. Matrix multiplication checks the row data for errors. For example, when the number of " 1 " and parity bits included in the row data are set to be even, the number of " 1 " is set to be even. The row data output from the data storage 112 is composed of binary data. If the number of included " 1 " and the number of parity bits are even, the number of " 1 " is an even number, and an error has not occurred in the row data. If the number of " 1 " is an odd number, the error has occurred in the row data. It can be judged that.

If an error is detected in the row data, the error detector 115 transmits the row data including the error to the error correction unit 130. If no error is detected in the row data, the error detector 115 does not transmit the row data to the error correction unit 130. The error detector 115 transmits the data including the error to the error corrector 130 through the global error line GEL.

As shown in FIG. 1, the error detector 115 is disposed in an empty space inside the memory bank 110, thereby reducing the area occupied by the error detector 115 in the memory chip 105.

The data storage unit 112 sequentially outputs raw data in response to an output signal of an external device, for example, the command decoder 251 of FIG. 4, and the error detector 115 has an error for the sequentially outputted raw data. Check The data storage 112 exchanges data with the memory controller 140 through a global input / output line GIOL.

When the memory bank 110 is configured of DRAM (Dynamic Random Access Memory), the error detector 115 performs an error detection operation while the refresh of the memory bank 110 is not performed. This error detection operation may be executed between a predetermined time, for example, between the refresh operation and the next refresh operation, or may be executed once every several refresh operations. The time at which the error detection operation is executed may be set at the time of designing the memory device 100 or may be arbitrarily set by the user. However, according to the design of the memory chip 105, the error detector 115 may simultaneously perform an error detection operation while the refresh operation is in progress. In this case, the error detector 115 may receive a part of data output from the memory banks 110 and 120 and check whether there is an error during the refresh operation without specifying addressing of the memory banks 110 and 120. . In addition, the error detector 115 may use data output when the data of the memory banks 110 and 120 is externally read. That is, when reading the data of the memory banks 110 and 120 from the outside, the error detector 115 may receive a part of the data output from the memory banks 110 and 120 and detect whether there is an error of the data.

The error detector 115 uses local I / O lines (not shown) inside the memory bank 110 to detect an error of row data. Therefore, the data is not collided with data written to or read from the memory bank 110. That is, the data input / output into the memory bank 110 is transmitted through the global input / output line GIOL, but the data transmitted from the memory bank 110 to the error detector 115 does not use the global input / output line GIOL. As such, the error detector 115 does not affect the input / output of the data of the memory bank 110, and thus no time for error detection is separately required. Therefore, almost no performance cost is required for error detection. The resulting power consumption is also reduced.

In addition, since the error detector 115 sends the data to the error correction unit 130 only when an error is detected in the data stored in the corresponding memory bank 110, the power power consumption is reduced and the error correction time is also reduced. . Thus, the maintenance cost of the memory device 100 is reduced.

In addition, since the error detection operation may be performed even while data is inputted and outputted to the memory bank 110, the operation of the memory chip 105 is not disturbed, thereby improving the reliability of the memory device 100.

The memory controller 140 controls data input and output to the memory banks 110 and 120.

The memory controller 140 may include a refresh unit (not shown). The refresh unit controls the refresh of the memory banks 110 and 120. The refresh unit executes the refresh at a specific time point, for example, every 64 [ms]. When the refresh signal output from the refresh unit is transmitted to the memory bank 110, memory cells connected to a specific word line of the memory bank 110 are simultaneously refreshed, and word lines refreshed by an internal counter (not shown) are sequentially. To increase one by one. The refresh unit provides a refresh signal to satisfy a specification of 64 [ms], and the memory banks 110 and 120 allow only a portion of the banks to be refreshed each time the refresh signal is received, thereby increasing the refresh period of the memory banks 110 and 120. Has an increasing effect.

The memory device 100 may further include a CPU (not shown). In this case, the memory controller 140 receives the error data transmitted from the error detector 115 and transmits the error data to the CPU. The CPU receives error data transmitted from the memory controller 140, corrects an error included in the error data, and transmits the corrected data to the memory controller 140. The CPU may be configured as another type of controller capable of controlling the memory controller 140.

The memory controller 140 may include an error corrector 130. That is, when there is a data error in the memory banks 110 and 120, the memory controller 140 may perform a function of correcting the error. In this case, the CPU does not need to be provided in the memory device 100, and even if provided, the CPU may perform another control function without performing an error correction function.

2 is a block diagram illustrating another embodiment of a memory device according to the present invention. 2, the memory device 200 includes a memory chip 205, an error correction unit 230, and a memory controller 240.

The memory chip 205 includes a plurality of memory banks 213 and 223, an error detector 207, and a global input / output line GIOL.

Since the structures of the plurality of memory banks 213 and 223 are identical to each other, only the first memory bank 213 will be described herein for convenience of description. The memory bank 213 is divided into a data storage unit 212 and a parity storage unit 211. Data is stored in the data storage unit 212. The data storage unit 212 includes a plurality of word lines (not shown) and a plurality of bit lines (not shown). Memory cells (not shown) are connected to an area where the word lines and the bit lines intersect, and data is stored in the memory cells. The parity storage unit 212 stores parity data including parity bits corresponding to row data among data stored in the data storage unit 212. Row data refers to data stored in memory cells connected to the word lines. That is, the row data is output for each word line. For example, if row data output from the data storage unit 212 is 8 bits, the parity bit for the row data may be set to 1 bit. Since the row data corresponds to the word lines, the number of word lines and the number of parity bits of the data storage unit 212 are set to be the same. Although FIG. 1 illustrates that only two memory banks 213 and 223 are provided in the memory chip 205 for convenience of description, the present invention is not limited thereto. That is, the memory chip 205 may have three or more memory banks.

The error detector 207 is disposed in the empty space between the memory banks 213 and 223. The error detector 207 checks whether there is an error in the data stored in the memory banks 213 and 223. That is, the error detector 207 receives the row data and the parity bits corresponding thereto from the memory banks 213 and 223, and checks whether the row data has an error by performing matrix operation on the row data and the parity bits. . For example, when the number of " 1 " and the parity bits included in the row data are set to be even, the number of " 1 " is included in the row data (composed of binary numbers) output from the memory bank 213. If the number of "1" and the number of parity bits are equal, the number of "1" is an even number, the error does not occur in the row data. If the number of "1" is an odd number, the error has occurred in the row data. You can judge.

If an error is detected in the row data, the error detector 207 transmits the row data including the error to the error correction unit 230. If no error is detected in the row data, the error detector 207 does not transmit the row data to the error correction unit 230.

As illustrated in FIG. 2, the error detector 207 is disposed in the empty space between the memory banks 213 and 223, thereby reducing the area occupied by the error detector 207 in the memory chip 205.

The memory banks 213 and 223 sequentially output row data in response to an output signal of an external device, for example, the command decoder 251 of FIG. 4, and the error detector 207 receives an error for the sequentially output row data. Check for presence. That is, when error detection for the first memory bank 213 is completed, the memory device 200 proceeds to error detection for the next memory bank 223. The memory banks 213 and 223 exchange data with the memory controller 240 through the global input / output line GIOL.

When the memory bank 213 is made of DRAM, the error detector 207 performs an error detection operation while the refresh of the memory bank 213 is not in progress. This error detection operation may be executed between a predetermined time, for example, between the refresh operation and the next refresh operation, or may be executed once every several refresh operations. The time at which the error detection operation is executed may be set at the time of designing the memory device 200 or may be arbitrarily set by the user. However, according to the design of the memory chip 205, the error detector 207 may simultaneously perform an error detection operation while the refresh operation is in progress. In this case, the error detector 207 may check a presence of an error by receiving a part of data output from the memory banks 213 and 223 during the refresh operation without specifying addressing of the memory banks 213 and 223 separately. . Also, the error detector 207 may use data output when the data of the memory banks 213 and 223 are externally read. That is, when reading data of the memory banks 213 and 223 from the outside, the error detector 207 may receive a part of the data output from the memory banks 213 and 223 and detect the presence or absence of an error of the data.

The error detector 207 uses local I / O lines (not shown) inside the memory bank 213 to detect an error of row data. Therefore, the data is not collided with data written to or read from the memory bank 213. That is, the data input / output to the memory bank 213 is transmitted through the global input / output line GIOL, but the data transmitted from the memory bank 213 to the error detector 207 does not use the global input / output line GIOL. As such, since the error detector 207 does not affect the input / output of the data of the memory banks 213 and 223, time for error detection is not separately required. Thus, the performance cost required for error detection is rarely needed.

In addition, since the error detector 207 sends the data to the error correction unit 230 only when an error is detected in the data stored in the corresponding memory bank, the power power consumption is reduced and the error correction time is also reduced. Thus, the maintenance cost of the memory device 200 is reduced.

In addition, since the error detection operation may be performed even while data is input and output to the memory banks 213 and 223, the operation of the memory chip 205 is not disturbed, thereby improving reliability of the memory device 200.

The memory controller 240 controls data input and output to the memory banks 213 and 223.

The memory controller 240 may include a refresh unit (not shown). The refresh unit controls the refresh of the memory banks 213 and 223. The refresh unit executes the refresh at a specific time point, for example, every 64 [ms]. When the refresh signal output from the refresh unit is transmitted to the memory bank, memory cells connected to a specific word line of the memory bank are simultaneously refreshed, and the word lines refreshed by an internal counter (not shown) are sequentially increased one by one. The refresh unit provides a refresh signal to satisfy a specification of 64 [ms], and the memory banks 213 and 223 refresh only a portion of the banks each time the refresh signal is received, thereby increasing the refresh period of the memory banks 213 and 223. Has an increasing effect.

The memory device 200 may further include a CPU (not shown). In this case, the memory controller 240 receives error data transmitted from the error detector 207 and transfers the error data to the CPU. The CPU receives error data transmitted from the memory controller 240, corrects an error included in the error data, and transmits the corrected data to the memory controller 240. The CPU may be configured as another type of controller capable of controlling the memory controller 240.

The memory controller 240 may include an error corrector 230. That is, when there is a data error in the memory banks 213 and 223, the memory controller 240 may perform a function of correcting the error. In this case, the CPU need not be provided in the memory device, and even if provided, the CPU can perform other control functions without performing the error correction function.

3 is a detailed block diagram of the error detector 207 connected to the memory bank 213 shown in FIG. 2. Referring to FIG. 3, the error detector 207 includes an internal counter 311, a first selector 321, a multiplexer 331, a second selector 322, and an error checker 341.

The internal counter 311 counts the number of row addresses selected according to the external signal P1. Specifically, the memory bank 213 outputs the row data according to the designation of the row address output from the row decoder 254 of FIG. 4, and the internal counter 311 up counts one row each time the row data is output. . Then, when all the raw data is output from the memory bank 213, it is initialized to "0". According to the design of the memory devices 100 and 200, the internal counter 311 may be configured to perform a down count.

The first selector 321 inputs the output signal of the internal counter 311 and the column selection signal CS1, and controls the operation of the multiplexer 331 according to the externally input ECC signal ECC. The ECC signal Ecc is activated when the memory controllers 140 and 240 perform SECDED, and accordingly, the SECDED for the memory bank 213 is performed. When the ECC signal ECC is deactivated, an error detection operation on the memory bank 213 is performed. As such, the SECDED and the error detection operation are not simultaneously performed with respect to the memory bank 213.

The multiplexer 331 multiplexes the raw data output from the memory bank 213. That is, the multiplexer 331 outputs raw data input according to the output signal of the first selector 321. The row data includes parity data stored in the memory bank 213.

The second selector 322 inputs data output from the multiplexer 331, and transmits the input row data to the memory controllers 140 and 240 or the error check unit 341 according to the ECC signal ECC.

The error check unit 341 checks whether an error is included in the input row data. If an error is included, the raw data including the error is transmitted to the error correction unit 230.

4 is a detailed block diagram of the memory chip 205 shown in FIG. 2. Referring to FIG. 4, the memory chip 205 includes an error detector 207, a command decoder 251, an address decoder 252, a column decoder 253, a row decoder 254, a memory array 210, and I. / O sense amplifier 255 is provided.

The error detection unit 207 checks whether there is an error of data output from the memory array 210 through the I / O sense amplifier 255, and if there is an error, the error detection unit 207 checks the data including the error in an external device, such as an error correction unit. Output to 230.

The command decoder 251 decodes a command signal input from the outside and outputs a signal for driving the memory array 210. The output signal of the command decoder 251 is transmitted to the address buffer 252.

The address buffer 252 outputs a row address for selecting word lines of the memory array 210 and a column address for selecting bit lines of the memory array 210. The row address is sent to the row decoder 254 and the column address is sent to the column decoder 253.

The command signal may include a refresh control signal for performing a refresh, and the memory array 210 may enter a refresh mode according to the refresh control signal output from the command decoder 251. That is, the address buffer 252 generates an internal address for selecting a page to be refreshed in response to the refresh control signal output from the command decoder 251 and transmits the internal address to the column decoder 253 and the row decoder 254. . The address buffer 252 has a switch (not shown) therein, selectively outputs an external address during a read / write operation, and selectively outputs an internal address when entering a refresh mode.

The column decoder 253 selects one of the memory banks 213 and 223 of FIG. 2 in response to the column address output from the address buffer 252, and bit lines of the selected memory bank. Choose one.

The row decoder 254 selects one of the memory banks included in the memory array 210 in response to the row address output from the address buffer 252, and selects one of the word lines of the selected memory bank.

The memory array 210 includes a plurality of memory banks 213 and 223 of FIG. 2. Data is stored in the memory array 210. Each memory bank receives an address output from the column decoder 253 and the row decoder 254 to store or output data. Since the configuration of the memory array 210 is the same as that shown in FIG. 1 or 2, redundant descriptions thereof will be omitted.

The I / O sense amplifier 255 amplifies the data output from the memory array 210 and outputs it to the outside, or amplifies the data input from the outside and transmits the data to the memory array 210. The I / O sense amplifier 255 may be provided in each of the memory banks in the memory array 210 and may function as a data amplifier for amplifying and outputting the data and the parity bits stored in the memory banks. In this case, the error detector 207 may detect an error through the output data of the data amplifier.

In FIG. 4, the error detector 207 is connected to the I / O sense amplifier 255. However, in order to perform various error detection operations, the error detector 207 may include the I / O sense amplifier 255. The memory array 210 may be connected to the memory array 210 without being connected to the memory array 210. In this case, the error detector 207 operates independently. Accordingly, a row decoder 254 of FIG. 4 is separately provided for the error detector 207 to independently specify the row data of the memory array 210. Accordingly, the error detector 207 performs an error detection operation when external data is stored in the memory array 210 or data is not read out to the outside, or when the refresh operation does not proceed.

5 is a block diagram illustrating still another embodiment of a memory device according to the present invention. Referring to FIG. 5, the memory device 200 includes a memory controller 240 and a memory board 260.

The memory board 260 is equipped with a plurality of memory chips 261 and 263. The structure of the memory chips 261 may employ the structure shown in FIG. 1 or 2. The memory board 260 has a dual in-line memory module (DIMM) structure. Data is stored in the memory chips 261 of the plurality of memory chips 261 and 263, and parity data is stored in the memory chip 263.

The memory controller 240 transmits a command signal CMD, an address signal ADD, and a clock signal CLK to the memory board 260 to control the transfer of data input and output to the memory board 260. Since the operation of the memory controller 240 performs the same operation as that of the memory controller 240 shown in FIGS. 1 and 2, duplicate description thereof will be omitted.

6 is a flowchart illustrating an error correction method according to the present invention. Referring to Figure 6, the error correction method according to the present invention proceeds through the first to sixth steps (611 to 661). An error correction method illustrated in FIG. 6 will be described with reference to FIGS. 1 to 4.

In a first step 611, the memory devices 100 and 200 receive a command instructing to read the raw data from an external device, for example, the command decoder 251. The command includes a row address of data to be read from the memory banks 110, 120, 213, and 223.

In a second step 621, the memory devices 100 and 200 execute a data read step of reading specified row data of the memory banks 110, 120, 213, and 223. In this case, the memory devices 100 and 200 read parity bits corresponding to the row data from the memory banks 110, 120, 213, and 223 together with the row data.

In a third step 631, the error detectors 115, 125, and 207 execute an error detection step of detecting an error of the read row data.

In a fourth step 641, the error detectors 115, 125, and 207 transmit the row data to the error correction units 130 and 230 when an error is detected in the error detection step. A data transmission determination step not transmitted to 130 and 230 is executed. The error detectors 130 and 230 perform matrix operations on the read data and the read parity bits to detect errors.

In a fifth step 651, the memory devices 100 and 200 receive raw data of which the error is corrected from the error correctors 130 and 230.

In a sixth step 661, the memory devices 100 and 200 store the received row data in original memory cells of the memory banks 110, 120, 213, and 223.

In the fourth step 641, if no error is detected, the memory device 100 or 200 reads the next row data of the designated word line (671), and performs the error detection step on the read row data.

As described above, the memory devices 100 and 200 read the row data of the memory banks 110, 120, 213, and 223, and transmit the row data to the error correction units 130 and 230 only when an error is detected from the row data, and the error is detected. If not, the row data is not transmitted to the error correction units 130 and 230. As such, it is possible to prevent the raw data from being unnecessarily transmitted to the error correction units 130 and 230. Therefore, unnecessary power consumption and unnecessary time waste generated in the process of correcting data errors of the memory devices 100 and 200 can be reduced.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (11)

A memory chip comprising a plurality of memory banks each including a plurality of memory blocks for storing data, and an error detector for detecting an error of data stored in the plurality of memory banks, the memory banks and the error detector; Connected via local input / output lines in the memory bank; And
A memory controller including an error correction unit correcting an error of the stored data, the memory banks and the memory controller are connected through a global input / output line, and the error correction unit provided outside the error detector and the memory chip is global. Connected via an error line;
The plurality of memory banks store parity bits corresponding to row data of the stored data.
The error detector in the memory chip,
A far multiplexer that reads row data from the memory bank through the local input / output lines and reads a parity bit corresponding to the read row data when an error of the stored data is detected; And
The read row data and the read parity bits are matrixed to detect an error of the read row data. When an error is detected, the error correcting unit stores the data including the error through the global error line. An error check unit for transmitting to the memory device comprising a. The method of claim 1,
And when the error is not detected from the stored data, the error detector does not transmit the detection result to the memory controller. The method of claim 1,
And the error detector is located between the plurality of memory banks, and connected in parallel with the plurality of memory banks, respectively. The method of claim 1,
And the plurality of memory banks includes a plurality of parity bit storage units for storing the parity bits. The method of claim 1, wherein the error detection unit
And a decoder and an up counter for selecting the plurality of memory blocks. The method of claim 4, wherein
The plurality of memory banks include a data amplifier configured to amplify and output the stored data and the parity bits.
And the error detector detects the error through output data of the data amplifier.
The method of claim 5,
And a plurality of error detection units, wherein the plurality of error detection units are provided in each of the plurality of memory banks to detect an error of data stored in a corresponding memory bank. The memory banks provided in the memory chip and the error detector are connected through local input / output lines, and when the error of data stored in the memory bank is detected in the memory chip, the low data is read from the memory bank through the local input / output lines. A data read step of reading a parity bit corresponding to the read row data;
An error detection step of detecting an error of the read row data by performing matrix operation on the read row data and the read parity bits; And
The error detector in the memory chip and the error corrector provided outside the memory chip are connected through a global error line. When an error is detected in the error detection step, the row data is transmitted through the global error line. And a data transfer determining step of not transmitting the raw data to the error correcting unit if an error is not detected. The method of claim 8,
And receiving the error-corrected data from the outside after the data transmission determination step and storing the error-corrected data as original memory cells of the memory bank. The method of claim 8,
If the error is not detected in the error detecting step, the next row data of the read row data is read, and the error detection step of the read next row data is repeated until the last row data. Error correction method of memory device.
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