TWI812034B - Memory device and operation method thereof - Google Patents

Abstract

An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.

Description

Memory device and method of operating the same

The present invention relates to a memory block, a memory device and an operating method thereof.

In-memory search (IMS) technology is widely used in fields such as artificial intelligence, big data, and IP search. However, the data stored in the memory may contain erroneous bits due to various reasons. When there are bit errors in the stored data, the reliability of the search results will also be affected. Therefore, in order to ensure the reliability of search results, it is necessary to solve the problem of erroneous bits in the data stored in the search array in the memory.

An embodiment of the present invention discloses a memory device, which includes a plurality of memory blocks, a plurality of driving circuits, an error correction circuit and a control circuit. Each memory block includes a plurality of memory units. The driving circuit is coupled to the memory blocks. The error correction circuit is coupled to the memory block. The control circuit is coupled to the driving circuit and the error correction circuit for selecting one of the memory blocks as a target block and performing an error correction operation on the target block. The memory unit of the target block has a plural number of rows and a plural number of columns. The rows include at least one data row and at least one check row. Data row memory The data stored in the unit is user data. The data stored in the memory unit of the check line is the check code. The check code stored in the memory unit of each column is generated based on the user data stored in the memory unit of the same column. The error correction operation involves reading the memory cells of the target block column by column. The data stored in the memory unit of the target block is sent to the error correction circuit. The error correction circuit checks whether there are error bits in the user data stored in the memory units of each column based on the check codes stored in the memory units of each column and performs corrections to generate a code corresponding to the data stored in the memory units of each column. Correct information.

Another embodiment of the present invention discloses an operating method of a memory device, including: selecting one of a plurality of memory blocks as a target block to perform an error correction operation, the target block including a plurality of memory units, The memory units have a plurality of rows and a plurality of columns. The rows include at least one data row and at least one check row. The data stored in the memory unit of the data row is user data, and the data stored in the memory unit of the check row is user data. As a check code, the check code stored in the memory unit of each column is generated based on the user data stored in the memory unit of the same column; the memory units of the columns of the target block are read column by column; the target block is The data stored in the memory units of the rows is sent to an error correction circuit; and the error correction circuit checks whether the user data stored in the memory units of each row contains error bits based on the check codes stored in the memory units of each row. And correction is performed to generate a corrected data corresponding to the data stored in the memory unit of each column.

Another embodiment of the present invention discloses a memory block including a plurality of memory units. The memory cells have a plurality of rows and a plurality of columns. The rows of memory cells are coupled to a first driving circuit through a plurality of first signal lines. The memory cells of these rows For coupling to a second driving circuit through a plurality of second signal lines and to a sensing circuit through a plurality of third signal lines. The memory unit is further coupled to an error correction circuit. The rows include at least one data row and at least one check row. The data stored in the memory unit of the data row is user data. The data stored in the memory unit of the check line is the check code. The check code stored in the memory unit of each column is generated based on the user data stored in the memory unit of the same column.

In order to have a better understanding of the above and other aspects of the present invention, examples are given below and are described in detail with reference to the accompanying drawings:

10:Memory device

102: First drive circuit

104: Second drive circuit

106: Sensing circuit

108-1~108-3: Memory block

110: Error correction circuit

112:Control circuit

SL1~SLm: first signal line

BL1~BLn: second signal line

ML1~MLn: The third signal line

U1-1~Um-n: memory unit

S301~S307, S801~S807: steps

400, 500, 620: Data collection

700: Read column data

710:Logic

720:Correct information

730~760: Check unit

770:Computing unit

Figure 1 illustrates a block diagram of a memory device according to an embodiment of the present invention; Figure 2 illustrates a schematic diagram of a memory block according to an embodiment of the present invention; Figure 3 illustrates a memory device according to an embodiment of the present invention. A flow chart of the operation method of the physical device; Figure 4 shows a schematic diagram of the data collection stored in the memory block; Figures 5A~5D show a schematic diagram of reading the data in the memory block line by line for checking and correction; Figure 6 The figure shows a schematic diagram of programming the correct data set obtained after checking and correction into another memory block; Figure 7 shows a schematic diagram of the operation of the error correction circuit according to an embodiment of the present invention; Figure 8 shows a schematic diagram of the error correction circuit according to the present invention Operational flow of a memory device according to an embodiment.

Please refer to FIG. 1 , which illustrates a block diagram of a memory device according to an embodiment of the present invention. The memory device 10 includes a first driving circuit 102, a second driving circuit 104, a sensing circuit 106, a plurality of memory blocks 108-1~108-2, an error correction circuit 110 and a control Circuit 112. It should be noted that the arrangement of the memory blocks 108-1~108-3 and the position of each circuit block in Figure 1 are arranged for the purpose of clearly showing the connection relationship, and are not intended to limit the present invention, and are not consistent with the actual Configuration may vary. In addition, the present invention does not limit the number of memory blocks.

Each memory block 108-1~108-3 is coupled to the first driving circuit 102 through a plurality of first signal lines, coupled to the second driving circuit 104 through a plurality of second signal lines, and coupled to a plurality of third signal lines. The line is coupled to sensing circuit 106 . In one embodiment, the first signal line is a word line or a search line, the second signal line is a bit line, and the third signal line is a match line. , the first driving circuit 102 may be a word line driving circuit, and the second driving circuit 104 may be a bit line driving circuit.

Please refer to Figure 2 for a schematic diagram of a memory block according to an embodiment of the present invention. Since the memory blocks 108-1~108-3 have similar structures, only the memory block 108-1 is shown in Figure 2. The memory block 108-1 may include a plurality of memory units U1-1~Um-n. The memory units U1-1~Um-n can be resistive storage elements, ferroelectric transistors, floating gate transistors, etc. These memory units U1-1~Um-n form an in-memory search array (IMS array). The memory units U1-1~Um-n are configured as m columns and n rows, where m and n are positive integers. The i-th column memory cell is coupled to the first driving circuit 102 through the first signal line SLi, where i=1, 2, ..., m. The jth row memory unit passes the second letter The signal line BLj is coupled to the second driving circuit 104 and is coupled to the sensing circuit 106 through the third signal line MLj, where j=1, 2, ..., n.

The memory units U1-1~Um-n can be programmed into one of two different states respectively. For floating gate transistors, the state is determined based on the threshold voltage. The two different states are high threshold voltage and low threshold voltage. The low threshold voltage can represent one of 0 and 1, and the high threshold voltage can represent The other of 0 and 1.

In one embodiment, a memory unit is configured with one memory cell. Depending on the state of the memory cell, a memory cell can store data representing 0 or 1. This architecture is called content addressable memory (CAM).

In another embodiment, two memory cells are configured into one memory cell. For example, the memory units U1-1 and U2-1 can be configured as one memory cell, the memory units U1-2 and U2-2 can be configured as another memory cell, and so on. Based on the combination of the states of two memory cells, a memory cell can store data representing 0, 1, or don’t care. This architecture is called ternary content addressable memory (TCAM).

It should be noted that in some embodiments, taking a TCAM that stores feature values of multiple pictures as an example, the data stored in a memory cell may represent one bit in the feature value of a picture, and the data stored in a single memory unit is There is no specific meaning. However, the accuracy of the data is independent of the specific meaning represented by the data. As long as the data stored in the memory units are correct, the data stored in the memory cells composed of memory units will be correct. In other words, the data stored in the memory cells of each column is correct, and the memory cells of each row The data stored in the unit will also be correct. Therefore, the data described in the following article refers to the data stored in the memory unit.

The error correction circuit 110 is coupled to the memory blocks 108-1~108-3. Details of the error correction circuit 110 will be described in detail below.

The control circuit 112 is coupled to the first driving circuit 102, the second driving circuit 104, the sensing circuit 106 and the error correction circuit 110. The control circuit 112 is used to control the operations of the first driving circuit 102, the second driving circuit 104, the sensing circuit 106 and the error correction circuit 110 through signals.

The operations that the memory device 10 can perform include basic operations of CAM and TCAM such as program operations, read operations, erase operations, and search operations. The programming operation and the erasing operation can be realized by the control circuit 112 controlling the first driving circuit 102 and the second driving circuit 104 to respectively apply appropriate bias voltages to the first signal lines SL1 to SLm and the second signal lines BL1 to BLn. The read operation and the search operation can be controlled by the control circuit 112 to control the first driving circuit 102 and the second driving circuit 104 to respectively apply appropriate bias voltages to the first signal lines SL1 ~ SLm and the second signal lines BL1 ~ BLn, and control the sensing circuit. 106 is implemented by detecting the current flowing out of the third signal lines ML1~MLn. During the search operation, the bias voltage applied by the first driving circuit 102 to the first signal lines SL1 ~ SLm represents the data to be searched, and the sensing circuit 106 detects the current flowing out of the third signal lines ML11 ~ MLn. Determine whether any row of memory cells stores data that matches the data being searched. It should be noted that the specific execution methods of the programming operation, reading operation, erasing operation and search operation will depend on the type of the memory device 10 (such as NOR type, NAND type), the type of memory unit (such as resistive storage element, Ferroelectric transistor, floating gate transistor vary according to body type) and other factors. It should be noted that while some memory blocks are performing search operations, other memory blocks may be idle or perform operations other than search operations. The so-called idle state means that the memory block is not undergoing programming operations, reading operations, erasing operations, search operations, and error correction operations as will be described below.

The memory device 10 may further perform error correction operations.

Please refer to FIG. 3 , which illustrates a flow chart of an operating method of a memory device according to an embodiment of the present invention. This process is used to check and correct errors in the data stored in the memory block.

In step S301, the control circuit 112 determines a target block from the memory blocks 108-1~108-3. The control circuit 112 may select an idle state block from the memory blocks 108-1 to 108-3 as the target block. For example, assuming that the memory block 108-2 is performing a search operation and the memory blocks 108-1 and 108-3 are not performing any operations, the control circuit 112 may select the memory block 108-1 as the target block. In one embodiment, the data set stored in the memory block 108-1 is as shown in Figure 4.

Please refer to FIG. 4 , which is a schematic diagram of a data set stored in a memory block according to an embodiment of the present invention. Data set 400 is stored in memory cells of memory block 108-1. For example, the data in the four columns from the top are respectively stored in the four columns of memory cells corresponding to the first signal lines SL1 to SL4 in the memory block 108-1, and the data in the eleven rows from the left are stored in the memory block 108 respectively. In -1, there are eleven rows of memory cells corresponding to the second signal lines BL1~BL11. For example, the data 0011 in the first row from the left is stored in the memory units U1-1~U4-1 corresponding to the first signal line BL1. The memory unit U1-1 stores 0, and the memory unit U2-1 stores 0. , memory unit U3-1 stores 1, memory unit U4-1 stores What is saved is 1. For convenience of explanation, "memory unit corresponding to a specific signal line" will be described as "memory unit on a specific signal line". For example, the memory cells U1-1~U1-n corresponding to the first signal line SL1 will be described as the memory cells U1-1~U1-n on the first signal line SL1; the memory cells U1-1~U1-n corresponding to the second signal line BL1 (or the The memory cells U1-1~Um-1 on the three signal lines ML1) will be described as the memory cells U1-1~U1-n on the second signal line BL1 (or the third signal line ML1). In this embodiment, at least one row of memory cells in the memory block 108-1 is configured as a data row, and at least one row of memory cells is configured as a check row. The data stored in the data row is user data, and the data stored in the check row is check code. User information includes, for example, image feature values and IP addresses. In the data set 400, from the left, the first row is user data 0011, the second row is user data 1110, the third row is user data 1111, the fourth row is check code 1101, and the fifth row is user data 1001, the sixth line is user data 0010, the seventh line is user data 0110, the eighth line is check code 0010, the ninth line is user data 0101, the tenth line is check code 1100, and the eleventh line is Check code 1001, where the bits of the check code are represented by dots. That is to say, in the memory block 108-1, the memory cells on the first signal lines BL1~BL3, BL5~BL7, and BL9 are data rows that store user data, and the first signal lines BL4, BL8, and BL10 are data rows. . The memory unit on BL11 is the inspection line, which stores the inspection code. The data in each column contains check codes generated based on the user data in the same column. For example, in the data in the first row from above, the fourth, eighth, tenth, and eleventh digits are check codes. These check codes are based on the first, second, third, fifth, and fifth digits that also belong to the first row. Generated from six, seven, and nine bits of user data. The algorithm used to generate the check code can be Reed-Solomon code, parity check code, check sum, cyclic redundancy Any well-known and applicable algorithm such as cyclic redundancy code.

In step S303, the control circuit 112 determines whether error checking and correction is triggered. If not, end this process; if yes, execute S303. The control circuit 112 can determine whether to trigger error checking and correction for the target block based on parameters such as the number of reads of the target block, the number of searches, and the duration of the data (the time elapsed since the previous programming). For example, when the number of reads, the number of searches, or the data retention time is greater than a corresponding threshold, the control circuit 112 determines to trigger error checking and correction for the target block.

In step S304, the control circuit 112 instructs the first driving circuit 102 and the second driving circuit 104 to apply a read bias to the target block (memory block 108-1) to read each column in the target block column by column. The data stored in the memory unit is transmitted to the error correction circuit 110.

In step S305, the error correction circuit 110 determines whether the data read from the memory cells of each column contains erroneous bits. If yes, execute S306; if no, end this process.

In S306, the error correction circuit 110 determines whether the error bit can be corrected. If yes, execute S307; if no, end this process. Any error correction code has an error correction rate. When the number of error bits exceeds the upper limit of the number of error bits that can be corrected by the error correction code used, the error bits cannot be corrected even if the existence of the error bits is known.

In S307, the error correction circuit 110 corrects the error bits in the data read from the memory cells of each column and generates (outputs) corrected data.

Please refer to Figures 5A-5D. Figures 5A-5D illustrate a schematic diagram of reading the data of the target block column by column and sending it to the error correction circuit for checking and correction. The data set 500 shown in Figures 5A-5D is formed due to the occurrence of erroneous bits in the data set 400 shown in Figure 4. In this embodiment, there is an error in the data stored in the memory unit U2-3, that is, the data bit 502 in the data set 500 is actually an error bit. The bit in the data set 400 is 1, and in the data set 500 is 0 (error).

In Figure 5A, the first driving circuit 102 applies a read voltage Vread to the first signal line SL1 and applies a pass voltage Vpass to the other first signal lines SL2~SLm to read the memory unit U1- on the first signal line SL1. The data stored in 1~U1-11 is 510, which is 01111000011. The read data is input to the error correction circuit 110 for error checking and correction. After checking, the error correction circuit 110 obtains a check result 530 of 01111000011 with no error bits.

In Figure 5B, the first driving circuit applies the read voltage Vread to the first signal line SL2, and applies the pass voltage Vpass to the other first signal lines SL1, SL3~SLm to read the memory unit U2 on the first signal line SL2. The data stored in -1~U2-11 is 540, which is 01010010110. The read data is input to the error correction circuit 110 for error checking and correction. After checking, the error correction circuit 110 obtains the check result that the third bit from the left in 01010010110 is an error bit. Then, the error correction circuit 106 corrects the error bit from 0 to 1 and outputs correction data 550, that is, 01110010110.

In Figure 5C, the first driving circuit applies the read voltage Vread to the first signal line SL3, and applies the pass voltage Vpass to the other first signal lines SL1~SL2, SL4~SLm to read the memory on the first signal line SL3. The data stored in units U3-1~U3-11 The material is 560, which is 11100111000. The read data is input to the error correction circuit 110 for error checking and correction. After checking, the error correction circuit 110 obtains a check result 570 of 11100111000 with no error bits.

In Figure 5D, the first driving circuit applies the read voltage Vread to the first signal line SL4, and applies the pass voltage Vpass to the other first signal lines SL1~SL3, SL5~SLm to read the memory on the first signal line SL4. The data stored in units U4-1~U4-11 is 580, which is 10111000101. The read data is input to the error correction circuit 110 for error checking and correction. After checking, the error correction circuit 110 obtains a check result 590 that 10111000101 has no error bits.

In one embodiment, after obtaining the check result that there are no error bits, the error correction circuit 110 may output a signal representing "no error" to the control circuit 112 . When the control circuit receives the signal representing "no error", it will not modify the data stored in the memory cells of the column in which no error bits occur in the memory block 108-1. For example, in the examples of Figures 5A to 5D, the control unit 1112 will not modify the data stored in the memory units on the first signal lines SL1, SL3 to SL4. On the other hand, the error correction circuit 110 can output correction data corresponding to the data stored in the memory cell of the column in which the error is detected to the control circuit 112, and the control circuit 112 can program the first signal line on which the error bit occurs according to the correction data. memory unit to change incorrect data into correct data. Taking the example of Figures 5A to 5D as an example, after the operation of Figure 5B is performed, the error correction circuit 110 outputs the correction data 550, that is, 01110010110, to the control circuit 112. The control circuit 112 instructs the first driving circuit according to the correction data 550. 102 and the second driving circuit 104 pair the first signal line SL1~SLm and the second signal lines BL1~BLn respectively apply programming bias voltages to program the memory cells U2-1~U2-n, thereby changing the data stored in the memory unit U2-3 from 0 to 1.

In another embodiment, after obtaining the check result that no error bits are found, the error correction circuit 110 may output the data with no errors found after the check as corrected data (the same as the read data). For example, in the examples of Figures 5A, 5C, and 5D, the error correction circuit 110 finds no errors after checking the read data 510, 560, and 580. The error correction circuit 110 will regard the data without errors after checking as Correction data 530, 570, and 590 (same as the read data 510, 560, and 580) are output. The control circuit 112 can receive the correction data output by the error correction circuit 110 (including the correction data 530, 570, 590 of data with no errors detected and the correction data 550 obtained after correction), and instruct the first drive circuit 102 and the second drive Circuit 104 applies a programming bias to another memory block to program the correction data into another memory block. For example, since the memory block 10-2 is performing a search operation and the memory block 108-1 is performing an error correction operation, the control circuit 112 can program the correction data obtained by performing the error correction operation of the memory block 108-1 into the memory block. 108-3. As shown in Figure 6, after the data set 500 originally stored in the memory block 108-1 is checked and corrected by the error correction circuit 110, data composed of corrected data corresponding to each column of data in the data set 500 is obtained. Set 620, data set 620 is programmed into memory block 108-3. As a result, the data set originally stored in the memory block 108-1 will be considered to have been "moved" to the memory block 108-3, which means that the data set 620 stored in the memory block 108-3 will be is considered to be the correct version of data set 500, and memory block 108-3 is used to perform the search operation instead of memory block 108-1.

Please refer to FIG. 7 , which is a schematic diagram of error correction according to an embodiment of the present invention. Data 700 is the data read from the memory unit on the first signal line SL2 in Figure 5B, in which bit b9 is an error bit. Logic 710 is a computational block equivalent to an error correction circuit. The bits b1, b3, b5, b7, b9, and b11 are taken out and sent to the checking unit 730 for an even parity check (even parity check), that is, it is calculated whether the number of 1's in these bits is an even number (if so, the check result is 1, if not, the check result is 0), and C1=1 is obtained. The bits b2, b3, b6, b7, b10, and b11 are taken out and sent to the checking unit 740 for even and identical bit checking, and C2=0 is obtained. Bits b4, b5, b6, and b7 are taken out and sent to the checking unit 750 for even and identical bit checking, and C3=0 is obtained. Bits b8, b9, b10, and b11 are taken out and sent to the checking unit 760 for even and identical bit checking, and C4=1 is obtained. Then, the outputs of the checking units 730 to 760 are sent to the calculation unit 770 to calculate N=8*C4+4*C3+2*C2+C1. If N is 0, it means there is no error; if N is not 0, it means the Nth bit starting from the least significant bit is an error bit. In this embodiment, the least significant bit is bit b1, and N is 9, which means that the ninth bit b9 starting from bit b1 is an error bit. Therefore, the calculation unit 770 can change the ninth bit from 0 to 1 according to the operation result N to obtain the correction data 720 and output it.

Please refer to FIG. 8 , which illustrates an operation flow of a memory device according to an embodiment of the present invention.

In step S801, an error correction check (ECC check) is performed, column by column until the entire range has been checked. The entire range here refers to the memory units that store data in a memory block. In other words, memory cells that do not store data do not need to be checked for error correction. For example, taking the example of Figures 5A~5D, the memory area Block 108-1 actually has m columns of memory cells, but when performing an error correction check, only the four columns of memory cells with stored data, that is, the memory cells on the first signal lines SL1 to SL4, can be read.

In step S802, it is determined whether an error bit is detected. If yes, execute step S803; if not, execute step S806. Referring to the foregoing description, step S802 may be performed by the error correction circuit 110 .

In step S803, the memory unit corresponding to the first signal line where the error bit detected in the error correction check is located is programmed to correct the data in the memory unit storing the error bit. The control circuit 112 may decide which memory cell on which first signal line to program based on the check result of the error correction circuit 110 . This method is suitable for memory types that allow individual programming and erasing operations on a single word line.

In step S804, it is determined whether the memory cell storing the error bit can be reprogrammed. If yes, perform step S805; if not, perform step S805. The control circuit 112 may perform verification after programming the memory cell on the first signal line corresponding to the error bit detected in the error correction check according to the output of the error correction circuit 110 to confirm whether the data in the memory cell in the column after programming is Same as the correction data (correct data) to be programmed. The reason why the incorrect bits stored in the memory cell cannot be changed through reprogramming may be that the memory cell is damaged.

In step S805, another row of memory cells (ie, memory cells on another bit line/match line) is used to store the correct version of the data. The reason why the erroneous bits stored in the memory cells cannot be corrected through reprogramming may be that the memory cells are damaged. Therefore, the control circuit 112 can select the memory cell on another bit line/match line to Store the correct version of the row of user data corresponding to the memory cell that cannot be reprogrammed (ie, the row of user data after the incorrect bits have been corrected). Taking the examples of Figures 2 and 5B as an example, if the memory unit U2-3 cannot be reprogrammed to store correct data, the control circuit 112 can store the memory units U1-3~U4-3 on the second signal line BL3. The correct version of the user data (i.e. 1111, not 1011) is programmed into the memory units U1-12~U4-12 on the second signal line BL12.

In step S806, a search request is applied.

In step S807, it is determined whether the error correction check is triggered. If yes, execute step S801; if not, execute step S806.

The process of this embodiment may be executed individually for each memory block in the memory device.

During a search operation, the check lines used to store check codes may not be searched or the search results may not be output. In one embodiment, the control circuit 112 may instruct the second driving circuit not to apply a search bias to the second signal line corresponding to the check row when performing a search operation on the memory block. In another embodiment, the control circuit 112 may instruct the sensing circuit not to detect current flowing from the third signal line corresponding to the check row when performing a search operation on the memory block. A specific implementation method is, for example, a current sensing unit (eg, a sense amplifier) in a disabling sensing circuit for detecting the third signal line corresponding to the inspection row.

In one embodiment, the location and number of check rows are fixed. In another embodiment, the position and number of inspection rows are variable, such as dynamically configured by the control circuit 112 .

On the other hand, the present invention can be combined with an error correction mechanism for input during search to achieve better search result reliability. For example, an error correction circuit for the input data (data to be searched) during search can be configured in the first driving circuit to ensure that the search voltage applied by the first driving circuit to the memory block corresponds to the actual search voltage. material.

The present invention can perform error correction operations on memory blocks that are not stored in search operations, so as to increase the accuracy of the data set stored in the memory blocks. This allows search operations to be targeted at the correct set of data, thereby improving the reliability of search results.

In summary, although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

S301~S307: steps

Claims (8)

A memory device, including: a plurality of memory blocks, each memory block including a plurality of memory units; a plurality of drive circuits coupled to the memory blocks; an error correction circuit coupled to the memory areas block; and a control circuit coupled to the drive circuits and the error correction circuit for selecting one of the memory blocks as a target block and performing an error correction operation on the target block. The memory units of the block have a plurality of rows and a plurality of columns. The rows include at least one data row and at least one check row. The data stored in the memory units of the at least one data row is user data. The at least one data row is user data. The data stored in the memory units of a check row is a check code, and the at least one check code stored in the memory units in each column is based on the user data stored in the memory units in the same column. Produced; wherein the error correction operation includes reading the memory cells of the columns of the target block column by column, and transmitting the data stored in the memory cells of the columns of the target block to the error correction circuit, The error correction circuit checks whether there are error bits in the user data stored in the memory units in each column based on the at least one check code stored in the memory units in each column and performs corrections to generate corresponding A correction data of the data stored in the memory units of each column, wherein in the target block, the memory units of the column in which the user data stored in the target block are checked to have erroneous bits are based on the corresponding The correction data of the data stored in the memory cells of the column is programmed. The memory device of claim 1, wherein the correction data corresponding to the data stored in the memory cells of each column of the target block is programmed into another of the memory blocks. . The memory device of claim 1, wherein for the memory cells of the row that have error bits and whose stored data cannot be changed through programming, a portion of the data stored in the memory cells of the row is The correct version is programmed into the memory cells of another row in the target block. The memory device of claim 1, wherein the driving circuits include a bit line driving circuit, and when performing a search operation on the target block, the bit line driving circuit does not apply a search bias to the corresponding In at least one bit line of the at least one check row; or when performing a search operation on the target block, the sensing circuit does not detect the current flowing out of the at least one match line corresponding to the at least one check row. An operating method of a memory device, including: selecting one of a plurality of memory blocks as a target block to perform an error correction operation. The target block includes a plurality of memory units, and the memory units have a plurality of rows. and a plurality of columns, the rows include at least one data row and at least one check row, and the data stored in the memory units of the at least one data row is user data, The data stored in the memory units of the at least one check row is a check code, and the at least one check code stored in the memory units of each column is based on the users stored in the memory units of the same column. Data is generated; reading the memory cells of the columns of the target block column by column; transmitting the data stored in the memory cells of the columns of the target block to an error correction circuit; the error correction circuit According to the at least one check code stored in the memory units of each column, check whether there are error bits in the user data stored in the memory units of each column and perform corrections to generate the user data corresponding to each column. A correction data of the data stored in some memory units; and for the memory units of the column in which the user data stored in the target block has erroneous bits, according to the memory units corresponding to the column The correction data of the stored data is programmed. The operating method of claim 5 further includes: programming the correction data corresponding to the data stored in the memory units of each column of the target block to another memory block among the memory blocks. The operating method as described in claim 5, wherein for the memory cells of the row that have erroneous bits and whose stored data cannot be changed through programming, a correct value of the data stored in the memory cells of the row is The version is programmed into the memory cells of another row in the target block. The operating method of claim 5 further includes: when performing a search operation on the target block, not applying a search bias to at least one bit line corresponding to the at least one check row; or when performing a search operation on the target block; When the target block performs a search operation, the current flowing out of the at least one matching line corresponding to the at least one check row is not detected.

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