KR101532819B1 - Methods, devices, and systems for dealing with threshold voltage change in memory devices - Google Patents

Methods, devices, and systems for dealing with threshold voltage change in memory devices Download PDF

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KR101532819B1
KR101532819B1 KR1020127007493A KR20127007493A KR101532819B1 KR 101532819 B1 KR101532819 B1 KR 101532819B1 KR 1020127007493 A KR1020127007493 A KR 1020127007493A KR 20127007493 A KR20127007493 A KR 20127007493A KR 101532819 B1 KR101532819 B1 KR 101532819B1
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voltage
memory cells
vt
state
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KR20120062818A (en
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젠레이 센
윌리엄 에이치. 라드케
피터 필레이
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마이크론 테크놀로지, 인크.
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

The present application includes methods, devices, and systems for processing threshold voltage changes in memory devices. Many embodiments include a control circuit having an array of memory cells and a sense circuit coupled to the array. The control circuit is configured to determine changes in threshold voltages (Vt) associated with memory cells without using a reference cell, and to adjust the sense circuit based on the determined changes and without using reference cells.

Description

[0001] METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES [0002] FIELD OF THE INVENTION [0003]

The present disclosure relates generally to semiconductor memory devices, methods, and systems, and more particularly, to methods, devices, and systems for handling threshold voltage changes in memory devices.

Memory devices are typically provided as internal, semiconductor, integrated circuits and / or external removable devices in computers or other electronic devices. In particular, a plurality of memory cells, including random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change random access memory There are different types of memory.

Flash memory devices can be utilized as volatile and non-volatile memory for a wide range of electronic applications. Typically, flash memory devices use a one-transistor memory cell that allows for high memory density, high reliability, and low power consumption.

The use of a flash memory is advantageous over other electronic devices such as solid state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, Players, and movie players. Typically, data such as program code, user data, and / or system data such as a basic input / output system (BIOS) are stored in flash memory devices.

Two common types of flash memory array architectures are "NAND" and "NOR" architectures for the logical form in which each so-called conventional memory cell arrangement is arranged. The NAND array architecture arranges an array of its memory cells into a matrix such that the control gates of each memory cell in the "row" of the array are coupled to an access line, commonly referred to in the art as a "word line" (In some cases, forming). However, each memory cell is not directly coupled to its data line (which is generally referred to in the art as a digit line, e.g., a bit line) by its drain. Instead, the memory cells of the array are coupled together in series to a source-drain, between a common source and a data line, where memory cells commonly coupled to a particular data line are referred to as "columns. &Quot;

The memory cells in the NAND array architecture can be programmed to the desired state. For example, the charge may be placed on the charge storage node of the memory cell to place the cell in one of a number of programmed states, or it may be removed from the charge storage node of the memory cell. For example, a single level cell (SLC) may represent two states, e.g., 1 or 0. Flash memory cells may also have more than two states, for example, 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, Can be stored. These cells are referred to as multi-level cells (MLCs). MLCs may allow the fabrication of higher density memories without increasing the number of memory cells because each cell may represent more than one digit, for example, more than one bit. For example, a cell that can represent four digits may have sixteen programmed states.

The charge stored on the charge accumulation node of the memory cells, for example the threshold voltage Vt, may change because the flash memory cells undergo the programming, sensing, and erasing cycles over time, Can be generated. That is, the determined state of the memory cell during the sensing operation performed on the cell may be other than the state in which the cell is programmed. One approach to tracking and / or compensating for changes in Vt of a memory cell may include sensing operation for a memory cell, e.g., using a reference cell during a read. However, the use of a reference cell can increase the area of the memory array, reduce the amount of memory cells in the array, and / or increase the amount of circuitry associated with the memory device.

1 is a schematic diagram of a portion of a non-volatile memory array in accordance with multiple embodiments of the present disclosure;
2A illustrates a plurality of threshold voltage (Vt) distributions associated with memory cells programmed in accordance with multiple embodiments of the present disclosure.
FIG. 2B illustrates a plurality of Vt distributions associated with memory cells programmed in accordance with multiple embodiments of the present disclosure.
Figure 3 is a table of tracking gains and error rates associated with multiple changes in Vt distributions associated with memory cells programmed in accordance with multiple embodiments of the present disclosure.
4 illustrates a block diagram of a memory device in accordance with multiple embodiments of the present disclosure.
Figure 5 illustrates a block diagram of a memory device in accordance with multiple embodiments of the present disclosure.

The present application includes methods, devices, and systems for handling threshold voltage changes in memory devices. Many embodiments include a control circuit having an array of memory cells and a sense circuit coupled to the array. The control circuit is configured to determine changes in threshold voltages (V t) associated with memory cells without using a reference cell and to adjust the sense circuit based on the determined changes without using the reference cell.

Embodiments of the present invention provide a method and apparatus for determining changes in threshold voltages (V t) associated with a plurality of memory cells without using a reference cell, and determining a state of a plurality of memory cells based on Vt variations determined without using a reference cell May be used to adjust the voltage (s) used to sense and / or to sense the state of a plurality of memory cells using the regulated voltages. For example, embodiments of the present disclosure may be used to track and / or compensate for threshold voltage changes, e.g., shifts, in memory devices without using a reference cell. Tracking and / or compensation for threshold voltage changes may provide advantages, among other benefits, such as increased reliability, e.g., reduced error rate, and / or increased memory device lifetime.

In the following detailed description of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration how numerous embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments herein and that other embodiments may be utilized and that process, electrical, and / or structural changes may be made without departing from the scope of the present invention I understand.

As used herein, "multiple" may refer to more than one. For example, a plurality of memory devices may refer to one or more memory devices. Additionally, the indications "N" and "M ", as used herein in connection with the references in the drawings, indicate that a number of specific features so designated may be included with the numerous embodiments herein .

The figures herein follow a numbering convention in which the first digit or digits correspond to a drawing number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by use of similar digits. For example, 110 may refer to element "10" in FIG. 1, and a similar element may be referred to as 210 in FIG. As will be appreciated, the elements shown in the various embodiments herein may be added, exchanged and / or eliminated to provide further embodiments of the present disclosure. It is also to be understood that the proportions and relative scales of the elements provided in the figures are intended to illustrate the embodiments of the present application and should not be taken as limiting.

1 is a schematic diagram of a portion of a non-volatile memory array 100 in accordance with multiple embodiments of the present disclosure. The embodiment of FIG. 1 illustrates a NAND architecture non-volatile memory. However, the embodiments described herein are not limited to these examples. 1, memory array 100 includes access lines, e.g., word lines 105-1, ..., 105-N, and cross data lines, e.g., And bit lines 107-1, 107-2, 107-3, ..., 107-M. For ease of addressing in a digital environment, the number of word lines 105-1, ..., 105-N and the number of local bit lines 107-1, 107-2, 107-3, ..., 107 -M) may be a power of some two, for example, 256 word lines by 4096 bit lines.

The memory array 100 includes NAND strings 109-1, 109-2, 109-3, ..., 109-M. Each NAND string includes non-volatile memory cells 111-1, ..., 111-N coupled to each of the word lines 105-1, ..., 105- . The nonvolatile memory cells 111-1, ..., 111-N of the NAND strings 109-1, 109-2, 109-3, ..., 109- For example, a source-drain is connected in series between the field effect transistor 113 and the drain select gate SGD, for example, Each source select gate 113 is configured to selectively couple each NAND string to a common source 123 in response to a signal on a source select line 117 while each drain select gate 119 is configured to couple a drain select line Is configured to selectively couple each NAND string to each bit line in response to a signal on the bit line (115).

The source of the source select gate 113 is connected to the common source line 123, as shown in the embodiment illustrated in FIG. The drain of the source select gate 113 is connected to the source of the memory cell 111-1 of the corresponding NAND string 109-1. The drain of the drain select gate 119 is connected to the bit line 107-1 of the corresponding NAND string 109-1 at the drain contact 121-1. The source of the drain select gate 119 is connected to the last memory cell 111-N of the corresponding NAND string 109-1, e.g., the drain of the floating gate transistor.

As will be appreciated by those skilled in the art, subsets of cells coupled to a selected word line, e.g., (105-1, ..., 105-N) may be programmed and / or sensed together as a group, For example. A programming operation, e. G., A write operation, may be performed to increase the threshold voltage (Vt) of the selected cells coupled to the selected access line to a desired program voltage level corresponding to the desired program state, Programming pulses, e.g., 16V-20V, to the selected word line.

A sensing operation, such as a read or program verify operation, may include sensing a change in voltage and / or current of a bit line coupled to a selected cell to determine a state of the selected cell. For example, a plurality of voltages sufficient to place the unselected cells in the conductive state, for example, the pass voltage ("Vpass"), Sensing the state of the selected cell may include applying a plurality of sense voltages, e.g., read voltages ("Vread"), to the selected word line while biasing the word lines. The bit line corresponding to the selected cell that has been read and / or verified can be sensed to determine whether the selected cell is challenging in response to a particular sense signal applied to the selected word line. For example, the state of the selected cell may be determined by the word line voltage at which the bit line current reaches a particular reference current associated with a particular state.

The sense voltages used during the sensing operation of the selected cell, e.g., Vread, may be based on the potential Vt of the selected cell. For example, a voltage associated with Vt associated with one of the program states of the selected cell may be used as Vread. The voltage associated with Vt associated with one of the program states of the selected cell may include an average Vt, a Vt distribution, and / or a Vt distribution width, as described further herein, for example.

As will be appreciated by those skilled in the art, in a sensing operation performed on a memory cell selected in a NAND string, unselected memory cells of the string are biased to be in a conductive state. In this sensing operation, the state of the selected cell may be determined based on the sensed current and / or voltage for the bit line corresponding to the string. For example, the state of the selected cell may be determined based on whether the bit line current changes by a certain amount or reaches a certain level in a predetermined period.

When the selected cell is in the conductive state, a current flows between the source line contact portion at one end of the string and the bit line contact portion at the other end of the string. As such, the current associated with sensing the selected cell is carried through each of the other cells in the string, the diffusion regions between the cell stacks, and the selection transistors.

Figure 2a illustrates a plurality of threshold voltages Vt associated with memory cells programmed in accordance with multiple embodiments herein, e.g., memory cells 111-1, ..., 111-N, ≪ / RTI > 2A, Vt distributions 225-0, 225-1, 225-2, and 225-3 are programmed into one of four program states L0, L1, L2, and L3, respectively. In one embodiment, Lt; / RTI > However, the embodiments herein are not limited to memory cells programmed with a particular number of states, for example, memory cells may be programmed with more or less than four program states. As those skilled in the art will appreciate, program states L0, L1, L2, and L3 may represent a plurality of stored data digits. For example, state L0 may represent binary data "11" stored by the data cell, state L1 may represent binary data "01" stored by the cell, state L2 may represent binary data &Quot;, and state L3 may represent binary data "10" stored by the cell.

In many embodiments of the invention, a plurality of programming voltage pulses may be applied to the control gate of a memory cell to program the cell by increasing the Vt level of the cell to a desired level. For example, in the embodiment shown in FIG. 2A, during a programming operation, the Vt level of the memory cells to be programmed to program state L1 is increased until the Vt level reaches the Vt level associated with the Vt distribution 225-1 do. The Vt level of the memory cells to be programmed in the programmed state L2 is increased until the Vt level reaches the Vt level associated with the Vt distribution 225-2. The Vt level of the memory cells to be programmed in the program state L3 is increased until the Vt level reaches the Vt level associated with the Vt distribution 225-3.

The Vt distribution may include multiple Vt levels. For example, the Vt distribution may include an average Vt level among other Vt levels. The average Vt level may correspond to the expected Vt level for a given Vt distribution. In many embodiments, the average Vt level may correspond to a peak of its associated Vt distribution, e.g., the average Vt level of a particular Vt distribution may correspond to a peak of a memory cell programmed with a program state corresponding to a particular Vt distribution A common Vt level can be indicated. However, the embodiments of the present invention are not limited thereto. For example, the average Vt level may not correspond to the peak of its associated Vt distribution if its associated Vt distribution is asymmetric.

2A, each Vt distribution includes an average Vt level, for example, the Vt distribution 225-0 includes Vmean0, the Vt distribution 225-1 includes Vmean1, Vt distribution 225-2 includes Vmean2, and Vt distribution 225-3 includes Vmean3. In addition, the difference in voltage between the average Vt levels associated with adjacent Vt distributions is shown as "d" in FIG. 2A. That is, d illustrates the difference in the voltage between Vmean1 and Vmean0, the difference in the voltage between Vmean2 and Vmean1, and the difference in the voltage between Vmean3 and Vmean2.

The Vt distribution may also have a Vt distribution width associated therewith. The Vt distribution width may correspond to a range of Vt levels associated with a particular Vt distribution. In the embodiment shown in FIG. 2A, the Vt distribution width (

Figure 112012023424552-pct00001
) Are associated with the Vt distributions 225-0, 225-1, 225-2, and 225-3. Vt distribution width (
Figure 112012023424552-pct00002
) May correspond to a range of Vt levels within one standard deviation of the average Vt level for a particular Vt distribution. For example, the Vt distribution width (
Figure 112012023424552-pct00003
Has a range of Vt levels within one standard deviation of Vmean0 for Vt distribution 225-0, a range of Vt levels within one standard deviation of Vmean1 for Vt distribution 225-1, a range of Vt distribution 225-2 A range of Vt levels within one standard deviation of Vmean2 and a range of Vt levels within one standard deviation of Vmean3 for Vt distribution 225-3. However, embodiments of the present application are not limited thereto and may include other Vt distribution widths. For example, the Vt distribution width may correspond to a range of all Vt levels associated with a particular Vt distribution.

In many embodiments of the present application, the sense voltages used during a sensing operation of a memory cell programmed with a program state associated with the Vt distribution shown in FIG. 2A may be based on the Vt distributions shown in FIG. 2A. For example, the sense voltages may include Vt levels associated with Vt distributions such as average Vt levels, e.g., Vmean0, Vmean1, Vmean2, and / or Vmean3, and /

Figure 112012023424552-pct00004
Lt; RTI ID = 0.0 > Vt < / RTI >

The sensing operation of the memory cell programmed into the program state associated with the Vt distribution shown in FIG. 2A may have an error rate associated with the sensed state, for example, an error rate. That is, the sensed state of the memory cell may be a state other than the state where the cell is programmed. The ratio of the number of times the sensed state of the memory cell with respect to the error rate, for example, the total number of times the state of the memory cell is sensed,

Figure 112012023424552-pct00005

, Where Q is the tail probability of the standard Gaussian distribution.

FIG. 2B illustrates a plurality of Vt distributions associated with memory cells programmed in accordance with various embodiments of the present application, for example, memory cells 111-1, ..., 111-N shown in FIG. do. 2B, the Vt distributions 227-0, 227-1, 227-2, and 227-3 are arranged in a manner similar to that described above with respect to FIG. 2A, with four program states L0 , L1, L2, and L3, where memory cells also experience additional programming, sensing, and / or erasing cycles. Additional programming, sensing, and / or erasing cycles may cause the stored charge on the floating gates of the memory cells to change, which may cause a change in Vt distributions, e.g., shift, as shown in Figure 2b have. That is, additional programming, sensing, and / or cancellation cycles may cause the Vt distribution 225-0 to have a Vt distribution 227-0 and the Vt distribution 225-1 to have a Vt distribution 227-1 , Vt distribution 225-2 to Vt distribution 227-2, and Vt distribution 225-3 to Vt distribution 227-3.

As shown in FIG. 2B, a change in the Vt distributions may cause the Vt levels associated with the Vt distributions to change. For example, a change in the Vt distributions may cause the average Vt levels associated with the Vt distributions to change. The change in average Vt levels is shown in Figure 2b

Figure 112012023424552-pct00006
As shown in FIG. In other words,
Figure 112012023424552-pct00007
From the Vt distribution 225-2 to the Vt distribution 227-0, from the Vt distribution 225-1 to the Vt distribution 227-1, from the Vt distribution 225-2 to the Vt distribution 227-2, Vmean0, Vmean2, and Vmean3 arising from the respective changes from the Vt distribution 225-3 to the Vt distribution 227-3.

The change in Vt distributions can also cause the Vt distribution widths associated with Vt distributions to change, as shown in FIG. 2B. For example, a change in Vt distributions may be represented by a Vt distribution width (

Figure 112012023424552-pct00008
Can be made to change, for example, to be wider.

The magnitude of the variation of the Vt distributions, e.g., the magnitude of the variations of the Vt distribution widths and / or Vt levels associated with the Vt distributions, is dependent on the programming, sensing, and / Depending on the number of cells. The magnitude of the change in Vt distributions may also depend on the temperature (s) during which the memory cells are exposed during the cycles. For example, the magnitude of the change in Vt distributions may increase as the number of cycles performed for memory cells increases and / or the temperature (s) the memory cells are exposed during cycles.

A change in the Vt distribution, such as a change in Vt distributions as shown in FIG. 2B, may cause a false detection of a memory cell associated with the Vt distribution, for example, if the Vt distribution change is not tracked and / . That is, if the change in the Vt distribution is not tracked and / or compensated, then the sensed state of the memory cell associated with the Vt distribution may be in a state other than the state in which the cell is programmed. For example, the sensed state of a memory cell programmed in program state Ll may be a program state (L2).

The error rate of the sensing operation of the memory cell associated with the Vt distribution experiencing the change,

Figure 112012023424552-pct00009

Where Q is the tail probability of a standard Gaussian distribution, and d,

Figure 112012023424552-pct00010
, And
Figure 112012023424552-pct00011
≪ RTI ID = 0.0 > d, <
Figure 112012023424552-pct00012
, And
Figure 112012023424552-pct00013
to be. The error rate may represent the ratio of the number of times the sensed state of the memory cell with respect to the total number of times the state of the memory cell is sensed is in a state other than the state where the cell is programmed due to the Vt distribution change. In addition, the tracking gain associated with the Vt distribution experiencing the change,

Figure 112012023424552-pct00014

, Where d is the d associated with Figure 2a,

Figure 112012023424552-pct00015
Lt; RTI ID = 0.0 >
Figure 112012023424552-pct00016
to be. The tracking gain may be used to determine the number of memory cells in which the sensed state may not be in a programmed state due to a change in Vt distribution. Thus, the average Vt level associated with the Vt distribution change (
Figure 112012023424552-pct00017
) And / or a larger Vt distribution width associated with the Vt distribution change (
Figure 112012023424552-pct00018
) Is greater than the larger error rate of the sensing operation of the memory cells associated with the changed Vt distribution and / or the greater number of memory cells associated with the changed Vt distribution where the sensed state may not be the programmed state of the cell . ≪ / RTI >

FIG. 3 illustrates a plurality of variations of Vt distributions associated with memory cells programmed in accordance with various embodiments of the present disclosure, e.g., tracking gains and error rates associated with shifts, e.g., a table of error rates (300). The memory cells are programmed in one of four program states (L0, L1, L2, and L3) in a manner similar to that described above with respect to Figure 2A, and Vt distributions, e.g., Vt levels associated with Vt distributions Is increased in 20 millivolts (mV) increments, and the difference in voltage between adjacent mean Vt levels, e.g., d, is held at 1600 mV. The tracking gain and error rate associated with each Vt distribution are determined using the formulas described above with respect to FIG. 2B.

The error rate associated with each Vt distribution may indicate the error rate that occurs when the Vt distribution changes are not tracked and / or compensated. Failure in tracking and / or compensating for Vt distribution variations can result in erroneous sensing of memory cells. The tracking gain associated with each Vt distribution may represent a potential benefit that can be achieved by tracking and / or compensating for Vt distribution changes. For example, the tracking gain may indicate the extent to which erroneous sensing of memory cells may be reduced by tracking and / or compensating for Vt distribution changes in accordance with many embodiments of the present disclosure.

As shown in table 300, the tracking gains and error rates increase as the Vt distribution variation increases. For example, the tracking gain and error rate associated with a Vt distribution change of 60mV are 0.677dB and 3.0E-17, respectively, and the tracking gain and error rates associated with a Vt distribution change of 80mV are 0.915dB and 2.0E-15, respectively. However, the error correction code (ECC) decoder can only correct an error rate of less than 1.0E-15, for example if the error rate exceeds 1.0E-15, the error correction operation may fail. Thus, the ECC decoder may not be able to track and / or compensate for Vt distribution changes above 80 mV.

FIG. 4 illustrates a block diagram of a memory device 400 in accordance with multiple embodiments of the present disclosure. As shown in FIG. 4, the memory device 400 includes a memory array 440. The memory array 440 may be, for example, the memory array 100 described above with respect to FIG. Memory array 440 may include, for example, single level memory cells (SLCs) and / or multi-level memory cells (MLCs) capable of storing four program states. However, the embodiments are not limited thereto and may include other MLCs. In many embodiments, the memory array 440 may not include any reference memory cells, and, for example, the memory array 440 may include only data memory cells.

In many embodiments, the memory device 400 may perform hard sensing operations. That is, in the absence of changes in the Vt's of memory cells in the memory array 440, the memory array 440 does not output the sensed Vt's to the control circuit 442, The state (s) of the memory cells in the memory cell.

As shown in FIG. 4, the memory device 400 also includes a control circuit 442 coupled to the memory array 440. The control circuit 442 includes a sense circuit 444 and an error correction code (ECC) decoder 446. The control circuit 442 may use threshold voltages Vt associated with memory cells in the memory array 440 without using reference cells, e.g., Vt distribution widths, Vt levels such as average Vt levels, and / or Vt Lt; RTI ID = 0.0 > distributions. ≪ / RTI > The control circuit 442 may then adjust the sense circuit 444 to sense the state of the memory cells based on the determined Vt variations without using the reference cell and may, for example, Can be adjusted. The sensing circuit 444 can then use the adjusted V ts to sense the state of the memory cells in the memory array 440. That is, the control circuit 442 may track and / or compensate for Vt variations of the memory cells in the memory array 440 without using the reference cell.

For example, the sense circuit 444 may sense the state of the memory cells using a first voltage to sense a programmed cell in a particular program state. The ECC decoder 446 may then perform an error correction operation on the sensed state. If the error correction operation fails, the sensing circuit 444 may sense the state of the memory cells using a second voltage, e. G., A different voltage than the first voltage, to sense the programmed cell in a particular program state have. The ECC decoder 446 may perform an error correction operation on the sensed state using the second voltage, and if such an error correction operation again fails, the sensing circuit 444 senses the cell programmed to a particular programmed state A voltage different from the third voltage, e.g., the first and second voltages, may be used to sense the state of the memory cells. Such a process may continue until an error-correcting operation that does not fail, for example, a successful error-correcting operation, occurs. For example, the sense circuit 444 may sense the state of the memory cells using the second voltage only if the error correction operation performed on the sensed state using the first voltage fails.

In many embodiments, the process described in the previous paragraph can be performed while the memory device 400 is in the test mode. For example, the test mode may be triggered by an initial failure of an error correction operation, e.g., a failure of an error correction operation that occurs prior to the start of the process described by the previous paragraph.

In many embodiments, the control circuit 442 may increase or decrease the voltage used to sense the state of the memory cells by a particular amount of voltage. For example, the second voltage may be 20 mV larger than the first voltage, and the third voltage may be 20 mV larger than the second voltage. However, the embodiments of the present application are not limited to one particular amount of voltage, for example, the voltage may increase or decrease by an amount of voltage other than 20 mV and / or the amount of each increase or decrease of the voltage may be different. In many embodiments, the amount of increase or decrease in voltage may depend on the number of programming, sensing, and / or erasing cycles previously performed on the memory cells, and / or the age of the memory cells. For example, the amount of voltage may increase as the number of programming, sensing, and / or erasing cycles previously performed increases, and the amount of voltage may decrease as the memory cells age increase.

In addition, the number of voltages used before a successful error correcting operation occurs may depend on the specific amount of voltage at which the voltages increase. For example, the number of voltages used before a successful error correction operation occurs may increase as the specific amount of voltage at which the voltages increase is reduced. Also, in many embodiments, the sensing circuit 444 may use other voltages of no more than ten.

The error correction operation may fail if the ECC decoder 446 can not correct errors associated with the sensed state. For example, an error correction operation performed on the sensed state using the first voltage may fail if the ECC decoder 446 can not correct errors associated with the sensed state using the first voltage. The ECC decoder 446 may not be able to correct errors associated with the sensed state if the number of errors associated with the sensed state exceeds the correction capability of the ECC decoder 446. [ The correction capability of ECC decoder 446 may be, for example, 12 bit errors.

In many embodiments, the first voltage may be a predetermined voltage, e.g., a voltage associated with the initial programming operation. In many embodiments, the first voltage may be a voltage determined by the control circuit 442 to be least likely to cause the error correction operation to fail. The use of a voltage least likely to cause an error correction operation to fail may result in fewer sensing and error correction operations performed by the sensing circuit 444 and the ECC decoder 446, respectively.

The control circuit 442 may use a plurality of programming and sensing operations previously performed on a plurality of memory cells and / or memory cells programmed to a particular state to determine a voltage that is seldom likely to cause an error correction operation to fail have. For example, the plurality of programming and sensing operations previously performed on the plurality of memory cells and / or memory cells that have been programmed in a particular state may be used to determine an algorithm that is less likely to cause an error correction operation to fail Lt; / RTI > The algorithm may be implemented in firmware (not shown in FIG. 4) located in the control circuit 442. Alternatively, the algorithm may be implemented in hardware and / or software.

In many embodiments in which the memory array 440 includes MLCs containing four program states, the sense circuit 444 may be configured to sense the first voltage and the second program state to sense the first program state The second voltage can be used to sense the state of the memory cells. The first and second programmed states may be, for example, L1 and L2, respectively, as described above with respect to Figures 2A and 2B. The ECC decoder 446 may then perform an error correction operation on the sensed state. If the error correcting operation fails, the sensing circuit 444 generates a third voltage, e.g., a voltage that is different from the first voltage as a voltage used to sense the first program state, and a fourth voltage, e. G. A voltage different from the second voltage may be used as the voltage used to sense the second program state to sense the state of the memory cells. The ECC decoder 446 may perform an error correction operation on the sensed state using the third voltage and the fourth voltage and if such an error correction operation also fails the sensing circuit 444 generates a fifth voltage, A voltage that is different from the first and third voltages as the voltage used to sense the first program state and a second and third voltages that are used to sense the sixth voltage, A voltage different from the fourth voltages may be used to sense the state of the memory cells. Such a process may continue until an error-correcting operation that does not fail, for example, a successful error-correcting operation, occurs. For example, the sense circuit 444 may use the third and fourth voltages to sense the state of the memory cells only if the error correction operation performed on the sensed state using the first and second voltages fails have. In addition, the error correction operation may fail if the ECC decoder 446 can not correct errors associated with the sensed state, as described hereinabove.

The process described in the previous paragraph can be performed while the memory device 400 is in the test mode. In addition, the voltages may be increased or decreased by a certain amount of voltage. For example, the third voltage may be 20 mV larger than the first voltage, and the fifth voltage may be 20 mV larger than the third voltage. However, the embodiments of the present application are not limited to one particular amount of voltage, for example, the voltages may be increased or decreased by a voltage amount other than 20 mV, and / or the amount of increase or decrease of each voltage may be different. Additionally, the amount of increase or decrease in voltage may depend on the number of programming, sensing, and / or erasing cycles previously performed on the memory cells, as described herein above. In addition, the number of voltages used before a successful error correcting operation occurs may depend on the specific amount of voltage at which the voltages increase, as described herein above.

In many embodiments, the first and second voltages may be predetermined voltages, e.g., voltages associated with the initial programming operation. In many embodiments, the first and second voltages may be voltages determined by the control circuit 442 to be less likely to cause the error correction operation to fail. The control circuit 442 may be previously implemented for a number of memory cells and / or memory cells programmed with a particular program state, e.g., a first program state and / or a second program state, as described herein above A number of programming and sensing operations may be used to determine voltages that are less likely to cause an error correction operation to fail.

A number of previous approaches for tracking and / or compensating for changes in Vt of a memory cell may include sensing for a memory cell, e.g., using a reference cell during a read operation. However, the use of a reference cell can increase the area of the memory array, reduce the amount of memory cells in the memory array, and / or increase the amount of circuitry associated with the memory device. Conversely, for example, tracking and / or compensation of Vt variations in memory cells according to many embodiments herein without the use of a reference cell may reduce the area of the memory array, / RTI > and / or reduce the amount of circuitry associated with the memory device.

The embodiment illustrated in FIG. 4 may include additional circuitry not illustrated so as not to obscure the embodiments of the present disclosure. For example, memory device 400 may include an address signal for latching address signals provided on I / O connectors through I / O circuitry. The address signals may be received and decoded by the row decoder and column decoder to access the memory array 440. Those skilled in the art will appreciate that the number of address input connectors may depend on the density and architecture of memory device 400 and / or memory array 440.

5 illustrates a block diagram of a memory device 500 in accordance with multiple embodiments of the present disclosure. As shown in FIG. 5, the memory device 500 includes a memory array 540. The memory array 540 may be, for example, the memory array 100 described above with respect to FIG. Memory array 540 may include MLCs, such as, for example, MLCs capable of storing eight or sixteen program states. However, embodiments are not so limited and may include other types of MLCs and / or SLCs. In many embodiments, the memory array 540 may not include any reference memory cells, and, for example, the memory array 540 may include only data memory cells.

In many embodiments, the memory device 500 may perform a soft sensing operation. For example, the sensed V ts are output from the memory array 540 to the control circuit 542 and the control circuit 542 uses the sensed V ts to determine the state (s) of the memory cells in the memory array 540 . In a soft sense operation, the number of sensed states is greater than the number of states stored by the memory cells in the memory array 540. For example, in embodiments where the memory array 540 includes MLCs capable of storing 16 program states, the soft sensing operation may generate 128 sensed states. The soft sensing operation may provide more information, e.g., reliability information, about the states of the memory cells than the hard sensing operation. The information obtained from the soft sensing operation may be input into an algorithm, e.g., a minimum mean square error (MMSE) algorithm, as further described herein.

As shown in FIG. 5, the memory device 500 also includes a control circuit 542 coupled to the memory array 540. The control circuit 542 includes a sense circuit 544. The control circuit 542 may use the reference cells to determine the Vts associated with the memory cells in the memory array 540, such as Vt distributions, Vt levels such as average Vt levels, and / or Vt distribution widths Lt; / RTI > The control circuit 542 may then adjust the sense circuit 544 to sense the state of the memory cells based on the determined Vt variations without using the reference cell and may, for example, Can be adjusted. The sensing circuit 544 may then use the adjusted V ts to sense the state of the memory cells in the memory array 540. That is, control circuit 542 may track and / or compensate for Vt variations in the memory cells of memory array 540 without using a reference cell.

For example, sense circuit 544 may sense Vts associated with memory cells in memory array 540, e.g., Vt distributions, Vt levels such as average Vt levels, and / or Vt distribution widths can do. Control circuitry 542 may then use the sensed V ts to determine a plurality of voltages corresponding to a plurality of program states associated with memory cells, wherein each determined voltage comprises a respective one of the plurality of program states Corresponds to one. For example, the control circuit 542 may use the sensed Vts to determine a plurality of mean Vt levels, Vt distributions, and / or Vt distribution widths, wherein each mean Vt level, Vt distribution, and / Or Vt distribution width corresponds to each one of the plurality of program states. Control circuitry 542 may then determine the plurality of voltages corresponding to the plurality of program states using the determined average Vt levels, Vt distributions, and / or Vt distribution widths, The circuit 544 can sense the state of the memory cells using the determined voltages. Alternatively, the control circuit 542 may provide the average Vt levels, Vt distributions, and / or Vt distribution widths determined with the sensed Vt levels to an ECC decoder, e.g., a soft ECC decoder (not shown in Figure 5) . This may provide more information, e.g., reliability information, about the states of the memory cells, which may result in greater processing gain.

In many embodiments, sensed V ts may be input to the algorithm to determine the multiple voltages corresponding to the plurality of program states associated with memory cells. The algorithm may be implemented in firmware (not shown in FIG. 5) located in the control circuit 542. Alternatively, the algorithm may be implemented in hardware and / or software. The algorithm may be, for example, a minimum mean square error (MMSE) algorithm. However, embodiments are not so limited, and may include any algorithm capable of determining the multiple voltages corresponding to the plurality of program states.

The MMSE algorithm, which can determine its multiple voltages corresponding to its multiple program states, may include initialization and multiple iterations. The initialization may include the following steps.

Figure 112012023424552-pct00019

M is the number of program states associated with memory cells,

Figure 112012023424552-pct00020
Is the Vt level associated with each program state, e.g., the average Vt level. For example, if the memory cells are MLCs capable of storing eight program states, M is 8, and 8
Figure 112012023424552-pct00021
The values are 8 program states and corresponding 8 Vt levels, e.g., average Vt levels.

The iteration of the MMSE algorithm may include the following steps.

Figure 112012023424552-pct00022

In repetition,

Figure 112012023424552-pct00023
Are the determined Vt levels, e.g., the determined average Vt levels,
Figure 112012023424552-pct00024
Is a boundary Vt between two Vt distributions, e.g., a decision region boundary.
Figure 112012023424552-pct00025
RTI ID = 0.0 > Vt < / RTI &
Figure 112012023424552-pct00026
), For example, a region between two adjacent V ts,
Figure 112012023424552-pct00027
Lt; / RTI >
Figure 112012023424552-pct00028
Lt; RTI ID = 0.0 > Vt < / RTI > Additionally, t is the iteration index, for example, t = 1 for the first iteration and t = 2 for the second iteration.

Thus, the input of the MMSE algorithm is the sensed Vt associated with the memory cells in the array 540, and the output of the MMSE algorithm is the determined Vt levels, e.g., the determined average Vt levels (

Figure 112012023424552-pct00029
) And boundary Vt's (
Figure 112012023424552-pct00030
)to be. During each iteration, the sensed V ts are determined based on the comparison to the boundaries V t,
Figure 112012023424552-pct00031
), And the determined Vt levels and boundaries Vt are updated based on the partitioning.

Also,

Figure 112012023424552-pct00032
Lt; RTI ID = 0.0 > Vt < / RTI > levels, for example,
Figure 112012023424552-pct00033
), E.g., a difference, for example,
Figure 112012023424552-pct00034
Is a measure of the similarity between the results of two consecutive iterations. If the discrepancy between two consecutive determined Vt levels is greater than a certain amount (
Figure 112012023424552-pct00035
), For example, if two consecutive determined Vt levels are sufficiently similar, the iterations of the algorithm are not further driven and the algorithm ends. However, if the discrepancy between two consecutive determined Vt levels is greater than a certain amount (
Figure 112012023424552-pct00036
), For example, if two consecutive determined Vt levels are not sufficiently similar, an additional iteration of the algorithm is driven. That is, the iterations of the algorithm are such that two consecutive determined Vt levels are equal to a certain amount (
Figure 112012023424552-pct00037
) Is not exceeded. Changes in V ts associated with memory cells have been tracked, and V ts corresponding to program states associated with, for example, memory cells, have been detected such that mismatches between two consecutive determined V t levels
Figure 112012023424552-pct00038
). ≪ / RTI >

A number of previous approaches for tracking and / or compensating for changes in Vt of a memory cell may include sensing for a memory cell, e.g., using a reference cell during a read operation. However, the use of reference cells can increase the area of the memory array, reduce the amount of memory cells in the array, and / or increase the amount of circuitry associated with the memory device. Conversely, for example, tracking and / or compensation of Vt variations in memory cells according to many embodiments herein without the use of a reference cell may reduce the area of the memory array, And / or reduce the amount of circuitry associated with the memory device.

The embodiment illustrated in FIG. 5 may include additional circuitry not illustrated so as not to obscure the embodiments of the present disclosure. For example, memory device 500 may include address circuitry for latching address signals provided on I / O connectors through I / O circuits. The address signals may be received and decoded by the row decoder and column decoder to access the memory array 540. Those skilled in the art will appreciate that the number of address input connectors may depend on the density and architecture of the memory device 500 and / or memory array 540.

conclusion

The present application includes methods, devices, and systems for handling threshold voltage changes in memory devices. Many embodiments include a control circuit having an array of memory cells and a sense circuit coupled to the array. The control circuit is configured to determine a change in threshold voltages (V t) associated with memory cells without using a reference cell and to adjust the sense circuit based on the determined changes without using a reference cell.

Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that the computed types may be substituted for the specific embodiments shown to achieve the same result. This application is intended to cover adaptations or variations of the various embodiments herein. It is to be understood that the above description has been made in an exemplary manner, rather than in a limiting manner. The above embodiments, and combinations of other embodiments not specifically described herein, will be apparent to those skilled in the art upon review of the above description. The scope of the many embodiments herein includes other applications in which the above structures and methods are used. Accordingly, the scope of the many embodiments of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of streamlining the present disclosure. The method herein is not to be interpreted as reflecting an intention that the disclosed embodiments should employ more features than are expressly recited in each claim. Rather, to reflect the following claims, the claims are in one single disclosed embodiment that is less than all features. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims (37)

13. A memory device comprising:
An array of memory cells; And
And a control circuit having a sense circuit coupled to the array,
The control circuit comprising:
By sensing a threshold voltage (V t) of each of the memory cells and determining a plurality of voltages for sensing a corresponding one of a plurality of states associated with the memory cells using the sensed V ts, Determine changes in V ts, each determined voltage for sensing one of the plurality of states,
Outputs the detected Vts and the determined plurality of voltages to an error correction code (ECC) decoder,
And adjust the sensing circuit based on the determined changes.
The method according to claim 1,
Wherein the control circuit includes the ECC decoder,
Wherein the sensing circuit is configured to sense a state of the memory cells using a first voltage,
Wherein the ECC decoder is configured to perform an error correction operation on the sensed state,
Wherein the sense circuit is configured to sense a state of the memory cells using a second voltage when the error correction operation fails.
The method of claim 2,
Wherein the ECC decoder is configured to perform an error correction operation on the sensed state using the second voltage,
Wherein the sense circuit is configured to sense a state of the memory cells using a third voltage if the error correction operation for the state sensed using the second voltage fails.
The method of claim 2,
Wherein the error correction operation fails if the ECC decoder is unable to correct errors associated with the state sensed using the first voltage.
The method of claim 2,
Wherein the control circuit is configured to determine a voltage that will cause the error correction operation to succeed,
Wherein the sensing circuit is configured to use the determined voltage as the first voltage.
The method of claim 5,
Wherein the control circuit is configured to use a plurality of memory cells programmed in a particular state and a plurality of programming and sensing operations previously performed on the memory cells to determine a voltage that will cause the error correction operation to succeed, device.
The method according to any one of claims 1 to 6,
Wherein the control circuit is configured to determine the changes in the V ts while the memory device is in a test mode.
A method of operating a memory device,
Determining changes in threshold voltages (Vt) of each of a plurality of memory cells, wherein determining changes in Vt's of each of the plurality of memory cells comprises:
Sensing Vt of each of the plurality of memory cells; And
Determining a plurality of voltages for respectively sensing a corresponding one of a plurality of states associated with the plurality of memory cells using the sensed Vt
Each determined voltage being for sensing a respective one of the plurality of states;
Outputting the detected Vts and the determined plurality of voltages to an error correction code (ECC) decoder;
Adjusting a voltage used to sense the state of the plurality of memory cells based on the determined changes; And
Sensing the state of the plurality of memory cells using the adjusted voltage.
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The method of claim 8,
Determining a plurality of average V ts using the sensed V ts, wherein each average V t corresponds to a respective one of a plurality of states; And
And determining the plurality of voltages using the average V t.
The method of claim 8,
The method comprises:
Determining a plurality of Vt distributions using the sensed Vts, wherein each Vt distribution corresponds to a respective one of the plurality of states; And
And using the Vt distributions to determine the plurality of voltages.
The method of claim 8,
The method comprises:
Determining a plurality of Vt distribution widths using the sensed Vts, wherein each Vt distribution width corresponds to a respective one of the plurality of states; And
And determining the plurality of voltages using the Vt distribution widths.
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A method of operating a memory device,
Sensing a state of a plurality of memory cells using a first voltage;
Performing an error correction operation on the sensed state; And
Sensing a state of the plurality of memory cells using a second voltage if the error correction operation fails;
Sensing threshold voltages (Vt) of each of the plurality of memory cells;
Determining a plurality of voltages for respectively sensing a corresponding one of a plurality of states associated with the plurality of memory cells using the sensed V ts, each determined voltage sensing each one of the plurality of states For -; And
Outputting the detected Vts and the determined plurality of voltages to an error correction code (ECC) decoder
≪ / RTI >
15. The method of claim 14,
The method comprises:
Performing an error correction operation on the sensed state using the second voltage; And
Sensing a state of the plurality of memory cells using a third voltage if the error correction operation for the state sensed using the second voltage fails.
15. The method of claim 14,
Wherein the first voltage is a predetermined voltage.
The method according to any one of claims 14 to 16,
Wherein the first voltage is a voltage that causes the error correction operation to succeed.
18. The method of claim 17,
The method includes determining a voltage that will cause the error correction operation to be successful by using a plurality of memory cells programmed to a particular state.
18. The method of claim 17,
The method includes determining a voltage that will cause the error correcting operation to be successful by using a plurality of programming and sensing operations previously performed on the plurality of memory cells.
15. The method of claim 14,
Wherein the error correction operation fails if the plurality of errors associated with the state sensed using the first voltage exceeds a correction capability of the error correction code (ECC) decoder.
15. The method of claim 14,
The method
Determining the first voltage using a plurality of memory cells programmed to the first state; And
And using the plurality of memory cells programmed to the second state to determine the second voltage.
15. The method of claim 14,
The method
And determining the first voltage and the second voltage using a plurality of programming and sensing operations previously performed on the plurality of memory cells.
13. A memory device comprising:
An array of memory cells; And
A control circuit having a sensing circuit coupled to the array,
The sensing circuit is configured to sense threshold voltages (Vt) of each of the memory cells,
Wherein the control circuit is operable to determine a plurality of voltages for respectively sensing a corresponding one of a plurality of states associated with the memory cells using the sensed V ts and to sense the sensed V ts and the determined plurality of voltages, Code (ECC) decoder,
Each determined voltage being for sensing a respective one of the plurality of states.
24. The method of claim 23,
Wherein the sensing circuit is configured to sense the state of the memory cells using the determined voltages.
23. The method according to any one of claims 23 to 24,
Wherein the array comprises only data cells.
24. The method of claim 23,
The detected Vts include a plurality of average Vt,
Wherein the control circuit is configured to determine the plurality of voltages using the average Vt.
24. The method of claim 23,
The detected Vts include a plurality of Vt distributions,
Wherein the control circuit is configured to determine the plurality of voltages using the Vt distributions.
24. The method of claim 23,
The sensed V ts include a plurality of V t distribution widths,
Wherein the control circuit is configured to determine the plurality of voltages using the Vt distribution widths.
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