CN104282339B

CN104282339B - Read voltage setting method, control circuit and memorizer memory devices

Info

Publication number: CN104282339B
Application number: CN201310284758.8A
Authority: CN
Inventors: 林纬; 许祐诚; 林小东; 吴宗霖; 郑国义
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2013-07-08
Filing date: 2013-07-08
Publication date: 2018-12-14
Anticipated expiration: 2033-07-08
Also published as: CN104282339A

Abstract

The present invention provides a kind of reading voltage setting method, control circuit and memorizer memory devices.Method includes: to read the detection data that is stored in the storage unit of wordline to obtain corresponding critical voltage distribution, and be distributed according to this critical voltage to judge to correspond to the default reading voltage of this wordline；Bestow according to it is default read voltage multiple detections reading voltages obtained so far wordline to read multiple detection page datas；And according to the minimal error bit number among the number of error bits of these detection page datas, determine that voltage is read in the optimization of this corresponding wordline.This method further includes that calculation optimization reads reading voltage change of the voltage with the default difference read between voltage as this corresponding wordline；And the reading voltage change of this corresponding bit line is recorded in reading table again.

Description

Read voltage setting method, control circuit and memorizer memory devices

Technical field

The invention relates to a kind of reading voltage setting method, control circuit and memorizer memory devices.

Background technique

Digital camera, mobile phone and MP3 are very rapid in growth over the years, so that demand of the consumer to storage medium Also rapidly increase.Since type nonvolatile (rewritable non-volatile memory) has data Non-volatile, power saving, it is small in size, without the characteristics such as mechanical structure, read or write speed be fast, be most suitable for portable electronic product, such as pen Remember this computer.Solid state hard disk is exactly a kind of storage device using flash memory as storage medium.Therefore, flash memory industry becomes electricity in recent years A ring quite popular in sub- industry.

Fig. 1 is the schematic diagram of the flash element according to depicted in the prior art.

Fig. 1 is please referred to, flash element 1 includes the electric charge capture layer (charge traping layer) for stored electrons 2, it is situated between for applying alive control grid (Control Gate) 3, tunneling oxide layer (Tunnel Oxide) 4 and inter polysilicon Electric layer (Interpoly Dielectric) 5.It, can be by the way that electron injection charge be mended when flash element 1 to be write data to Layer 2 is caught to change the critical voltage of flash element 1, thus defines the high low state of number of flash element 1, and realizes storage data Function.Here, injection electronics to the process that charge benefit catches layer 2 is known as sequencing.Conversely, when being intended to remove stored data When, it is removed by catching in layer 2 institute's injected electrons from charge benefit, then before flash element 1 can be made to reply not to be programmed State.

However, in process of production, the critical voltage distributions shift of flash element may be made because of the variation of processing procedure, So that the storing state of flash element 1 possibly can not be correctly identified.

Summary of the invention

The present invention provides a kind of reading voltage setting method and control circuit and the memory storage dress using the method It sets, it can be according to the critical voltage profile set reading voltage change appropriate of storage unit, to correctly identify storage The storing state of unit.

Exemplary embodiment of the present invention proposes a kind of reading voltage setting method, is used for type nonvolatile mould Block, wherein this reproducible nonvolatile memorizer module has multiple storage units, a plurality of wordline and multiple bit lines, Mei Yicun A wherein bit line for the wherein wordline and these bit lines of storage unit and these wordline is electrically connected, each storage unit Multiple bit datas can be stored, each bit data can be identified as first state or the second state according to a voltage.This reading Voltage setting method includes: in the multiple storage units for being connected the first wordline among Data programming to these wordline； The data being stored in the storage unit of the first wordline are read to divide to obtain the critical voltage of the storage unit of corresponding first wordline Cloth；And judge that the first of corresponding first wordline presets according to the peak value of the critical voltage of the storage unit of the first wordline distribution Read voltage.

In one example of the present invention embodiment, above-mentioned reading voltage setting method, which further includes that adjustment first is default, reads electricity Pressure reads voltage to obtain multiple first detections；It is more to read to the first wordline respectively to bestow these first detection reading voltages A first page data；According to the error bit of this detection data every one first page data corresponding with these first page data acquisitions Number；And it according to the minimal error bit number among the number of error bits of these the first page datas, is read from these first detections Voltage is read in the first optimization that corresponding first wordline is obtained among voltage.This reading voltage setting method further includes that calculating first is excellent Change the first reading voltage change for reading voltage with the first default difference read between voltage as corresponding first wordline；With And the first of corresponding first wordline is recorded in reading table again and reads voltage change.

In one example of the present invention embodiment, above-mentioned reading is stored in the data in the storage unit of the first wordline to obtain The step of taking the critical voltage distribution of the storage unit of corresponding first wordline includes: to bestow multiple scanning voltages to the first wordline, To read multiple scanning bit datas of corresponding each scanning voltage from the storage unit for being connected to the first wordline；Respectively count Calculate the multiple first states for being identified as the bit data of first state among the scanning bit data of these corresponding scanning voltages Bit data incrementss；And first is obtained according to the first state bit data incrementss for respectively corresponding to these scanning voltages The critical voltage of the storage unit of wordline is distributed.

In one example of the present invention embodiment, the peak of the critical voltage distribution of the above-mentioned storage unit according to the first wordline Value includes: the peak value searched in critical voltage distribution come the first default the step of reading voltage for judging corresponding first wordline；With And according to corresponded among the peak value and these scanning voltages in critical voltage is distributed this peak value scanning voltage obtain relative to The first of corresponding first wordline presets the voltage variety for reading voltage and reads according to this voltage variety identification first is default Voltage is taken, wherein this voltage variety is plus the first default scanning voltage for reading voltage and being equal to this corresponding peak value.

In one example of the present invention embodiment, above-mentioned reading voltage setting method, further includes: use the first default reading Voltage reads multiple bit datas from the storage unit of the first wordline；Judgement is using this first default voltage that reads from the first word The bit data read in the storage unit of line whether can according to corresponding error-correcting code come error correction to obtain the second number of pages According to；And when the bit data for using the first default reading voltage to read from the storage unit of the first wordline can not be according to correspondence When error-correcting code is come by error correction to obtain the second page data, the default reading of voltage change adjustment first is read using first Voltage is taken to obtain the first new reading voltage and bestow the first new reading voltage to the first wordline to obtain the second page data.

In one example of the present invention embodiment, above-mentioned reading voltage setting method further include: according to depositing for the first wordline The critical voltage of storage unit is distributed to judge that the correspond to the first wordline second default reading voltage and third preset reading voltage；It adjusts Whole second default reads voltage to obtain multiple second detections and read voltages and adjust third default to read voltage more to obtain Voltage is read in a third detection；It bestows these second detection reading voltages and detects reading voltage to the first wordline to read with third Multiple third page datas；The number of error bits of each third page data is obtained according to detection data and these third page datas；Root According to the minimal error bit number among the number of error bits of third page data, voltage and these thirds are read from these second detections The second optimization that corresponding first wordline is obtained among detection reading voltage reads voltage and reads voltage with third optimization；Calculate second Optimization reads voltage and reads voltage adjustment as the second of corresponding first wordline with the second default difference read between voltage Value；The difference that third optimization is read between voltage and the default reading voltage of third is calculated to read as the third of corresponding first wordline Voltage change；And the second reading voltage change of corresponding first wordline of record and third read voltage tune in reading table again Whole value.

Exemplary embodiment of the present invention proposes a kind of reading voltage setting method, is used for type nonvolatile mould Block, wherein this reproducible nonvolatile memorizer module has multiple storage units, a plurality of wordline and multiple bit lines, Mei Yicun A wherein bit line for the wherein wordline and these bit lines of storage unit and these wordline is electrically connected, each storage unit Multiple bit datas can be stored, each bit data can be identified as first state or the second state according to a voltage.This reading Voltage setting method includes: in the multiple storage units for being connected the first wordline among Data programming to these wordline； The the first default reading voltage for adjusting corresponding first wordline reads voltage to obtain multiple first detections；Respectively bestow these One detection reads voltage and reads multiple first page datas to the first wordline；It is obtained according to this detection data and these first page datas Take the number of error bits of corresponding every one first page data；And according to the minimum among the number of error bits of these the first page datas Voltage is read in number of error bits, the first optimization for reading corresponding first wordline of acquisition among voltage from these first detections.This reading Taking voltage setting method further includes calculating the first optimization to read voltage with the first default difference read between voltage as corresponding The first of first wordline reads voltage change；And the first of corresponding first wordline is recorded in reading table again and reads voltage adjustment Value.

In one example of the present invention embodiment, above-mentioned reading voltage setting method further include: adjust corresponding first wordline Second it is default read voltage and read voltages and adjust the third of corresponding first wordline to obtain multiple second detections default read Voltage is taken to obtain multiple third detections and read voltage；It bestows these second detections and reads voltage and third detection reading voltage extremely First wordline is to read multiple third page datas；Each third page data is obtained according to above-mentioned data and these third page datas Number of error bits；According to the minimal error bit number among the number of error bits of third page data, read from these second detections Voltage is read in second optimization of voltage the first wordline corresponding with acquisition among these thirds detection reading voltage and third optimizes reading Take voltage；It calculates the second optimization and reads the of voltage and the second default difference read between voltage as corresponding first wordline Two read voltage change；It calculates the difference that third optimization is read between voltage and the default reading voltage of third and is used as corresponding first The third of wordline reads voltage change；And recorded in reading table again the second of corresponding first wordline read voltage change with Third reads voltage change.

Exemplary embodiment of the present invention proposes a kind of control circuit, for accessing reproducible nonvolatile memorizer module. This control circuit includes: interface and memory management circuitry.Interface is for electrically connecting to this type nonvolatile Module, wherein this reproducible nonvolatile memorizer module has multiple storage units, a plurality of wordline and multiple bit lines, each A wherein bit line for the wherein wordline and these bit lines of storage unit and these wordline is electrically connected, and each storage is single Member can store multiple bit datas, and each bit data can be identified as first state or the second state according to a voltage.Storage Device management circuit is electrically connected to above-mentioned interface and to by the first company of wordline institute among Data programming to these wordline In the multiple storage units connect.Come in addition, memory management circuitry reads the data being stored in the storage unit of the first wordline Obtain the critical voltage distribution of the storage unit of corresponding first wordline and the critical voltage of the storage unit according to the first wordline The peak value of distribution first default reads voltage judge corresponding first wordline.

In one example of the present invention embodiment, the above-mentioned default voltage that reads of memory management circuitry adjustment first is to obtain Voltage is read in multiple first detections, is respectively bestowed these first detections and is read voltage to the first wordline to read multiple first pages Data, according to the number of error bits of this detection data and these the first corresponding every one first page datas of detection page data acquisitions, with And according to the minimal error bit number among the number of error bits of these the first page datas, from these first detections read voltages it Voltage is read in middle the first optimization for obtaining corresponding first wordline.Furthermore memory management circuitry calculates the first optimization and reads voltage Voltage change is read as the first of corresponding first wordline with the first default difference read between voltage, and in stressed table Middle the first reading voltage change for recording corresponding first wordline.

In one example of the present invention embodiment, the data in the storage unit that above-mentioned reading is stored in the first wordline are come It obtains in the operation of critical voltage distribution of the storage unit of corresponding first wordline, memory management circuitry bestows multiple scannings Voltage is to the first wordline, to read multiple scanning ratios of corresponding each scanning voltage from the storage unit for being connected to the first wordline Special data.It is identified among the scanning bit data for corresponding to these scanning voltages in addition, memory management circuitry respectively calculates For multiple first state bit data incrementss of the bit data of first state, and according to respectively corresponding to these scanning electricity The first state bit data incrementss of pressure obtain the critical voltage distribution of the storage unit of the first wordline.

In one example of the present invention embodiment, it is distributed in the critical voltage of the above-mentioned storage unit according to the first wordline Peak value is come in the operation for the first default reading voltage for judging corresponding first wordline, memory management circuitry searches critical voltage point Peak value in cloth is obtained according to the scanning voltage for corresponding to this peak value among the peak value and these scanning voltages in critical voltage is distributed Take the first default voltage variety for reading voltage relative to corresponding first wordline, and according to this voltage variety identification the One default reading voltage, wherein this voltage variety is equal to the scanning voltage for corresponding to this peak value plus the first default reading voltage.

In one example of the present invention embodiment, above-mentioned memory management circuitry is using the first default voltage that reads from first Multiple bit datas are read in the storage unit of wordline, judge to use this first default reading storage list of the voltage from the first wordline The bit data read in member whether can according to corresponding error-correcting code come error correction to obtain the second page data, and when making It can not be according to corresponding error-correcting code with the bit data that the first default reading voltage is read from the storage unit of the first wordline When come by error correction to obtain the second page data, the default voltage that reads of voltage change adjustment first is read to obtain using first It takes the first new reading voltage and bestows the first new reading voltage to the first wordline to obtain the second page data.

In one example of the present invention embodiment, above-mentioned memory management circuitry is also to the storage list according to the first wordline The critical voltage distribution of member come judge corresponding first wordline second it is default read voltage and third is default reads voltage, adjustment the Two default read voltages to obtain multiple second detections and read voltages and adjust that third is default to read voltage to obtain multiple the Voltage is read in three detections.In addition, memory management circuitry is also to bestow, voltage is read in these second detections and third detection is read It takes voltage to the first wordline to read multiple third page datas, obtains each third according to above-mentioned data and these third page datas The number of error bits of page data, and according to the minimal error bit number among the number of error bits of third page data, from these Voltage is read in the second optimization that voltage the first wordline corresponding with acquisition among these thirds detection reading voltage is read in second detection Optimize with third and reads voltage.Furthermore memory management circuitry also reads voltage and the second default reading to calculate the second optimization Take a difference between voltage to read voltage change as the second of corresponding first wordline, calculate third optimization read voltage with The default difference read between voltage of third reads voltage change as the third of corresponding first wordline, and in reading table again It records the second of corresponding first wordline and reads voltage change and third reading voltage change

Exemplary embodiment of the present invention proposes a kind of memorizer memory devices comprising connector, duplicative are non-volatile Memory module and Memory Controller.Connector is electrically connected to host system.Type nonvolatile Module has multiple storage units, a plurality of wordline and multiple bit lines, a wherein wordline for each storage unit and these wordline And a wherein bit line for these bit lines is electrically connected, each storage unit can store multiple bit datas, each bit number According to first state or the second state can be identified as according to a voltage.Memory Controller is electrically connected to connector and can make carbon copies Formula non-volatile memory module, and multiple deposited to connected the first wordline among Data programming to these wordline In storage unit.In addition, Memory Controller, which reads the data being stored in the storage unit of the first wordline, corresponds to first to obtain The critical voltage of the storage unit of wordline be distributed and according to the peak value of the critical voltage of the storage unit of the first wordline distribution come Judge the first default reading voltage of corresponding first wordline.

In one example of the present invention embodiment, the default reading voltage of above-mentioned Memory Controller adjustment first is more to obtain Voltage is read in a first detection, is respectively bestowed these first detections and is read voltage to the first wordline to read multiple first numbers of pages According to according to the number of error bits of this data every one first page data corresponding with these first page data acquisitions, and according to these Minimal error bit number among the number of error bits of first page data reads from these first detections and obtains correspondence among voltage Voltage is read in first optimization of the first wordline.Furthermore Memory Controller calculates the first optimization and reads voltage and the first default reading Difference between voltage is taken to read voltage change as the first of corresponding first wordline, and record corresponding the in reading table again The first of one wordline reads voltage change.

In one example of the present invention embodiment, the data in the storage unit that above-mentioned reading is stored in the first wordline are come It obtains in the operation of critical voltage distribution of the storage unit of corresponding first wordline, Memory Controller bestows multiple scanning electricity It is depressed into the first wordline, to read multiple scanning bits of corresponding each scanning voltage from the storage unit for being connected to the first wordline Data.In addition, Memory Controller, which respectively calculates, is identified as the among the scanning bit datas of these corresponding scanning voltages Multiple first state bit data incrementss of the bit data of one state, and according to respectively corresponding to these scanning voltages First state bit data incrementss obtain the critical voltage distribution of the storage unit of the first wordline.

In one example of the present invention embodiment, it is distributed in the critical voltage of the above-mentioned storage unit according to the first wordline Peak value is come in the operation for the first default reading voltage for judging corresponding first wordline, Memory Controller searches critical voltage distribution In peak value, according to corresponded among the peak value and these scanning voltages in critical voltage is distributed this peak value scanning voltage obtain Relative to the first default voltage variety for reading voltage of corresponding first wordline, and according to this voltage variety identification first Default to read voltage, wherein this voltage variety is plus the first default scanning voltage for reading voltage and being equal to this corresponding peak value.

In one example of the present invention embodiment, above-mentioned Memory Controller is using the first default voltage that reads from the first word Multiple bit datas are read in the storage unit of line, judge to use this first default reading storage unit of the voltage from the first wordline The bit data of middle reading whether can according to corresponding error-correcting code come error correction to obtain the second page data, and when using First it is default read bit data that voltage is read from the storage unit of the first wordline can not according to corresponding error-correcting code come When by error correction to obtain the second page data, the default voltage that reads of voltage change adjustment first is read to obtain using first First newly reads voltage and bestows the first new reading voltage to the first wordline to obtain the second page data.

In one example of the present invention embodiment, above-mentioned Memory Controller is also to the storage unit according to the first wordline Critical voltage distribution second default read voltage and third is default reads voltage, adjustment second judge corresponding first wordline It is default to read voltage to obtain multiple second detection reading voltages and adjust the default voltage that reads of third to obtain multiple thirds Voltage is read in detection.In addition, Memory Controller is also to bestow, voltage is read in these second detections and electricity is read in third detection The first wordline is depressed into read multiple third page datas, obtains each third number of pages according to above-mentioned data and these third page datas According to number of error bits, and according to the minimal error bit number among the number of error bits of third page data, from these second Detection, which reads the detection of voltage and these thirds and reads the second of corresponding first wordline of acquisitions among voltage, optimizes reading voltage and the Voltage is read in three optimizations.Furthermore Memory Controller also reads voltage and the second default reading voltage to calculate the second optimization Between a difference read voltage change as the second of corresponding first wordline, calculate that voltage is read in third optimization and third is pre- If the difference read between voltage reads voltage change, and the record pair in reading table again as the third of corresponding first wordline It answers the second of the first wordline to read voltage change and third reads voltage change

Based on above-mentioned, the reading voltage setting method, control circuit and memorizer memory devices of this exemplary embodiment can be with Voltage value is adjusted to adjust default reading voltage, thus correctly using reading appropriate according to the distribution of the critical voltage of storage unit Ground identification has the storing state of the storage unit of the reproducible nonvolatile memorizer module of processing procedure defect.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.

Detailed description of the invention

Fig. 1 is the schematic diagram of the flash element according to depicted in the prior art；

Fig. 2 is the schematic diagram of the host system according to depicted in an exemplary embodiment and memorizer memory devices；

Fig. 3 is the signal of the computer according to depicted in an exemplary embodiment, input/output device and memorizer memory devices Figure；

Fig. 4 is the schematic diagram of the host system according to depicted in an exemplary embodiment and memorizer memory devices；

Fig. 5 is the schematic block diagram of the memorizer memory devices according to depicted in the first exemplary embodiment；.

Fig. 6 is the schematic block diagram of the reproducible nonvolatile memorizer module according to depicted in an exemplary embodiment；

Fig. 7 is the schematic diagram of the memory cell array according to depicted in an exemplary embodiment；

Fig. 8 is grid corresponding to the write-in data that are stored in memory cell array according to depicted in an exemplary embodiment The statistics distribution diagram of voltage；

Fig. 9 is the schematic diagram of the sequencing storage unit according to depicted in an exemplary embodiment；

Figure 10 is the schematic diagram that data are read in the slave storage unit according to depicted in an exemplary embodiment；

Figure 11 is the schematic diagram that data are read in the slave storage unit according to depicted in another exemplary embodiment；

Figure 12 is that management reproducible nonvolatile memorizer module depicted in exemplary embodiment is shown according to the present invention It is intended to；

Figure 13 is the schematic block diagram of the Memory Controller according to depicted in an exemplary embodiment；

Figure 14 is according to depicted in an exemplary embodiment when the multiple sequencing of storage unit and to be stored in storage after erasing single The statistics distribution diagram of grid voltage corresponding to write-in data in element array；

Figure 15 is confirmation reproducible nonvolatile memorizer module depicted in an exemplary embodiment according to the present invention The default example schematic for reading voltage；

Figure 16~18 are confirmation type nonvolatile moulds depicted in an exemplary embodiment according to the present invention The example schematic of voltage is read in the optimization of block；

Figure 19 is the flow chart for reading voltage setting method depicted in an exemplary embodiment according to the present invention；

Figure 20 is the flow chart of the method for reading data of physical page under the reading according to depicted in this exemplary embodiment.

Description of symbols:

1: flash element；

2: charge benefit catches layer；

3: control grid；

4: tunneling oxide layer；

5: dielectric layers between polycrystal silicon；

1000: host system；

1100: computer；

1102: microprocessor；

1104: random access memory；

1106: input/output device；

1108: system bus；

1110: data transmission interface；

1202: mouse；

1204: keyboard；

1206: display；

1208: printer；

1212: portable disk；

1214: storage card；

1216: solid state hard disk；

1310: digital camera；

1312:SD card；

1314:MMC card；

1316: memory stick；

1318:CF card；

1320: embedded storage device；

100: memorizer memory devices；

102: connector；

104: Memory Controller；

106: reproducible nonvolatile memorizer module；

2202: memory cell array；

2204: Word line control circuit；

2206: bit line control circuit；

2208: row decoder；

2210: data input/output buffer；

2212: control circuit；

702: storage unit；

704: bit line；

706: wordline；

708: source electrode line；

712: select grid drain electrode transistor；

714: select grid source electrode transistor；

VA: the first reads voltage；

VB: the second reads voltage；

VC: third reads voltage；

VD: the four reads voltage；

VE: the five reads voltage；

VF: the six reads voltage；

VG: the seven reads voltage；

P: peak value；

VP: the voltage of corresponding peak value；

VO: the first optimizes voltage；

VTEST1, VTEST2, VTEST3: voltage is read in detection；

400 (0)~400 (N): physical blocks；

202: memory management circuitry；

204: host interface；

206: memory interface；

208: error checking and correcting circuit；

210: buffer storage；

212: electric power management circuit；

282: storage unit；

284: soft value acquiring unit；

1601,1603,1605,1701,1703,1801,1803,1805: block

S1901, S1903, S1905, S1907, S1909, S1911: the step of voltage, is read in setting；

S2001, S2003, S2005, S2007, S2009, S2011, S2013: the step of reading data.

Specific embodiment

In general, memorizer memory devices (also referred to as, memory storage system) include duplicative non-volatile memories Device module and controller (also referred to as, control circuit).Being commonly stored device storage device is used together with host system, so that host System can write data into memorizer memory devices or read from memorizer memory devices data.

Fig. 2 is the host system according to depicted in an exemplary embodiment and memorizer memory devices.

Referring to figure 2., host system 1000 generally comprises computer 1100 and input/output (input/output, I/O) is filled Set 1106.Computer 1100 include microprocessor 1102, random access memory (random access memory, RAM) 1104, System bus 1108 and data transmission interface 1110.Input/output device 1106 include the mouse 1202 such as Fig. 3, keyboard 1204, Display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device 1106 of device shown in Fig. 3, defeated Enter/output device 1106 can further include other devices.

In embodiments of the present invention, memorizer memory devices 100 are through data transmission interface 1110 and host system 1000 other elements are electrically connected.Pass through microprocessor 1102, random access memory 1104 and input/output device 1106 Operation can write data into memorizer memory devices 100 or read data from memorizer memory devices 100.For example, depositing Reservoir storage device 100 can be portable disk 1212 as shown in Figure 3, storage card 1214 or solid state hard disk (Solid State Drive, SSD) 1216 equal type nonvolatile storage devices.

In general, host system 1000 is that can substantially cooperate with memorizer memory devices 100 to store appointing for data Meaning system.Although host system 1000 is explained with computer system, however, of the invention another in this exemplary embodiment Host system 1000 can be digital camera, video camera, communication device, audio player or video playing in one exemplary embodiment The systems such as device.For example, when host system is digital camera (video camera) 1310, type nonvolatile storage dress It sets then as its used SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded Storage device 1320 (as shown in Figure 4).Embedded storage device 1320 include embedded multimedium card (Embedded MMC, eMMC).It is noted that embedded multimedium card is directly electrically connected on the substrate of host system.

Fig. 5 is the schematic block diagram of the memorizer memory devices according to depicted in the first exemplary embodiment.

Referring to figure 5., memorizer memory devices 100 include that connector 102, Memory Controller 104 and duplicative are non- Volatile 106.

In this exemplary embodiment, connector 102 be compatible to universal serial bus (Universal Serial Bus, USB) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, and connector 102 is also possible to meet advanced attachment arranged side by side (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral part Connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, secure digital (Secure Digital, SD) interface standard, the advanced attachment of sequence (Serial Advanced Technology Attachment, SATA) standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multimedium storage Deposit card (Multi Media Card, MMC) interface standard, down enters formula multimedium memory card (Embedded Multimedia Card, eMMC) interface standard, Common Flash Memory (Universal Flash Storage, UFS) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.

Memory Controller 104 refers to execute multiple logic gates with hardware pattern or the realization of firmware pattern or control Enable, and carried out in reproducible nonvolatile memorizer module 106 according to the instruction of host system 1000 data write-in, It the operation such as reads and erases.

Reproducible nonvolatile memorizer module 106 is electrically connected to Memory Controller 104, and to store The data that host system 1000 is written.Reproducible nonvolatile memorizer module 106 can be multi-level cell memory (Multi Level Cell, MLC) NAND-type flash memory module is (that is, can store the flash memory of 2 bit datas in a storage unit Module), Complex Order storage unit (Trinary Level Cell, TLC) NAND-type flash memory module is (that is, in a storage unit The flash memory module of 3 bit datas can be stored), other flash memory modules or other memory modules with the same characteristics.

Fig. 6 is the schematic block diagram of the reproducible nonvolatile memorizer module according to depicted in an exemplary embodiment.

Fig. 6 is please referred to, reproducible nonvolatile memorizer module 106 includes memory cell array 2202, wordline control Circuit 2204, bit line control circuit 2206,2208, data input/output buffer row decoder (column decoder) 2210 with control circuit 2212.

Memory cell array 2202 include to store multiple storage units 702 of data, it is multiple selection delete drain electrode (select gate drain, SGD) transistor 712 and multiple select grid source electrodes (select gate source, SGS) crystal Pipe 714 and connect the multiple bit lines 704 of these storage units, a plurality of wordline 706, with common source line 708 (such as Fig. 7 institute Show).Storage unit 702 is configured on the crosspoint of bit line 704 and wordline 706 with array manner.When from Memory Controller 104 receive write instruction or read data when, control circuit 2212 can control Word line control circuit 2204, bit line control circuit 2206, row decoder 2208, data input/output buffer 2210 are to write data to memory cell array 2202 or from storage Data are read in cell array 2202, wherein Word line control circuit 2204 is to control the voltage bestowed to wordline 706, bit line control Circuit 2206 processed is to control the voltage bestowed to bit line 704, and row decoder 2208 is according to the decoding column address in instruction to select Corresponding bit line is selected, and data input/output buffer 2210 is configured to temporarily store data.

Storage unit in reproducible nonvolatile memorizer module 106 is to represent more bits with a variety of grid voltages (bits) data.Specifically, each storage unit of memory cell array 2202 has multiple states, and these states It is to be distinguished with multiple reading voltages.

Fig. 8 is grid corresponding to the write-in data that are stored in memory cell array according to depicted in an exemplary embodiment The statistics distribution diagram of voltage.

Fig. 8 is please referred to, by taking MLC NAND-type flash memory as an example, the grid voltage in each storage unit can be default according to first It reads voltage VA, the second default reading voltage VB and the default reading voltage VC of third and divides into 4 kinds of storing states, and these Storing state respectively represents " 11 ", " 10 ", " 00 " and " 01 ".In other words, each storing state includes minimum effective bit (Least Significant Bit, LSB) and highest significant bit (Most Significant Bit, MSB).In this model In example embodiment, the value for the 1st bit counted in storing state (that is, " 11 ", " 10 ", " 00 " and " 01 ") from left side is LSB, And the value for the 2nd bit counted from left side is MSB.Therefore, in the first exemplary embodiment, each storage unit can store 2 A bit data.It will be appreciated that grid voltage depicted in Fig. 8 and its storing state to should be only an example.? In another exemplary embodiment of the present invention, grid voltage is corresponding with storing state can also be with grid voltage is bigger and with " 11 ", " 10 ", " 01 " and " 00 " arrange.Alternatively, storing state corresponding to grid voltage can also be for the progress of physical holding of the stock value Value after mapping or reverse phase, in addition, in another example in example, the value that also can define the 1st bit counted from left side is MSB, and the value for the 2nd bit counted from left side is LSB.

In the example that each storage unit can store 2 bit datas, the storage unit in same wordline can constitute 2 The storage space of a physical page (that is, lower physical page and upper physical page).That is, the LSB of each storage unit is Corresponding lower physical page, and the MSB of each storage unit is corresponding upper physical page.In addition, in memory cell array 2202 In several physical pages can constitute a physical blocks, and physical blocks are to execute the minimum unit for operation of erasing.That is, every One physical blocks contain the storage unit of minimal amount being erased together.

The data write-in (or being sequencing) of the storage unit of memory cell array 2202 is to utilize to bestow a particular end The voltage of point, e.g. control grid voltage catch the amount of electrons of layer to change the benefit of the charge in grid, thus change storage The on state in the channel of unit, different storing states is presented.For example, page data is 1 instantly and upper page data is 1 When, control circuit 2212 can control Word line control circuit 2204 and not change grid voltage in storage unit, and by storage unit Storing state remain " 11 ".Instantly page data is 1 and when upper page data is 0, and Word line control circuit 2204 can controlled Change the grid voltage in storage unit under the control of circuit 2212 processed, and the storing state of storage unit is changed into " 10 ". Instantly page data is 0 and when upper page data is 0, and Word line control circuit 2204 can change under the control of control circuit 2212 Grid voltage in storage unit, and the storing state of storage unit is changed into " 00 ".Also, instantly page data be 0 and When upper page data is 1, Word line control circuit 2204 can change the grid in storage unit under the control of control circuit 2212 Voltage, and the storing state of storage unit is changed into " 01 ".

Fig. 9 is the schematic diagram of the sequencing storage unit according to depicted in an exemplary embodiment.

Fig. 9 is please referred to, in this exemplary embodiment, the sequencing of storage unit is to be written/verify critical electricity through pulse Pressure method is completed.Specifically, when being intended to write data into storage unit, Memory Controller 104 can set and be originally written into Voltage and write-in voltage pulse time, and indicate the control circuit 2212 of reproducible nonvolatile memorizer module 106 Carry out sequencing storage unit using set being originally written into voltage and voltage pulse time is written, to carry out writing for data Enter.Later, Memory Controller 104 will use verifying voltage to verify to storage unit, whether to judge storage unit It has been in correct storing state.If storage unit is not programmed into correct storing state, Memory Controller 104 It indicates control circuit 2212 and an incremental step pulse program (Incremental-step- is added with the write-in voltage bestowed at present Pulse programming, ISPP) adjusted value is as new write-in voltage (being also referred to as repeatedly written voltage) and according to new Write-in voltage and write-in voltage pulse time carry out sequencing storage unit again.Conversely, if storage unit has been programmed into When correct storing state, then it represents that data have been correctly written to storage unit.For example, being originally written into voltage can be set For 16 volts (Voltage, V), voltage pulse time, which is written, can be set to 18 microseconds (microseconds, μ s) and increment Step pulse formula adjusted value is set to 0.6V, however, the present invention is not limited thereto.

Figure 10 is the schematic diagram that data are read in the slave storage unit according to depicted in an exemplary embodiment, is with MLC For NAND-type flash memory.

Figure 10 is please referred to, the read operation of the storage unit of memory cell array 2202 is to read voltage in control by bestowing Door (control gate) processed passes through channel (path of the storage unit to be electrically connected bit line and source electrode line, the example of storage unit Path of the cell source in this way between draining) on state, carry out the data of recognition memory cell storage.Reading nextpage In the operation of data, Word line control circuit 2204 will use the first default voltage VA that reads and reading voltage be used as to bestow to storage Unit and the value that judges lower page of data whether is connected according to the channel of storage unit with corresponding arithmetic expression (1):

LSB=(VA) Lower_pre1 (1)

Wherein (VA) Lower_pre1 is indicated through the 1st nextpage verifying bestowing the first default reading voltage VA and obtaining Value.

For example, the channel of storage unit will not when the first default grid voltage for reading voltage VA less than storage unit The 1st nextpage validation value of simultaneously output valve " 0 " is connected, it is 0 that thus LSB, which can be identified in first state,.For example, it is default to work as first When reading grid voltage of the voltage VA greater than storage unit, the channel of storage unit can be connected and the 1st nextpage of output valve " 1 " is tested Card value, this LSB can be identified in the second state as a result,.Here, first state is identified as " 0 " and the second state is known It Wei " 1 ".That is, can pass through first with the grid voltage that LSB is 0 is presented the grid voltage that LSB is 1 is presented It is default to read voltage VA and be distinguished.

In the operation for reading upper page data, Word line control circuit 2204 can respectively be preset using second and read voltage VB It bestows to storage unit and whether is led according to the channel of storage unit as voltage is read with the default reading voltage VC of third The logical value that upper page data is judged with corresponding arithmetic expression (2):

MSB=((VB) Upper_pre2) xor (~(VC) Upper_pre1) (2)

Wherein (VC) Upper_pre1, which indicates to penetrate, bestows page verifying on default the 1st for reading voltage VC and obtaining of third Value, and (VB) Upper_pre2 is indicated to penetrate and is bestowed page validation value on the second default the 2 for reading voltage VB and obtaining, wherein Symbol "~" represents reverse phase.In addition, reading grid of the voltage VC less than storage unit when third is default in this exemplary embodiment When voltage, the channel of storage unit does not turn on and page validation value ((VC) Upper_pre1) on the 1st of output valve ' 0' the, when the Two is default when reading voltage VB and being less than the grid voltage of storage unit, and the channel of storage unit does not turn on and output valve ' 0' Page validation value ((VB) Upper_pre2) on 2nd.

Therefore, according to arithmetic expression (2), when the default reading voltage VB of the default reading voltage VC and second of third is smaller than stored When the grid voltage of unit, in the case where bestowing third default reading voltage VC, the channel of storage unit does not turn on simultaneously output valve ' 0' The 1st on page validation value and bestow the second default channel for reading storage unit under voltage VB do not turn on and output valve ' Page validation value on the 2nd of 0'.At this point, MSB can be identified as second state of being in, that is, " 1 ".

For example, reading that voltage VC is greater than the grid voltage of storage unit and second default to read voltage VB small when third is default When the grid voltage of storage unit, in the case where bestowing third default reading voltage VC, the channel of storage unit can be connected and export Page validation value on the 1st of value ' 1', and do not turned on and defeated bestowing the second default channel for reading storage unit under voltage VB Page validation value on the 2nd of value ' 0' out.At this point, MSB can be identified as being in first state, that is, " 0 ".

For example, reading the default grid voltage for reading voltage VB and being all greater than storage unit of voltage VC and second when third is default When, in the case where bestowing the default reading voltage VC of third, the channel of storage unit can be connected and page validation value on the 1st of output valve " 1 " the, And page validation value on the 2nd of simultaneously output valve ' 1' can be connected bestowing the second default channel for reading storage unit under voltage VB. At this point, MSB can be identified as second state of being in, that is, " 1 ".

It will be appreciated that although the present invention is explained with MLC NAND-type flash memory.However, the present invention is not limited to This, other multilayered memory unit NAND-type flash memories can also carry out the reading of data according to above-mentioned principle.

For example, each storing state includes the 1 that left side is counted by taking TLC NAND-type flash memory as an example (as shown in figure 11) Intermediate significant bit (the Center of the minimum effective bit LSB of a bit, the 2nd counted from left side bit Significant Bit, CSB) and the highest significant bit MSB of the 3rd bit counted from left side, under wherein LSB is corresponding The page, the page during CSB is corresponding, the page in MSB correspondence.In this example, the grid voltage in each storage unit can be according to One default read voltage VA, second default reads that voltage VB, third are default to be read voltage VC, the 4th default read voltage VD, the Five default reading voltage VE, the 6th default reading voltage VF and the 7th preset and read voltage VG and divide into 8 kinds of storing states (that is, " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " and " 011 ").

Figure 12 is that management reproducible nonvolatile memorizer module depicted in exemplary embodiment is shown according to the present invention It is intended to.

Figure 13 is please referred to, Memory Controller 104 (or memory management circuitry 202) can be next pair as unit of physical page The storage unit 702 of reproducible nonvolatile memorizer module 106 is carried out write operation and is come as unit of physical blocks Operation of erasing is carried out to the storage unit 702 of reproducible nonvolatile memorizer module 106.Specifically, duplicative is non- The storage unit 702 of volatile 106 can constitute multiple physical pages, and these physical pages can constitute it is multiple Physical blocks 400 (0)~400 (N).Physical blocks are the minimum unit erased.That is, each physical blocks contain minimal amount The storage unit being erased together.Physical page is the minimum unit of sequencing.That is, a physical page is write-in data Minimum unit.Each physical page generally includes data bit area and redundancy ratio special zone.Data bit area includes that multiple entities are deposited Data of the fetch bit location to store user, and redundancy ratio special zone to stocking system data (for example, control information and mistake More code).For example, the LSB of the storage unit in same wordline can constitute real under one by taking TLC nand flash memory as an example The body page；The CSB of storage unit in same wordline can constitute a middle physical page；And it is located at same wordline On the MSB of storage unit can constitute a upper physical page.

Figure 13 is the schematic block diagram of the Memory Controller according to depicted in an exemplary embodiment.It will be appreciated that The structure of Memory Controller shown in Figure 13 is only an example, and invention is not limited thereto.

Figure 13 is please referred to, Memory Controller 104 connects including memory management circuitry 202, host interface 204, memory Mouth 206 and error checking and correcting circuit 208.

Integrated operation of the memory management circuitry 202 to control Memory Controller 104.Specifically, memory pipe Managing circuit 202 has multiple control instructions, and when memorizer memory devices 100 operate, these control instructions can be performed The operation such as to carry out the write-in of data, read and erase.

In this exemplary embodiment, the control instruction of memory management circuitry 202 is realized with firmware pattern.For example, Memory management circuitry 202 has microprocessor unit (not being painted) and the read only memory (not being painted), and these controls refer to Order is programmed in the so far read only memory.When memorizer memory devices 100 operate, these control instructions can be by microprocessor Unit is executed the operation such as to carry out the write-in of data, read and erase.

In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also be with source code pattern The specific region of reproducible nonvolatile memorizer module 106 is stored in (for example, being exclusively used in storage system in memory module The system area of data) in.In addition, memory management circuitry 202 has microprocessor unit (not being painted), the read only memory (not It is painted) and random access memory (not being painted).In particular, this read only memory has driving code, and when memory controls When device 104 is enabled, microprocessor unit, which can first carry out this driving code section, will be stored in type nonvolatile Control instruction in module 106 is loaded into the random access memory of memory management circuitry 202.Later, microprocessor list Member such as can operate these control instructions to carry out the write-in of data, read and erase at the operation.

In addition, the control instruction of memory management circuitry 202 can also be with a hardware in another exemplary embodiment of the present invention Pattern is realized.For example, memory management circuitry 202 includes microcontroller, Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity Circuit is erased on road, memory reading circuitry, memory and data processing circuit is electrically connected to microcontroller.Wherein, it stores Physical blocks of the Single Component Management circuit to manage reproducible nonvolatile memorizer module 106；Memory write circuit is used It writes data into duplicative is non-volatile and deposits to assign write instruction to reproducible nonvolatile memorizer module 106 In memory modules 106；Memory reading circuitry to reproducible nonvolatile memorizer module 106 assign reading instruction with Data are read from reproducible nonvolatile memorizer module 106；Memory erases circuit to non-volatile to duplicative Property memory module 106 assign erase instruction data to be erased from reproducible nonvolatile memorizer module 106；And it counts According to processing circuit to handle be intended to be written data to reproducible nonvolatile memorizer module 106 and from duplicative it is non- The data read in volatile 106.

Host interface 204 is electrically connected to memory management circuitry 202 and to receive and identification host system 1000 instructions and data transmitted.That is, instruction and data that host system 1000 is transmitted can penetrate host interface 204 are sent to memory management circuitry 202.In this exemplary embodiment, host interface 204 is to be compatible to USB standard.So And, it should be understood that the invention is not limited thereto, and host interface 204 is also possible to be compatible to PATA standard, the mark of IEEE 1394 Standard, PCI Express standard, SD standard, SATA standard, UHS-I interface standard, UHS-II interface standard, MS standard, MMC mark Standard, eMMC interface standard, UFS interface standard, CF standard, IDE standard or other suitable data transmission standards.

Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile to access duplicative Property memory module 106.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 106 can be via depositing Memory interface 206 is converted to the 106 receptible format of institute of reproducible nonvolatile memorizer module.

Error checking and correcting circuit 208 are electrically connected to memory management circuitry 202 and to execute a mistake Correction program is to ensure the correctness of data.Specifically, when memory management circuitry 202 is from duplicative non-volatile memories When reading data in device module 106, error checking and correcting circuit 208 can execute error-correcting routine to read data. For example, error checking and correcting circuit 208 are that low-density parity corrects (Low Density in this exemplary embodiment Parity Check, LDPC) circuit, and record log likelihood ratio (Log Likelihood Ratio, LLR) value can be stored Inquiry table.When memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, error checking With correcting circuit 208 error-correcting routine can be executed according to corresponding LLR value in read data and inquiry table.Its In, it is worth noting that error checking and correcting circuit 208 can also be turbine code (Turbo in another exemplary embodiment Code) circuit.

In an exemplary embodiment of the invention, Memory Controller 104 further includes buffer storage 210 and power management electricity Road 212.

Buffer storage 210 is electrically connected to memory management circuitry 202 and is configured to temporarily store from host system 1000 data and instruction or the data from reproducible nonvolatile memorizer module 106.

Electric power management circuit 212 is electrically connected to memory management circuitry 202 and to control memory storage dress Set 100 power supply.

In general, when being intended to read data from storage unit, Memory Controller 104 (or memory management circuitry 202) reading instruction, and type nonvolatile can be assigned to reproducible nonvolatile memorizer module 106 The control circuit 2212 of module 106 can bestow default reading voltage to the wordline for being connected to the storage unit to be read, with verifying The channel storing state of storage unit.However, as described above, may be because of type nonvolatile caused by process variation The critical voltage distributions shift (as shown in the dotted line of Figure 14) of the storage unit 702 of module 106 causes default reading voltage can not Correctly identify the storing state of storage unit.

In this exemplary embodiment, in opening in card program for memorizer memory devices 100, Memory Controller 104 (or deposit Reservoir manages circuit 202) it can be by preset data (hereinafter referred to as detection data) sequencing to duplicative non-volatile memories In the storage unit that each wordline of device module 106 is connected, and the detection data that is stored in storage unit is read to obtain The critical voltage of the storage unit of corresponding each wordline is taken to be distributed.Specifically, (or the memory pipe of Memory Controller 104 Reason circuit 202) gradually incremental multiple scanning voltages can be bestowed to each wordline, to read from the storage unit for be connected to wordline Multiple scanning bit datas of corresponding each scanning voltage are taken, and calculate scanning bit acquired in input scanning voltage every time It is identified as the incrementss (hereinafter referred to as " first state bit data incrementss ") of the bit data of first state in data, and And the cumulative distribution table of the first state bit data incrementss under different scanning voltage is depicted, thus rebuild each wordline Storage unit critical voltage distribution.

For example, in the process for the critical voltage distribution for rebuilding the storage unit of certain wordline (hereinafter referred to as the first wordline) In, Memory Controller 104 (or memory management circuitry 202) can first bestow the scanning voltage of 1 unit to the first wordline, with Read the scanning bit data of the scanning voltage of this corresponding 1 unit.Then, (or the memory management circuitry of Memory Controller 104 202) scanning voltage of 2 units can be bestowed again to the first wordline, to read the scanning bit number of the scanning voltage of this corresponding 2 unit According to, and calculate compared to for scanning bit data acquired in the scanning voltage of 1 unit, in the scanning electricity with 2 units In the acquired scanning bit data of pressure, it is identified as the incrementss of the bit data of first state.Later, Memory Controller 104 (or memory management circuitries 202) can bestow the scanning voltage of 3 units to the first wordline, to read this corresponding 3 unit again The scanning bit data of scanning voltage, and calculate compared to scanning bit data acquired in the scanning voltage of 2 units It says, in scanning bit data acquired in the scanning voltage of 3 units, is identified as the increase of the bit data of first state Amount.And so on, Memory Controller 104 (or memory management circuitry 202) can input multiple scanning voltages to the in instruction After one wordline and each input scanning voltage to the first wordline of calculating after acquired first state bit data incrementss, obtain The critical voltage of the storage unit of corresponding first wordline is distributed (as shown in the dotted line of Figure 14).

Especially since the critical voltage distribution of the storage unit 702 of reproducible nonvolatile memorizer module 106 is Through deviating, therefore, in this exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) can estimate suitable Voltage is read in the optimization of the critical voltage distribution deviated.

Specifically, firstly, Memory Controller 104 (or memory management circuitry 202) can be critical according to what is rebuild Voltage's distribiuting confirms the value of the default reading voltage of reproducible nonvolatile memorizer module.

Figure 15 is confirmation reproducible nonvolatile memorizer module depicted in an exemplary embodiment according to the present invention The default example schematic for reading voltage.It will be appreciated that although the example of Figure 15 is to confirm that corresponding duplicative is non-easily The first of any wordline (hereinafter referred to as the first wordline) of the property lost memory module 106 is default to read voltage VA to explain, but The method is equally applicable to confirm that the second default reading voltage VB of corresponding first wordline, third preset and read voltage VC, the 4th Default reading voltage VD, the 5th preset and read voltage VE, the 6th default voltage VF and the 7th that reads presets reading voltage VG.

Figure 15 is please referred to, Memory Controller 104 (or memory management circuitry 202) can search rebuild critical voltage Peak value (for example, peak value P) in distribution.Then, Memory Controller 104 (or memory management circuitry 202) can indicate answer Formula non-volatile memory module 106 is write, reading voltage is preset to adjust first to execute with gradually incremental voltage variety Read instruction, when error bit (error bit) data incrementss maximum of the bit data read out, at this time the The one default voltage that reads can be consistent with scanning voltage corresponding to the peak value P searched.For example, firstly, memory controls Device 104 (or memory management circuitry 202) can indicate that reproducible nonvolatile memorizer module 106 is become with the voltage of 1 unit Change amount presets reading voltage to adjust first, and bestows to the first wordline to be read out.Then, Memory Controller 104 (or Memory management circuitry 202) it can indicate that reproducible nonvolatile memorizer module 106 is adjusted with the voltage varieties of 2 units Whole first default reading voltage, and bestow to the first wordline to be read out.And so on, until default with adjusted first When the incrementss for reading the number of error bits for the bit data that voltage is read out are maximum, Memory Controller 104 (or storage Device manages circuit 202) it will record this voltage variety Δ, and the first default reading is calculated with voltage VP corresponding to peak value P Take voltage.If for example, the first default bit number for reading voltage and being read out adjusted with the voltage variety of 10 units According to erroneous bit data incrementss be the largest, the adjusted first default peak value P for reading voltage and being with being searched Corresponding voltage VP is consistent, and when the corresponding voltage of peak value P is 67 unit, then (or the memory pipe of Memory Controller 104 Reason circuit 202) the first default voltage that reads is judged as 57 units.

After the default reading voltage of confirmation reproducible nonvolatile memorizer module, Memory Controller 104 (or deposit Reservoir management circuit 202) multiple detections reading voltages can be set according to default reading voltage to read number from storage unit According to, and determine that voltage is read in optimization according to the number of error bits in data streams read.

After confirming the first default reading voltage of corresponding first wordline, Memory Controller 104 (or memory management Circuit 202) it can indicate that reproducible nonvolatile memorizer module 106 is used according to more after the first default reading voltage trim Voltage is read in a first detection, is previously written to read from the storage unit of the first wordline to the storage unit of the first wordline In detection data in the first page data.Later, Memory Controller 104 (or memory management circuitry 202) can be by foundation First detection is read read first page data of voltage and is compared with detection data, to calculate read first page data The number of error bits being had.Also, Memory Controller 104 (or memory management circuitry 202) can be according to mistake calculated Minimal error bit number among errored bit number selects corresponding first detection to read voltage as the first optimization and reads voltage VO。

Figure 16~18 are confirmation type nonvolatile moulds depicted in an exemplary embodiment according to the present invention The example schematic of voltage is read in the optimization of block.It will be appreciated that although the example of Figure 16~18 is to estimate that correspondence can answer The first optimization for writing any wordline (hereinafter referred to as the first wordline) of formula non-volatile memory module 106 reads voltage to say It is bright, but the method is equally applicable to estimate that voltage is read in the second optimization of corresponding first wordline, voltage, the 4th are read in third optimization Voltage is read in optimization, voltage is read in the 5th optimization, voltage is read in the 6th optimization and voltage is read in the 7th optimization.

Figure 16 is please referred to, Memory Controller 104 (or memory management circuitry 202) can indicate that duplicative is non-volatile Memory module 106 is bestowed the detection adjusted based on the first default reading voltage VA and reads voltage VTEST1 to read first Page data, and calculate according to detection data to detect the error bit read in read first page data of voltage VTEST1 Number.Specifically, as can be seen from Figure 16, the storing state of the storage unit in block 1601 should be " 001 ", but be mistaken for " 101 ", and the storing state of the storage unit in block 1603 and block 1605 should be " 101 ", but be mistaken for " 001 ".

Figure 17 is please referred to, Memory Controller 104 (or memory management circuitry 202) can indicate that duplicative is non-volatile Memory module 106 is bestowed the detection adjusted based on the first default reading voltage VA and reads voltage VTEST2 to read first Page data, and calculate according to detection data to detect the error bit read in read first page data of voltage VTEST2 Number.Specifically, as can be seen from Figure 17, the storing state of the storage unit in block 1701 should be " 001 ", but be mistaken for " 101 ", and the storing state of the storage unit in block 1703 should be " 101 ", but be mistaken for " 001 ".

Figure 18 is please referred to, Memory Controller 104 (or memory management circuitry 202) can indicate that duplicative is non-volatile Memory module 106 is bestowed the detection adjusted based on the first default reading voltage VA and reads voltage VTEST3 to read first Page data, and calculate according to detection data to detect the error bit read in read first page data of voltage VTEST3 Number.Specifically, as can be seen from Figure 18, the storing state of the storage unit in block 1801 and block 1805 should be " 001 ", but by " 101 " are mistaken for, and the storing state of the storage unit in block 1803 should be " 101 ", but be mistaken for " 001 ".

According to Figure 16~18, since voltage is read in the detection adjusted based on the first default reading voltage VA Number of error bits in read first page data of VTEST2 be it is the smallest, therefore, (or the memory of Memory Controller 104 Management circuit 202) it can select to read voltage VTEST2 as the first optimization reading voltage to detect.It will be appreciated that although In Figure 16~Figure 18 it is that the detection finely tuned with 3 reads voltages detect and simplify and illustrate, however, the present invention is not limited to This, in practical operation, it is default that Memory Controller 104 (or memory management circuitry 202) can be more than or less than first with multiple groups The detection for reading voltage VA reads voltage to be read out to the storage unit in wordline, can make read bit to find out Voltage is read in the optimization that data have minimum error bit.

In this exemplary embodiment, after finding out the corresponding first default most the first goodization reading voltage for reading voltage VA, Memory Controller 104 (or memory management circuitry 202) can calculate the first default reading voltage VA and the first goodization reads electricity This first reading voltage change is recorded in stressed table most to read voltage change as first by the difference of pressure (retry table).For example, this, which reads table again, can be recorded in reproducible nonvolatile memorizer module 106, or configuration exists In nonvolatile storage in Memory Controller 104 (or memory management circuitry 202).

In particular, when Memory Controller 104 (or memory management circuitry 202) indicates duplicative non-volatile memories Device module 106 according to first it is default read page data (hereinafter referred to as the first page data) that voltage VA is read from wordline can not be by When error correction, Memory Controller 104 (or memory management circuitry 202) can indicate type nonvolatile mould Block 106 adjusts the first default reading voltage VA according to the first reading voltage change in stressed table, and with adjusted First default the first page data for reading voltage VA (that is, voltage is read in the first optimization) to read from wordline.Due to reading table again In value be to be obtained according to current critical voltage distribution (that is, the critical voltage distribution deviated), therefore, duplicative is non- Volatile 106 can be accessed normally.

Figure 19 is the flow chart for reading voltage setting method depicted in an exemplary embodiment according to the present invention.

Figure 19 is please referred to, in step S1901, Memory Controller 104 (or memory management circuitry 202) can be will test In multiple storage units that Data programming is connected to one of wordline (hereinafter referred to as the first wordline).

In step S1903, Memory Controller 104 (or memory management circuitry 202), which can read, is stored in the first word Detection data in the storage unit of line is distributed to obtain the critical voltage of the storage unit of corresponding first wordline.It rebuilds critical The method of voltage's distribiuting has cooperated Figure 14 detailed description as above, and this will not be repeated here.

In step S1905, Memory Controller 104 (or memory management circuitry 202) can depositing according to the first wordline The peak value of the critical voltage distribution of storage unit first default reads voltage judge corresponding first wordline.

In step S1907, Memory Controller 104 (or memory management circuitry 202) can adjust the first default reading Voltage reads voltage to obtain multiple first detections.

In step S1909, Memory Controller 104 (or memory management circuitry 202) can respectively bestow those One detection reads voltage and reads multiple first page datas to first wordline, according to detection data and first page data acquisition pair Should every one first page data number of error bits and according to the minimal error bit number among the number of error bits of these, from this Voltage is read in the first optimization that corresponding first wordline of acquisition among voltage is read in a little first detections.Scanning voltage is bestowed to obtain pair It is as above that the number of error bits answered and the method for determining optimization reading voltage have cooperated Figure 16~18 to be described in detail, and is not repeated herein Explanation.

In step S1911, Memory Controller 104 (or memory management circuitry 202) can calculate the first optimization reading Voltage and the first default difference read between voltage as corresponding first wordline the first reading voltage change and Read the first reading voltage change that corresponding first wordline is recorded in table again.

It will be appreciated that although Figure 19 is to be painted corresponding the first default reading electricity to read lower physical page of setting The first of pressure VA reads voltage change, however the method can also be applied to the second of the default reading voltage VB of setting corresponding second Read voltage change, corresponding third presets the third reading voltage change for reading voltage VC, corresponding 4th default reading electricity The 4th reading voltage change of VD, the 5th of corresponding 5th default reading voltage VE is pressed to read voltage change, correspond to the 6th Default the 6th reading voltage change for reading voltage VF reads voltage adjustment with the 7th of the corresponding 7th default reading voltage VG Value.

Referring to figure 2. 0, in step S2001, Memory Controller 104 (or memory management circuitry 202) can be from host System, which receives, reads instruction.

Later, in step S2003, Memory Controller 104 (or memory management circuitry 202) can refer to according to this reading It enables and identifies corresponding wordline (hereinafter referred to as the first wordline) and bestow the first default reading voltage VA to the first wordline to obtain Multiple bit datas.

In step S2005, Memory Controller 104 (or memory management circuitry 202) determines whether can be correct Decoding acquired bit data in ground is to obtain the page data (hereinafter referred to as the second page data) that correction is completed.

If when available the first page data that correction is completed, in step S2007, Memory Controller 104 (or Memory management circuitry 202) the second page data that correction is completed can be exported to host system 1000.

If the second page data that correction is completed can not be obtained, in step S2009, Memory Controller 104 (or Memory management circuitry 202) the first reading voltage change can be obtained from stressed table, and voltage change is read with first Come to adjust the first default reading voltage and bestow reading voltage adjusted (that is, first new reading voltage) to the first wordline To obtain multiple bit datas.For example, in this exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) It can indicate reproducible nonvolatile memorizer module 106 and adjust reading electricity according to the reading voltage change in stressed table Pressure.However, the invention is not limited thereto, in another exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) reading voltage adjusted can also be calculated, and indicates reproducible nonvolatile memorizer module 106 according to adjustment Voltage afterwards reads instruction to execute.

In step S2011, Memory Controller 104 (or memory management circuitry 202) determines whether can be correct Decoding acquired bit data in ground is to obtain the second page data that correction is completed.

If when available the first page data that correction is completed, step S2007 can be performed.

If the first page data that correction is completed can not be obtained, in step S2013, Memory Controller 104 (or Memory management circuitry 202) output error message is understood to host system 1000.

It will be appreciated that the method can also be applied although Figure 20 is to be painted the flow chart for reading lower physical page Physical page and upper physical page in reading.For example, in reading in the example of physical page, if by bestowing the second reading When voltage VB can not obtain corresponding page data by decoding with bit data acquired in third reading voltage VC, memory control Device 104 (or memory management circuitry 202) processed will use the second reading voltage change and third reads voltage change to divide Not Tiao Zheng second it is default read voltage VB and third is default reads voltage VC, and with readings voltage adjusted (that is, second newly Read voltage and third and newly read voltage) come in therefrom physical page to obtain can error correction the second page data.For another example In reading in the example of physical page, if by bestowing the 4th default reading voltage VD, the 5th default reading voltage VE, the 6th Default reading voltage VF can not be obtained corresponding number of pages with bit data acquired in the 7th default reading voltage VG by decoding According to when, Memory Controller 104 (or memory management circuitry 202) will use the 4th reading voltage change, the 5th read electricity Pressure adjusted value, the 6th reading voltage change adjust separately the 4th default reading voltage, the with the 7th reading voltage change Five default reading voltage VE, the 6th default reading voltage VF and the 7th are default to be read voltage VG and uses reading electricity adjusted Press (that is, the "four news" (new ideas, which read voltage, the 5th, newly reads voltage, the 6th new reading voltage and the 7th new reading voltage) from upper physical page In face obtain can error correction page data.

It is noted that although memory management circuitry 202 is to realize to control in memory in this exemplary embodiment In device 104, however, the present invention is not limited thereto.In another exemplary embodiment of the present invention, memory management circuitry 202 also be may be implemented in One opens in the control circuit of card machine platform and is electrically connected to depositing for reproducible nonvolatile memorizer module 106 through an interface Storage unit array 2202.

In conclusion method for reading data of the invention, Memory Controller, memorizer memory devices and duplicative are non- Volatile can be distributed soft to obtain using adjustment appropriate reading voltage according to the critical voltage of storage unit Thus value promotes the ability of error correction, to avoid Missing data.

Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above-mentioned each method embodiment can lead to The relevant hardware of program instruction is crossed to complete.Program above-mentioned can be stored in a computer readable storage medium.The journey When being executed, execution includes the steps that above-mentioned each method embodiment to sequence；And storage medium above-mentioned include: ROM, RAM, disk or The various media that can store program code such as person's CD.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims

1. a kind of reading voltage setting method is used for a reproducible nonvolatile memorizer module, which is characterized in that this can be answered Formula non-volatile memory module is write with multiple storage units, a plurality of wordline and multiple bit lines, each of storage unit with A wherein wordline for those wordline and a wherein bit line for those bit lines are electrically connected, and each of storage unit can store up Multiple bit datas are deposited, each of bit data can be identified as a first state or one second state according to a voltage, should Method for reading data includes:

In multiple storage units that one first wordline among one Data programming to those wordline is connected；

Those for reading the data that are stored in those storage units of first wordline to obtain corresponding first wordline are deposited One critical voltage of storage unit is distributed；

Multiple scanning voltages are bestowed in first wordline, and are obtained according to the respectively corresponding erroneous bit data of the scanning voltage more A erroneous bit data incrementss；And

Increased according to a peak value of the critical voltage of those storage units of first wordline distribution and those erroneous bit datas Dosage one first default reads voltage judge to correspond to first wordline.

2. reading voltage setting method according to claim 1, which is characterized in that further include:

It adjusts the first default reading voltage and reads voltages to obtain multiple first detections；

It respectively bestows those first detections and reads voltage to first wordline to read multiple first page datas；

According to a number of error bits of the data each of first page data corresponding with those first page data acquisitions；

According to the minimal error bit number among the number of error bits of those the first page datas, electricity is read from those first detections Voltage is read in one first optimization that corresponding first wordline is obtained among pressure；

It calculates first optimization and reads voltage with the first default difference read between voltage as corresponding first wordline One first read voltage change；And

The first reading voltage change of corresponding first wordline is recorded in a stressed table.

3. reading voltage setting method according to claim 2, which is characterized in that above-mentioned reading is stored in first wordline Those storage units in the data obtain the critical voltage distributions of those storage units of corresponding first wordline Step includes:

Multiple scanning voltages are bestowed to first wordline, are corresponded to being read from those storage units for be connected to first wordline Multiple scanning bit datas of each of scanning voltage；

Respectively calculate the bit data for being identified as the first state among the scanning bit data of those corresponding scanning voltages Multiple first state bit data incrementss；And

Being somebody's turn to do for first wordline is obtained according to those first state bit data incrementss for respectively corresponding to those scanning voltages The critical voltage distribution of a little storage units.

4. reading voltage setting method according to claim 1, which is characterized in that those above-mentioned according to first wordline The peak value of the critical voltage distribution of storage unit comes with those erroneous bit data incrementss of those corresponding scanning voltages Judge that the first default the step of of reading voltage for corresponding to first wordline includes:

Search the peak value in critical voltage distribution；

Increased according to the maximum erroneous bit data among those erroneous bit data incrementss of those corresponding scanning voltages Amount identifies the scanning voltage that the peak value is corresponded among those scanning voltages；And

One the relative to corresponding first wordline is obtained according to the scanning voltage for corresponding to the peak value among those scanning voltages One presets the voltage variety for reading voltage and identifies the first default reading voltage according to the voltage variety, wherein should Voltage variety is plus the first default scanning voltage for reading voltage and being equal to the corresponding peak value.

5. reading voltage setting method according to claim 2, which is characterized in that further include:

Multiple bit datas are read from those storage units of first wordline using the first default voltage that reads；

Judgement uses first default those bit datas for reading voltage and reading from those storage units of first wordline Whether error-correcting code can be corresponded to come error correction to obtain one second page data according to one；And

When using this first it is default read those bit datas that voltage is read from those storage units of first wordline without Method when being obtained second page data by error correction, is adjusted according to the correspondence error-correcting code using the first reading voltage Value adjustment this first it is default read voltage with obtain one first it is new read voltage, and bestow this first it is new read voltage to this One wordline is to obtain second page data.

6. reading voltage setting method according to claim 1, which is characterized in that further include:

It is distributed according to the critical voltage of those storage units of first wordline to judge to correspond to the one second of first wordline It is default to read voltage and the default reading voltage of a third；

It adjusts this and second default reads voltage to obtain multiple second detections and read voltages and adjust that the third is default to read electricity Pressure reads voltage to obtain multiple third detections；

It bestows those second detections and reads voltage and those thirds detection reading voltage to first wordline to read multiple thirds Page data；

A number of error bits of each of third page data is obtained according to the data and those third page datas；

According to the minimal error bit number among the number of error bits of those third page datas, electricity is read from those second detections Press one second optimization reading voltage and the third of first wordline corresponding with acquisition among those thirds detection reading voltage excellent Change and reads voltage；

It calculates second optimization and reads voltage with the second default difference read between voltage as corresponding first wordline One second read voltage change；

It calculates third optimization and reads voltage with the default difference read between voltage of the third as corresponding first wordline A third read voltage change；And

It reads voltage in the second reading voltage change for reading corresponding first wordline of record in table again and the third and adjusts Value.

7. a kind of reading voltage setting method is used for a reproducible nonvolatile memorizer module, which is characterized in that this can be answered Formula non-volatile memory module is write with multiple storage units, a plurality of wordline and multiple bit lines, each of storage unit with A wherein wordline for those wordline and a wherein bit line for those bit lines are electrically connected, and each of storage unit can store up Multiple bit datas are deposited, each of bit data can be identified as a first state or one second state according to a voltage, should Method for reading data includes:

The one first default reading voltage for adjusting corresponding first wordline reads voltage to obtain multiple first detections；

8. reading voltage setting method according to claim 7, which is characterized in that further include:

When the bit data read from those storage units of first wordline using the first default reading voltage can not When being obtained second page data by error correction, the first reading voltage change is used according to the correspondence error-correcting code Adjust this first it is default read voltage with obtain one first it is new read voltage and bestow this first it is new read voltage to this first Wordline is to obtain second page data.

9. reading voltage setting method according to claim 7, which is characterized in that further include:

The one second of corresponding first wordline of adjustment is default to read voltage to obtain multiple second detections reading voltages and adjust One third of corresponding first wordline is default to read voltage to obtain multiple third detections and read voltage；

10. a kind of control circuit, for accessing a reproducible nonvolatile memorizer module, which is characterized in that control electricity Road includes:

One interface is for electrically connecting to the reproducible nonvolatile memorizer module, and wherein the duplicative is non-volatile deposits Memory modules have multiple storage units, a plurality of wordline and multiple bit lines, and each of storage unit and those wordline are wherein A wherein bit line for one wordline and those bit lines is electrically connected, and each of storage unit can store multiple bit numbers According to, and each of bit data can be identified as a first state or one second state according to a voltage；And

One memory management circuitry is electrically connected to the interface and to by one among a Data programming to those wordline In multiple storage units that first wordline is connected,

Wherein the memory management circuitry is also to read the data in those storage units for being stored in first wordline The critical voltage distribution of those storage units of corresponding first wordline is obtained,

Wherein the memory management circuitry is also to bestow multiple scanning voltages in first wordline, and according to respectively scanning electricity Corresponding erroneous bit data is pressed to obtain multiple erroneous bit data incrementss；And

Wherein the memory management circuitry is also to according to the critical voltage distributions of those storage units of first wordline One peak value judges one first default reading voltage of corresponding first wordline with those erroneous bit data incrementss.

11. control circuit according to claim 10, which is characterized in that

Wherein the memory management circuitry also reads electricity to adjust the first default reading voltage to obtain multiple first detections Pressure,

Wherein the memory management circuitry also reads voltage to first wordline to read respectively to bestow those first detections Multiple first page datas are taken,

Wherein the memory management circuitry is also to according to the data corresponding with those first page data acquisitions each of first One number of error bits of page data,

Wherein the memory management circuitry is also to the minimal error among the number of error bits according to those the first page datas Voltage is read in bit number, one first optimization for reading corresponding first wordline of acquisition among voltage from those first detections,

Wherein the memory management circuitry is also read between voltage and the first default reading voltage to calculate first optimization A difference read voltage change as the one first of corresponding first wordline,

Wherein the first reading voltage of the memory management circuitry also to record corresponding first wordline in a stressed table Adjusted value.

12. control circuit according to claim 10, which is characterized in that be stored in being somebody's turn to do for first wordline in above-mentioned reading The data in a little storage units obtain the operation of the critical voltage distribution of those storage units of corresponding first wordline In, which bestows multiple scanning voltages to first wordline, with from be connected to first wordline those deposit Multiple scanning bit datas of corresponding each of scanning voltage are read in storage unit, respectively calculate those corresponding scanning voltages Scanning bit data among be identified as the first state bit data multiple first state bit data incrementss, with And those of first wordline are obtained according to those first state bit data incrementss for respectively corresponding to those scanning voltages The critical voltage of storage unit is distributed.

13. control circuit according to claim 10, which is characterized in that in above-mentioned those storages according to first wordline The peak value of the critical voltage distribution of unit judges with those erroneous bit data incrementss of those corresponding scanning voltages In the first default operation for reading voltage of corresponding first wordline, which searches critical voltage distribution In the peak value, according to the maximum number of error bits among those erroneous bit data incrementss of those corresponding scanning voltages Identified according to incrementss a scanning voltage of the peak value is corresponded among those scanning voltages and according to those scanning voltages among The scanning voltage of the corresponding peak value is obtained to be become relative to the one first default voltage for reading voltage of corresponding first wordline Change amount and according to the voltage variety identify this first it is default read voltage, wherein the voltage variety is first default plus this Read the scanning voltage that voltage is equal to the corresponding peak value.

14. control circuit according to claim 10, which is characterized in that the memory management circuitry is first default using this It reads voltage and reads multiple bit datas from those storage units of first wordline, judge to use the first default reading electricity Press those bit datas for being read from those storage units of first wordline whether can according to a corresponding error-correcting code come One second page data is obtained by error correction,

When using this first it is default read those bit datas that voltage is read from those storage units of first wordline without Method according to the correspondence error-correcting code come when being obtained second page data by error correction, the memory management circuitry also to The first default reading voltage is adjusted using the first reading voltage change to obtain one first new reading voltage and bestow The first new voltage that reads obtains second page data to first wordline.

15. control circuit according to claim 10,

It is characterized in that, the memory management circuitry is also to critical according to this for those storage units for corresponding to first wordline Voltage's distribiuting come judge to correspond to first wordline one second it is default read voltage and the default reading voltage of a third,

The memory management circuitry also reads voltages simultaneously to obtain multiple second detections to adjust the second default reading voltage And adjust the default reading voltage of the third and read voltages to obtain multiple thirds detections,

The memory management circuitry also to bestow those second detection read voltages and those thirds detection read voltage to should First wordline to read multiple third page datas,

The memory management circuitry is also to obtain each of third page data according to the data and those third page datas One number of error bits,

The memory management circuitry is also to the minimal error bit among the number of error bits according to those third page datas Number reads the one second of voltage first wordline corresponding with acquisition among those thirds detection reading voltage from those second detections Voltage is read in optimization and voltage is read in third optimization,

The memory management circuitry also reads voltage and second default one read between voltage to calculate second optimization Difference reads voltage change as the one second of corresponding first wordline,

The memory management circuitry also reads voltage and default one read between voltage of the third to calculate third optimization Difference reads voltage change as a third of corresponding first wordline,

The the second reading voltage adjustment of the memory management circuitry also to read corresponding first wordline of record in table again at this Value reads voltage change with the third.

16. a kind of memorizer memory devices characterized by comprising

A connector is electrically connected to a host system；

One reproducible nonvolatile memorizer module, wherein the reproducible nonvolatile memorizer module has multiple storages Unit, a plurality of wordline and multiple bit lines, wherein a wordline and those bit lines of each of storage unit and those wordline Wherein bit line be electrically connected, each of storage unit can store multiple bit datas, and each of bit data It can be identified as a first state or one second state according to a voltage；And

One Memory Controller is electrically connected to the connector and the reproducible nonvolatile memorizer module, and to incite somebody to action In multiple storage units that one first wordline among one Data programming to those wordline is connected,

The Memory Controller also obtains pair to read the data in those storage units for being stored in first wordline Should the first wordline those storage units a critical voltage distribution,

The Memory Controller is and corresponding according to the respectively scanning voltage also to bestow multiple scanning voltages in first wordline Erroneous bit data obtain multiple erroneous bit data incrementss；And

The Memory Controller is also to the peak value according to the critical voltage distributions of those storage units of first wordline One first default reading voltage of corresponding first wordline is judged with those erroneous bit data incrementss.

17. memorizer memory devices according to claim 16, which is characterized in that

The Memory Controller also reads voltages to adjust the first default reading voltage to obtain multiple first detections,

The Memory Controller is also multiple to read to first wordline respectively to bestow those the first detection reading voltages First page data,

The Memory Controller is also to according to the detection data each of first page corresponding with those first page data acquisitions One number of error bits of data,

The Memory Controller also to the minimal error bit number among the number of error bits according to those the first page datas, Voltage is read in one first optimization for reading corresponding first wordline of acquisition among voltage from those first detections,

The Memory Controller also to calculate first optimization read voltage and this first it is default read between voltage it is one poor It is worth and reads voltage change as the one first of corresponding first wordline,

The the first reading voltage change of the Memory Controller also to record corresponding first wordline in a stressed table.

18. memorizer memory devices according to claim 17, which is characterized in that be stored in first word in above-mentioned reading The data in those storage units of line are distributed to obtain the critical voltage of those storage units of corresponding first wordline Operation in, which bestows multiple scanning voltages to first wordline, with should from be connected to first wordline Multiple scanning bit datas of corresponding each of scanning voltage are read in a little storage units, respectively calculate those corresponding scannings The multiple first state bit datas for being identified as the bit data of the first state among the scanning bit data of voltage increase Amount, and first wordline is obtained according to those first state bit data incrementss for respectively corresponding to those scanning voltages The critical voltage of those storage units is distributed.

19. memorizer memory devices according to claim 16, which is characterized in that in above-mentioned being somebody's turn to do according to first wordline The peak value of the critical voltage distribution of a little storage units and those erroneous bit data incrementss of those corresponding scanning voltages In operation to judge to correspond to the first default reading voltage of first wordline, which searches the critical voltage Peak value in distribution, according to the maximum wrong ratio of one among those erroneous bit data incrementss of those corresponding scanning voltages Special data incrementss identify the scanning voltage for corresponding to the peak value among those scanning voltages and according to those scanning voltages Among correspond to the scanning voltage of the peak value and obtain the one first default electricity for reading voltage relative to corresponding first wordline Pressure variable quantity and according to the voltage variety identify this first it is default read voltage, wherein the voltage variety plus this first Default scanning voltage for reading voltage and being equal to the corresponding peak value.

20. memorizer memory devices according to claim 16, which is characterized in that the Memory Controller using this first The default voltage that reads reads multiple bit datas from those storage units of first wordline, judges to use the first default reading Whether those bit datas for taking voltage to read from those storage units of first wordline can be according to a corresponding error corrections Code is obtained one second page data by error correction,

When using this first it is default read those bit datas that voltage is read from those storage units of first wordline without Method is according to the correspondence error-correcting code come when being obtained second page data by error correction, the Memory Controller is also to make The first default reading voltage is adjusted with the first reading voltage change to obtain one first new reading voltage and bestow this The first new voltage that reads obtains second page data to first wordline.

21. memorizer memory devices according to claim 16, which is characterized in that

Wherein the critical voltage of the Memory Controller also to those storage units according to corresponding first wordline is distributed Come judge to correspond to first wordline one second it is default read voltage and the default reading voltage of a third,

Wherein the Memory Controller also reads voltages to adjust the second default reading voltage to obtain multiple second detections And it adjusts the default reading voltage of the third and reads voltages to obtain multiple thirds detections,

Wherein also to bestow, voltage is read in those second detections to the Memory Controller and the detection of those thirds reads voltage extremely First wordline to read multiple third page datas,

Wherein the Memory Controller is also to obtain each of third page data according to the data and those third page datas A number of error bits,

Wherein the Memory Controller is also to the minimal error ratio among the number of error bits according to those third page datas Special number reads the one the of corresponding first wordline of acquisition among voltages and those thirds detection reading voltage from those second detections Voltage is read in two optimizations and voltage is read in third optimization,

Wherein the Memory Controller is also read between voltage and the second default reading voltage to calculate second optimization One difference reads voltage change as the one second of corresponding first wordline,

Wherein the Memory Controller is also read between voltage and the default reading voltage of the third to calculate third optimization One difference reads voltage change as a third of corresponding first wordline,

Wherein the second reading voltage tune of the Memory Controller also to read corresponding first wordline of record in table again at this Whole value reads voltage change with the third.