CN104952486B - Data storage method, memorizer control circuit unit and memorizer memory devices - Google Patents

Abstract

The present invention proposes a kind of data storage method, memorizer control circuit unit and memorizer memory devices.This data storage method includes: in the multiple storage units for being connected the first character line in the character line of the reproducible nonvolatile memorizer module of Data programming to memorizer memory devices, wherein the first default voltage that reads initially is set for first character line.This data storage method further include: adjustment first is default to read voltage so that obtain can be with reading voltage and bestow first and can read the first page data to the first character line with voltage is read for the first of the first character line; if and first available read voltage and when the first default difference read between voltage is greater than predetermined threshold level, carries out the protection for the first page data and operate.

Description

Data storage method, memorizer control circuit unit and memorizer memory devices

Technical field

The invention relates to a kind of data storage methods, and non-volatile for duplicative in particular to one kind Data storage method, memorizer control circuit unit and the memorizer memory devices of memory.

Background technique

Digital camera, mobile phone and MP3 are very rapid in growth over the years, so that demand of the consumer to storage media Also rapidly increase.Since type nonvolatile (rewritable non-volatilememory) has data Non-volatile, power saving, it is small in size, without the characteristics such as mechanical structure, read or write speed be fast, be most suitable for portable electronic product, such as pen Remember this computer.Solid state hard disk is exactly a kind of storage device using flash memory as storage media.Therefore, flash in recent years Device industry becomes a ring quite popular in electronic industry.

According to the storable bit number of each storage unit, single-order storage can be divided into non-(NAND) type flash memory Unit (Single Level Cell, abbreviation SLC) NAND type flash memory, multistage storage element (Multi Level Cell, abbreviation MLC) NAND type flash memory and Complex Order storage element (Trinary Level Cell, abbreviation TLC) NAND Type flash memory.

However, either that storage unit flash memory module, to stored by the same entity erased cell When data are repeatedly read, such as the reading times between 10 ten thousand to million times, it is more likely that read data, which can occur, is The situation of mistake in addition this be read several times in entity erased cell stored data and can be abnormal or lose.And it is such Phenomenon is known as " reading interference " (read-disturb) so that field of the present invention tool usually intellectual is used.In particular, flash In device module can storage flash memory storage system system data (such as firmware code (Firmware Code), archives configuration Table (FileAllocation Table, abbreviation FAT), and this system data can be high during flash memory storage system operates The reading on frequency ground.

Fig. 1 is the schematic diagram of the flash memory component according to shown by the prior art.

Fig. 1 is please referred to, flash memory component 1 includes the electric charge capture layer (chargetrapping for stored electrons Layer) 2, for applying alive control grid (Control Gate) 3, tunneling oxide layer (TunnelOxide) 4 and polycrystalline Dielectric layer (Interpoly Dielectric) 5 between silicon.It, can be by will be electric when flash memory component 1 to be write data to Son injection charge benefit catches layer 2 to change the critical voltage of flash memory component 1, thus defines the number of flash memory component 1 The high low state of word, and realize the function of storage data.Here, injection electronics to the process that charge benefit catches layer 2 is known as sequencing.Instead It is removed by catching in layer 2 institute's injected electrons from charge benefit when being intended to remove stored data, then can make quick flashing The reply of memory component 1 is the state before not being programmed.

However, in process of production, the critical voltage of flash memory component may be made to be distributed because of the variation of processing procedure Offset will result in above-mentioned " read so that the storing state of flash memory component 1 possibly can not be correctly identified The phenomenon that interference ", occurs.Also because existing flash memory in the electric field across tunneling oxide layer 4 with flash memory The micromation of processing procedure in turn results in the flash memory of flash memory processing procedure after 20 nanometers, and showing for reading interference occurs As increasingly severe, also because there is such phenomenon, there is driving various manufacturers that must develop invariably be can ensure that correctly Store the mechanism of data.

And existing reading interference protection mechanism, a number of error bits is usually set when being read Mesh threshold value, and will be more than that the data of this error bits numbers threshold value re-write other entities and erase list Member has ensured that the correctness of data.However, the reason of causing error bit has very much, error bit is made a decision if single, The number re-write that will lead to flash memory is too frequent, and then promotes the loss of flash memory, and causing to reduce can answer Write the service life of formula non-volatile memory storage device.

Summary of the invention

The present invention provides a kind of data storage method, memorizer control circuit unit and memorizer memory devices, can be with It is effectively prevented from Missing data caused by due to reading interference, and extends the service life of memorizer memory devices.

One example of the present invention embodiment proposes a kind of data storage method, is used for type nonvolatile mould Block, and above-mentioned reproducible nonvolatile memorizer module has multiple storage units, a plurality of character line and a plurality of bit line.Often A wherein bit line for the wherein character line and these bit lines of a storage unit and these character lines is electrically connected. Each storage unit can store multiple bit datas, and each bit data can be identified as first state or second according to voltage State.Above-mentioned data storage method include: the first character line by Data programming into these character lines connected it is more In a storage unit, wherein the first default voltage that reads initially is set for the first character line, and the first default reading is adjusted Voltage is taken to obtain the first available reading voltage for the first character line and bestow the first available voltage that reads to the first word Line is accorded with to read the first page data.Above-mentioned first page data is can correctly to be corrected by error checking with correcting circuit.Above-mentioned Data storage method further include: if the first available voltage and the first default the first difference read between voltage of reading is greater than first When predetermined threshold level, multiple storage units that second character line of the first page Data programming into these character lines is connected In.

In one example of the present invention embodiment, further includes: again by the first logical subunit belonging to the first page data First instance programmed cell is mapped to, wherein these storage units that the second character line is connected form multiple entity programs Unit, and first instance programmed cell is one of these entity program units.

In one example of the present invention embodiment, wherein adjustment first is default to read voltage to obtain for the first character line First can with read voltage and bestow first can with read voltage to the first character line come the step of reading the first page data Including according to reading again, table execution is stressed to be operated.

In one example of the present invention embodiment, wherein including: to execute according to the step of table executes stressed running is read again First is obtained according to stressed table after stressed running at least once and reads voltage change, and reads voltage adjustment according to first Reading voltage can be used to adjust the first default reading voltage to obtain first in value.

In one example of the present invention embodiment, above-mentioned data storage method includes further include: judgement, which executes, reads fortune again The number of work whether be greater than the first preset number and be less than or equal to the second preset number, and if execute read again running number it is big In the first preset number and when being less than or equal to the second preset number, then identify first it is available read voltage with first it is default read it is electric The first difference between pressure is greater than the first predetermined threshold level.

In one example of the present invention embodiment, above-mentioned data storage method further include: bestow multiple scanning voltage extremely First character line corresponding each scan the multiple of voltage and scans to read from these storage units for be connected to the first character line Bit data, and respectively calculate it is corresponding these scan voltage scan the bit for being identified as first state in bit data Multiple first state bit data incrementss of data.In addition, also according to respectively correspond to these scan voltage these first Status bits data incrementss obtain the critical voltage distribution of these storage units of the first character line.Then, critical electricity is searched Peak value and the valley adjacent with peak value in pressure distribution, and judge whether valley is greater than first in advance divided by the obtained ratio of peak value Fixed-ratio.And if identification first is available to read electricity when valley is greater than the first estimated rate divided by the obtained ratio of peak value Pressure and the first default the first difference read between voltage are greater than the first predetermined threshold level.

In one example of the present invention embodiment, above-mentioned data storage method further include: bestow multiple scanning voltage extremely First character line to read out the multiple data for respectively corresponding these scanning voltages from the first character line, and is recorded and is respectively corresponded Multiple error bits numbers of these data.Then judge by the minimal error bit number in these error bits numbers divided by Whether maximum the obtained error bits numbers ratio of error bits numbers is greater than the second estimated rate.And if number of error bits When mesh ratio is greater than the second estimated rate, then identify that first between the first available reading voltage and the first default reading voltage is poor Value is greater than the first predetermined threshold level.

One example of the present invention embodiment proposes a kind of memorizer control circuit unit, non-volatile for accessing duplicative Property memory module, and above-mentioned memorizer control circuit unit include: host interface, memory interface and memory management electricity Road.Host interface is electrically connected to host system.Memory interface is electrically connected to reproducible nonvolatile memorizer module, And above-mentioned reproducible nonvolatile memorizer module has multiple storage units, a plurality of character line and a plurality of bit line. Each storage unit electrically connects with a wherein character line for these character lines and a wherein bit line for these bit lines It connects.In addition, each storage unit can store multiple bit datas, and each bit data can be identified according at least one voltage For first state or the second state.Memory management circuitry is electrically connected to host interface and memory interface, and with following Up to the first instruction sequence to reproducible nonvolatile memorizer module with by Data programming into these character lines first In multiple storage units that character line is connected.And the above-mentioned first default voltage that reads initially is set for the first character Line.Memory management circuitry is also read to adjust the first default reading voltage with obtaining to can be used for the first of the first character line Voltage and the second instruction sequence is assigned to reproducible nonvolatile memorizer module to bestow first and available read voltage extremely First character line reads the first page data, wherein the first page data is can correctly to be corrected by error checking with correcting circuit. If the first available the first difference read between voltage and the first default reading voltage is greater than the first predetermined threshold level, memory Management circuit is also to assign third instruction sequence to reproducible nonvolatile memorizer module with by first page data program In multiple storage units that the second character line changed into these character lines is connected.

In one example of the present invention embodiment, memory management circuitry by belonging to the first page data first also to patrol Subelement is collected to remap to first instance programmed cell.These storage units that second character line is connected form multiple realities Body programmed cell, and first instance programmed cell is one of these entity program units.

In one example of the present invention embodiment, reading in the storage unit from the first character line can be by error checking Before the first page data correctly corrected with correcting circuit, memory management circuitry also reads table again to duplicative to basis Non-volatile memory module assigns the 4th instruction sequence to execute stressed running, with the storage list connected from the first character line Data are read in member.

In one example of the present invention embodiment, memory management circuitry basis after executing stressed running at least once Stressed table obtains first and reads voltage change, and the first default reading voltage is adjusted according to the first reading voltage change To obtain the first available reading voltage.

In one example of the present invention embodiment, memory management circuitry judges to execute whether the number for reading running again is greater than First preset number and be less than or equal to the second preset number.If executing the number for reading running again greater than the first preset number and being less than When equal to the second preset number, then memory management circuitry identification first is available reads between voltage and the first default reading voltage The first difference be greater than the first predetermined threshold level.

In one example of the present invention embodiment, memory management circuitry bestows multiple voltages that scan to the first character line, To read correspondence from these storage units for be connected to the first character line, each scanning the multiple of voltage scans bit data.And Memory management circuitry respectively calculate it is corresponding these scan voltage scan the ratio for being identified as first state in bit data Multiple first state bit data incrementss of special data, and according to respectively corresponding to these these first shapes for scanning voltage State bit data incrementss obtain the critical voltage distribution of these storage units of the first character line.Then, memory management electricity The peak value and the valley adjacent with peak value in critical voltage distribution are searched in road, and judge valley divided by the obtained ratio of peak value Whether the first estimated rate is greater than.If valley is greater than the first estimated rate divided by the obtained ratio of peak value, memory pipe It manages the available reading voltage of circuit identification first and the first default the first difference read between voltage is greater than the first predetermined threshold level.

In one example of the present invention embodiment, memory management circuitry bestows multiple voltages that scan to the first character line, To read out the multiple data for respectively corresponding these scanning voltages from the first character line, and records and respectively correspond the more of these data A error bits numbers.Then memory management circuitry judges to remove the minimal error bit number in these error bits numbers Whether it is greater than the second estimated rate with the obtained error bits numbers ratio of maximum error bits numbers.And if error bit When number ratio is greater than the second estimated rate, then memory management circuitry identification first is available reads voltage and the first default reading The first difference between voltage is greater than the first predetermined threshold level.

One example of the present invention embodiment proposes a kind of memorizer memory devices, comprising: connecting interface unit, duplicative Non-volatile memory module and memorizer control circuit unit.Connecting interface unit is electrically connected to host system.It can make carbon copies Formula non-volatile memory module has multiple storage units, a plurality of character line and a plurality of bit line, and each storage unit It is electrically connected with a wherein character line for these character lines and a wherein bit line for these bit lines.In addition, each Storage unit can store multiple bit datas, and each bit data can be identified as according at least one voltage first state or Second state.Memorizer control circuit unit is electrically connected to connecting interface unit and type nonvolatile mould Block, and in multiple storage units to be connected the first character line of the Data programming into these character lines.First The default voltage that reads initially is set for the first character line.Memorizer control circuit unit is also to adjust the first default reading Voltage is taken to obtain the first available reading voltage for the first character line and bestow the first available voltage that reads to the first word Line is accorded with to read the first page data.And the first page data is can correctly to be corrected by error checking with correcting circuit.If first can When with reading voltage and the first default the first difference read between voltage greater than the first predetermined threshold level, memorizer control circuit Unit is also in multiple storage units for being connected the second character line of the first page Data programming into these character lines.

In one example of the present invention embodiment, memorizer control circuit unit is also to by belonging to the first page data One logical subunit remaps to first instance programmed cell.These storage units that second character line is connected form more A entity program unit, and first instance programmed cell is one of these entity program units.

In one example of the present invention embodiment, reading in the storage unit from the first character line can be by error checking Before the first page data correctly corrected with correcting circuit, memorizer control circuit unit is also to execute weight according to stressed table Running is read, to read data from the storage unit that the first character line is connected.

In one example of the present invention embodiment, memorizer control circuit unit is after executing stressed running at least once First is obtained according to stressed table and reads voltage change, and the first default reading is adjusted according to the first reading voltage change Voltage is to obtain the first available reading voltage.

Whether memorizer control circuit unit judges execute the stressed number operated in one example of the present invention embodiment Greater than the first preset number and it is less than or equal to the second preset number.If execute read again running number be greater than the first preset number and When less than or equal to the second preset number, then memorizer control circuit unit identification first is available reads voltage and the first default reading The first difference between voltage is greater than the first predetermined threshold level.

In one example of the present invention embodiment, memorizer control circuit unit bestows multiple voltages that scan to the first character Line, to read correspondence from these storage units for be connected to the first character line, each scanning the multiple of voltage scans bit number According to.In addition, memorizer control circuit unit respectively calculate it is corresponding these scan scanning in bit data for voltage and be identified as Multiple first state bit data incrementss of the bit data of first state, and voltage is scanned according to these are respectively corresponded to These first state bit data incrementss obtain the first character line these storage units critical voltage distribution.Then, Memorizer control circuit unit searches the peak value and the valley adjacent with peak value in critical voltage distribution, and judges to remove valley Whether it is greater than the first estimated rate with the obtained ratio of peak value.If valley is greater than the first predetermined ratio divided by the obtained ratio of peak value When rate, then memorizer control circuit unit identification first is available reads voltage and the first default the first difference read between voltage Greater than the first predetermined threshold level.

In one example of the present invention embodiment, memorizer control circuit unit bestows multiple voltages that scan to the first character Line to read out the multiple data for respectively corresponding these scanning voltages from the first character line, and records and respectively corresponds these data Multiple error bits numbers.Then memorizer control circuit unit judges are by the minimal error ratio in these error bits numbers Whether special number is greater than the second estimated rate divided by the obtained error bits numbers ratio of maximum error bits numbers.And if When error bits numbers ratio is greater than the second estimated rate, then memorizer control circuit unit identification first it is available read voltage with First default the first difference read between voltage is greater than the first predetermined threshold level.

Based on above-mentioned, the present invention can reduce the number for being read out protection operation, reach that reduce duplicative non-volatile Property memory module loss, and then promoted reproducible nonvolatile memorizer module service life the effect of.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.

Detailed description of the invention

Fig. 1 is the schematic diagram of the flash memory component according to shown by the prior art；

Fig. 2 is the schematic diagram of the host system according to shown by an exemplary embodiment and memorizer memory devices；

Fig. 3 is the signal of the computer according to shown by an exemplary embodiment, input/output device and memorizer memory devices Figure；

Fig. 4 is the schematic diagram of the host system according to shown by an exemplary embodiment and memorizer memory devices；

Fig. 5 is the schematic block diagram for showing the memorizer memory devices according to shown by an exemplary embodiment；

Fig. 6 is the schematic block diagram of the reproducible nonvolatile memorizer module according to shown by an exemplary embodiment；

Fig. 7 is the schematic diagram of the memory cell array according to shown by an exemplary embodiment；

Fig. 8 is grid corresponding to the write-in data that are stored in memory cell array according to shown by an exemplary embodiment The statistics distribution diagram of voltage；

Fig. 9 is the schematic diagram of the sequencing storage unit according to shown by an exemplary embodiment；

Figure 10 is the schematic diagram that data are read in the slave storage unit according to shown by an exemplary embodiment；

Figure 11 is the schematic diagram that data are read in the slave storage unit according to shown by another exemplary embodiment；

Figure 12 A, Figure 12 B show with the example that Figure 12 C is the management entity erased cell according to shown by an exemplary embodiment It is intended to；

Figure 13 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment；

Figure 14 is according to shown by an exemplary embodiment when the multiple sequencing of storage unit and to be stored in storage after erasing single The statistics distribution diagram of grid voltage corresponding to write-in data in element array；

Figure 15 is the schematic diagram of the stressed table according to shown by this exemplary embodiment；

Figure 16 is the schematic diagram of the distribution of the critical voltage according to shown by another exemplary embodiment；

Figure 17 is the flow chart of the data storage method according to shown by this exemplary embodiment.

Description of symbols:

1: flash memory component；

2: charge benefit catches layer；

3: control grid；

4: tunneling oxide layer；

5: dielectric layers between polycrystal silicon；

1000: host system；

1100: computer；

1102: microprocessor；

1104: random access memory；

1106: input/output device；

1108: system bus；

1110: data transmission interface；

1202: mouse；

1204: keyboard；

1206: display；

1208: printer；

1212:U disk；

1214: memory card；

1216: solid state hard disk；

1310: digital camera；

1312:SD card；

1314:MMC card；

1316: memory stick；

1318:CF card；

1320: embedded storage device；

100: memorizer memory devices；

102: connecting interface unit；

104: memorizer control circuit unit；

106: reproducible nonvolatile memorizer module；2202: memory cell array；

2204: character line control circuit；

2206: bit line control circuit；

2208: row decoder；

2210: data input/output buffer；

2212: control circuit；

702: storage unit；

704: bit line；

706: character line；

708: source electrode line；

712: select grid drain electrode transistor；

714: select grid source electrode transistor；

VA: the first default reading voltage；

VB: the second default reading voltage；

VC: third is default to read voltage；

202: memory management circuitry；

410 (0)~410 (N): entity erased cell；

502: data field；

504: idle area；

506: system area；

508: replacing area；

LBA (0)~LBA (H): logic unit；

LZ (0)~LZ (M): logic region；

204: host interface；

206: memory interface；

208: error checking and correcting circuit；

210: buffer storage；

212: electric power management circuit；

1501: reading table again；

1503: reading number of operations field again；

1505: adjustment voltage field；

P: peak value；

Q: valley；

S1701, S1703, S1705, S1707, S1709: the step of reading data.

Specific embodiment

In general, memorizer memory devices (also referred to as, memory storage system) include duplicative non-volatile memories Device module and controller (also referred to as, control circuit).Being commonly stored device storage device is used together with host system, so that host System can write data into memorizer memory devices or read from memorizer memory devices data.

Fig. 2 is the schematic diagram of the host system according to shown by an exemplary embodiment and memorizer memory devices.

Referring to figure 2., host system 1000 generally comprises computer 1100 and input/output (input/output, I/O) is filled Set 1106.Computer 1100 include microprocessor 1102, random access memory (random accessmemory, RAM) 1104, System bus 1108 and data transmission interface 1110.Fig. 3 is the computer according to shown by an exemplary embodiment, input/output dress Set the schematic diagram with memorizer memory devices.Input/output device 1106 includes the mouse 1202 such as Fig. 3, keyboard 1204, display Device 1206 and printer 1208.It will be appreciated that the unrestricted input/output device 1106 of device shown in Fig. 3, input/defeated Device 1106 can further include other devices out.

In embodiments of the present invention, memorizer memory devices 100 are by data transmission interface 1110 and host system 1000 other elements are electrically connected.Pass through microprocessor 1102, random access memory 1104 and input/output device 1106 Running can write data into memorizer memory devices 100 or read data from memorizer memory devices 100.For example, depositing Reservoir storage device 100 can be USB flash disk 1212 as shown in Figure 3, memory card 1214 or solid state hard disk (Solid State Drive, abbreviation SSD) 1216 equal type nonvolatile storage devices.

In general, host system 1000 is that can substantially cooperate with memorizer memory devices 100 to store appointing for data Meaning system.Although host system 1000 is explained with computer system, however, of the invention another in this exemplary embodiment Host system 1000 can be digital camera, video camera, communication device, audio player or video playing in one exemplary embodiment The systems such as device.For example, when host system is digital camera (video camera) 1310, type nonvolatile storage dress It sets then as its used SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded Storage device 1320 (as shown in Figure 4).Fig. 4 is the host system according to shown by an exemplary embodiment and memorizer memory devices Schematic diagram.Embedded storage device 1320 includes embedded multi-media card (Embedded MMC, abbreviation eMMC).It is worth mentioning , embedded multi-media card is directly electrically connected on the substrate of host system.

Fig. 5 is the schematic block diagram for showing the memorizer memory devices according to shown by an exemplary embodiment.

Referring to figure 5., memorizer memory devices 100 include connecting interface unit 102, memorizer control circuit unit 104 With reproducible nonvolatile memorizer module 106.

In this exemplary embodiment, connecting interface unit 102 is to be compatible to universal serial bus (UniversalSerial Bus, abbreviation USB) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, and connecting interface unit 102 is also possible to meet Advanced attachment (Parallel Advanced TechnologyAttachment, abbreviation PATA) standard, Electrical and Electronic arranged side by side Association of Engineers (Institute of Electrical andElectronic Engineers, abbreviation IEEE) 1394 standards, High-speed peripheral component connecting interface (PeripheralComponent Interconnect Express, abbreviation PCI Express) standard, secure digital (SecureDigital, abbreviation SD) interface standard, the advanced attachment (Serial of sequence Advanced TechnologyAttachment, abbreviation SATA) standard, a ultrahigh speed generation (Ultra High Speed-I, letter Claim UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, abbreviation UHS-II) interface standard, memory stick (Memory Stick, abbreviation MS) interface standard, Multi Media Card (Multi Media Card, abbreviation MMC) interface standard, Down enters formula Multi Media Card (Embedded Multimedia Card, abbreviation eMMC) interface standard, general flash memory (Universal Flash Storage, abbreviation UFS) interface standard, compact flash (Compact Flash, abbreviation CF) interface Standard, integrated driving electrical interface (Integrated Device Electronics, abbreviation IDE) standard or other be suitble to Standard.

Memorizer control circuit unit 104 is to execute multiple logic gates or control with hardware pattern or firmware pattern implementation System instruction, and data are carried out in reproducible nonvolatile memorizer module 106 according to the instruction of host system 1000 The running such as be written, read and erase.

Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and uses To store the data that host system 1000 is written.In this exemplary embodiment, reproducible nonvolatile memorizer module 106 It is multi-level cell memory (Multi Level Cell, abbreviation MLC) NAND type flash memory module (that is, a storage unit In can store the flash memory modules of 2 bit datas).However, the invention is not limited thereto, duplicative non-volatile memories Device module 106 can also be single-order storage unit (Single Level Cell, abbreviation SLC) NAND type flash memory module (that is, flash memory module that 1 bit data can be stored in a storage unit), Complex Order storage unit (Trinary Level Cell, abbreviation TLC) NAND type flash memory module be (that is, can store 3 bit datas in a storage unit Flash memory module), other flash memory modules or other memory modules with the same characteristics.

Fig. 6 is the schematic block diagram of the reproducible nonvolatile memorizer module according to shown by an exemplary embodiment.

Fig. 6 is please referred to, reproducible nonvolatile memorizer module 106 includes memory cell array 2202, character line traffic control Circuit 2204 processed, bit line control circuit 2206, row decoder (column decoder) 2208, data input/output buffering Device 2210 and control circuit 2212.

Fig. 7 is the schematic diagram of the memory cell array according to shown by an exemplary embodiment.

Please refer to Fig. 6 and Fig. 7, memory cell array 2202 includes to store multiple storage units 702 of data, multiple Select grid drain electrode (select gate drain, abbreviation SGD) transistor 712 and multiple select grid source electrodes (select gate Source, abbreviation SGS) transistor 714 and connect a plurality of bit lines 704 of these storage units, a plurality of character line 706, with Common source line 708 (as shown in Figure 7).Storage unit 702 is to be configured with array manner in bit line 704 and character line 706 On crosspoint.When receiving write instruction from memorizer control circuit unit 104 or reading instruction, control circuit 2212 can be controlled Character line control circuit 2204 processed, bit line control circuit 2206, row decoder 2208, data input/output buffer 2210 It writes data to memory cell array 2202 or reads from memory cell array 2202 data, wherein character line control circuit 2204 to control the voltage bestowed to character line 706, and bit line control circuit 2206 is bestowed to control to bit line 704 Voltage, row decoder 2208 selects corresponding bit line according to the column address in instruction, and data input/output is slow It rushes device 2210 and is configured to temporarily store data.

Storage unit in reproducible nonvolatile memorizer module 106 is to represent more bits with a variety of grid voltages (bits) data.Specifically, each storage unit of memory cell array 2202 has multiple states, and these states It is to be distinguished with multiple reading voltages.

Fig. 8 is grid corresponding to the write-in data that are stored in memory cell array according to shown by an exemplary embodiment The statistics distribution diagram of voltage.

Fig. 8 is please referred to, by taking MLC NAND type flash memory as an example, the grid voltage in each storage unit can be according to One default voltage VA, the second default reading voltage VB and the third of reading is preset and reads voltage VC and divide into 4 kinds of storing states, and And these storing states respectively represent " 11 ", " 10 ", " 00 " and " 01 ".In other words, each storing state includes minimum having Imitate bit (Least Significant Bit, LSB) and highest significant bit (Most Significant Bit, MSB). In this exemplary embodiment, the value for the 1st bit counted in storing state (that is, " 11 ", " 10 ", " 00 " and " 01 ") from left side For LSB, and the value for the 2nd bit counted from left side is MSB.Therefore, in the first exemplary embodiment, each storage unit can Store 2 bit datas.It will be appreciated that grid voltage illustrated in fig. 8 and its storing state to should be only a model Example.In another exemplary embodiment of the present invention, grid voltage is corresponding with storing state can also be as grid voltage is bigger and It is arranged with " 11 ", " 10 ", " 01 " and " 00 ".Alternatively, storing state corresponding to grid voltage can also for physical holding of the stock value into Value after row mapping or reverse phase, in addition, also can define the value for the 1st bit counted from left side in another example in example For MSB, and the value for the 2nd bit counted from left side is LSB.

In the example that each storage unit can store 2 bit datas, the storage unit on same character line can structure At the storage space of 2 entity program units (that is, lower entity program unit and upper entity program unit).Namely It says, the LSB of each storage unit is corresponding lower entity program unit, and the MSB of each storage unit is corresponding upper entity Programmed cell.In addition, several entity program units can constitute an entity erased cell in memory cell array 2202, And entity erased cell is the minimum unit for executing running of erasing.That is, each entity erased cell contain minimal amount it The storage unit being erased together.

The data write-in (or being sequencing) of the storage unit of memory cell array 2202 is to utilize to bestow a particular end The voltage of point, e.g. control grid voltage catch the amount of electrons of layer to change the benefit of the charge in grid, thus change storage The on state in the channel of unit, different storing states is presented.For example, instantly the data of entity program unit be 1 and When the data of upper entity program unit are 1, it is single that the meeting control character line control circuit 2204 of control circuit 2212 does not change storage Grid voltage in member, and the storing state of storage unit is remained into " 11 ".Instantly the data of entity program unit be 1 and When the data of upper entity program unit are 0, character line control circuit 2204 can change under the control of control circuit 2212 to be deposited Grid voltage in storage unit, and the storing state of storage unit is changed into " 10 ".Instantly the data of entity program unit When data for 0 and upper entity program unit are 0, character line control circuit 2204 can change under the control of control circuit 2212 Become the grid voltage in storage unit, and the storing state of storage unit is changed into " 00 ".Also, entity program list instantly When the data of member are 0 and the data of upper entity program unit are 1, character line control circuit 2204 can be in control circuit 2212 The lower grid voltage changed in storage unit of control, and the storing state of storage unit is changed into " 01 ".

Fig. 9 is the schematic diagram of the sequencing storage unit according to shown by an exemplary embodiment.

Fig. 9 is please referred to, in this exemplary embodiment, the sequencing of storage unit is to be written/verify critical electricity by pulse Pressure method is completed.Specifically, when being intended to write data into storage unit, memorizer control circuit unit 104 can be set just Begin write-in voltage and write-in voltage pulse time, and indicates the control electricity of reproducible nonvolatile memorizer module 106 Sequencing storage unit is carried out using set being originally written into voltage and voltage pulse time is written in road 2212, to carry out data Write-in.Later, memorizer control circuit unit 104 will use verifying voltage to verify to storage unit, be deposited with judgement Whether storage unit has been in correct storing state.If storage unit is not programmed into correct storing state, memory Control circuit unit 104 indicates control circuit 2212 and adds an incremental step pulse program with the write-in voltage bestowed at present (Incremental-step-pulse programming, abbreviation ISPP) adjusted value (is also referred to as attached most importance to as new write-in voltage Make carbon copies into voltage) and carry out sequencing storage unit again according to new write-in voltage and write-in voltage pulse time.Conversely, if When storage unit has been programmed into correct storing state, then it represents that data have been correctly written to storage unit.For example, Being originally written into voltage can be set to 16 volts (Voltage, abbreviation V), and write-in voltage pulse time can be set to 18 microseconds (microseconds, abbreviation μ s) and incremental step pulse program adjusted value is set to 0.6V, however, the present invention is not limited thereto.

Figure 10 is the schematic diagram that data are read in the slave storage unit according to shown by an exemplary embodiment, is with MLC For NAND type flash memory.

Figure 10 is please referred to, the reading running of the storage unit of memory cell array 2202 is to read voltage in control by bestowing Check (control gate), by the channel of storage unit (path of the storage unit to be electrically connected bit line and source electrode line, E.g. cell source to drain between path) on state, come recognition memory cell storage data.Under reading In the running of the data of entity program unit, character line control circuit 2204 will use the first default voltage VA that reads as reading Voltage is taken come under bestowing to storage unit and whether be connected according to the channel of storage unit with corresponding expression formula (1) and judging The value of the data of entity program unit:

LSB=(VA) Lower_pre1 (1)

Wherein (VA) Lower_pre1 indicates the 1st lower entity program obtained and bestowing the first default reading voltage VA Change unit validation value.

For example, the channel of storage unit will not when the first default grid voltage for reading voltage VA less than storage unit The 1st lower entity program unit validation value of simultaneously output valve " 0 " is connected, it is 0 that thus LSB, which can be identified in first state,.Example Such as, when the first default grid voltage for reading voltage VA greater than storage unit, the channel of storage unit can be connected and output valve The lower entity program unit validation value in the 1st of " 1 ", it is 1 that this LSB, which can be identified in the second state, as a result,.Here, the first shape State is identified as " 0 " and the second state is identified as " 1 ".That is, to present LSB be 1 grid voltage with to The grid voltage that LSB is 0, which is presented, to be distinguished by the first default voltage VA that reads.

In the running for reading upper entity program cell data, character line control circuit 2204 can respectively use second The default reading voltage VB and default reading voltage VC of third bestows to storage unit and single according to storage as reading voltage Whether the channel of member is connected with corresponding expression formula (2) value for judging upper entity program cell data:

MSB=((VB) Upper_pre2) XOR (~(VC) Upper_pre1) (2)

Wherein (VC) Upper_pre1 is indicated by bestowing entity program on the obtain and third is default to read voltage VC the 1st Change unit validation value, and (VB) Upper_pre2 indicates real on the obtain and bestowing the second default reading voltage VB the 2nd Body programmed cell validation value, wherein symbol "~" represents reverse phase.In addition, being read in this exemplary embodiment when third is default When voltage VC is less than the grid voltage of storage unit, the channel of storage unit does not turn on and entity journey on the 1st of output valve ' 0' the Sequence unit validation value ((VC) Upper_pre1), when the second default grid voltage for reading voltage VB less than storage unit, The channel of storage unit does not turn on and entity program unit validation value ((VB) Upper_pre2) on the 2nd of output valve " 0 " the.

Therefore, according to expression formula (2), when the default reading voltage VB of the default reading voltage VC and second of third is smaller than stored When the grid voltage of unit, in the case where bestowing third default reading voltage VC, the channel of storage unit does not turn on simultaneously output valve " 0 " The 1st on entity program unit validation value and will not be led bestowing the second default channel for reading storage unit under voltage VB Entity program unit validation value on logical and output valve " 0 " the 2nd.At this point, MSB can be identified as second state of being in, that is, “1”。

For example, reading that voltage VC is greater than the grid voltage of storage unit and second default to read voltage VB small when third is default When the grid voltage of storage unit, in the case where bestowing third default reading voltage VC, the channel of storage unit can be connected and export Entity program unit validation value on the 1st of value ' 1', and bestow second it is default read voltage VB under storage unit channel Entity program unit validation value on the 2nd of simultaneously output valve " 0 " is not turned on.At this point, MSB can be identified as being in the first shape State, that is, " 0 ".

For example, reading the default grid voltage for reading voltage VB and being all greater than storage unit of voltage VC and second when third is default When, in the case where bestowing the default reading voltage VC of third, the channel of storage unit can be connected and entity program on the 1st of output valve " 1 " the Change unit validation value, and simultaneously output valve ' 1' can be connected in the channel of storage unit in the case where bestowing the second default reading voltage VB Entity program unit validation value on 2nd.At this point, MSB can be identified as second state of being in, that is, " 1 ".

It will be appreciated that although the present invention is explained with MLC NAND type flash memory.However, the present invention is not It is limited to this, other multilayered memory unit NAND type flash memories can also carry out the reading of data according to above-mentioned principle.

For example, Figure 11 is according to another exemplary embodiment by taking TLC NAND type flash memory as an example (as shown in figure 11) The schematic diagram of data is read in shown slave storage unit.Each storing state includes the 1st bit that left side is counted Intermediate significant bit (Center Significant Bit, the letter of minimum effective bit LSB, the 2nd counted from left side bit Claim CSB) and the highest significant bit MSB of the 3rd bit counted from left side, the wherein corresponding lower entity program unit of LSB, Entity program unit during CSB is corresponding, entity program unit in MSB correspondence.Grid in this example, in each storage unit Pole tension default can read voltage VA, second default read the default voltage VC, the 4th default of reading of voltage VB, third according to first Reading voltage VD, the 5th default reading voltage VE, the 6th default reading voltage VF and the 7th preset and read voltage VG and divide into 8 Kind storing state (that is, " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " and " 011 ").

Figure 12 A, Figure 12 B show with the example that Figure 12 C is the management entity erased cell according to shown by an exemplary embodiment It is intended to.

Figure 12 A is please referred to, memorizer control circuit unit 104 (or memory management circuitry 202) can be with entity program Unit is that unit carries out running being written and with reality come the storage unit 702 to reproducible nonvolatile memorizer module 106 Body erased cell carries out running of erasing for unit come the storage unit 702 to reproducible nonvolatile memorizer module 106.Tool For body, the storage unit 702 of reproducible nonvolatile memorizer module 106 can constitute multiple entity program units, and And these entity program units can constitute multiple entity erased cell 400 (0)~400 (N).Entity erased cell is erased Minimum unit.That is, each entity erased cell contains the storage unit of minimal amount being erased together.Entity program list Member is the minimum unit of sequencing.That is, an entity program unit is the minimum unit that data are written.Each entity program Unit generally includes data bit area and redundancy ratio special zone.Data bit area includes that multiple entity access addresses are used to store The data of person, and data (for example, control information and error correcting code) of the redundancy ratio special zone to stocking system.For example, with TLC For NAND quick-flash memory, the LSB of the storage unit on same character line can constitute a lower entity program list Member；The CSB of storage unit on same character line can constitute a middle entity program unit；And it is located at same The MSB of storage unit on character line can constitute a upper entity program unit.

Figure 12 B is please referred to, in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) entity erased cell 410 (0)~410 (N) can be logically grouped into data field 502, idle area 504, system area 506 with Replace area 508.The entity erased cell for logically belonging to data field 502 and idle area 504 is to store from host system The data of system 1000.Specifically, the entity that the entity erased cell of data field 502 is regarded as having stored data is erased list Member, and the entity erased cell in idle area 504 is the entity erased cell to replacement data area 502.That is, working as from master When machine system 1000 receives write instruction and the data to be written, memorizer control circuit unit 104 (or memory management electricity Road 202) entity erased cell can be extracted from idle area 504, and write data into extracted entity erased cell, With the entity erased cell in replacement data area 502.

The entity erased cell for logically belonging to system area 506 is to record system data.For example, system data includes Entity about the manufacturer of reproducible nonvolatile memorizer module and model, reproducible nonvolatile memorizer module Erased cell number, entity program unit number of each entity erased cell etc..

Logically belonging to replace the entity erased cell in area 508 is to replace program for bad entity erased cell, to take The entity erased cell of generation damage.Specifically, still there are normal entity erased cell and data field if replacing in area 508 When 502 entity erased cell damage, memory management circuitry 202 can extract normal entity in area 508 and erase list from replacing Member replaces the entity erased cell of damage.

In particular, the quantity meeting of data field 502, idle area 504, system area 506 and the entity erased cell for replacing area 508 It is different according to different memory specifications.Further, it is necessary to be appreciated that, in the running of memorizer memory devices 100, Entity erased cell is associated with to data field 502, idle area 504, system area 506 and replaces the grouping relationship in area 508 can be dynamically It changes.For example, when the entity erased cell that the entity erased cell damage in idle area 504 is substituted area 508 replaces, then Replace the entity erased cell in area 508 that can be associated to idle area 504 originally.

Figure 12 C is please referred to, memorizer control circuit unit 104 (or memory management circuitry 202) can configuration logic unit LBA (0)~LBA (H) is to map the entity erased cell of data field 502, wherein each logic unit has multiple logics single Member is to map the entity program unit of corresponding entity erased cell.Also, work as the logic to be write data to of host system 100 When the data that unit or update are stored in logic unit, memorizer control circuit unit 104 (or memory management circuitry 202) An entity erased cell can be extracted from idle area 504 data are written, with the entity erased cell of alternation data field 502. In this exemplary embodiment, logical subunit can be logical page (LPAGE) or logic sector.

In order to identify that the data of each logic unit are stored in that entity erased cell, in this exemplary embodiment, Memorizer control circuit unit 104 (or memory management circuitry 202) will record between logic unit and entity erased cell Mapping.Also, when host system 1000 is intended to access data in logical subunit, memorizer control circuit unit 104 (or deposit Reservoir manages circuit 202) it can confirm logic unit belonging to this logical subunit, and to type nonvolatile Module 106 assigns corresponding instruction sequence to access data in this logic unit mapped entity erased cell.For example, In this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can be non-volatile in duplicative Stored logic turns physical address mapping table to record each logic unit mapped entity and erase list in property memory module 106 Member, and when data to be accessed, logic can be turned entity by memorizer control circuit unit 104 (or memory management circuitry 202) Address mapping table is loaded into buffer storage 208 to safeguard.

Figure 13 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment.It has to be understood that , the structure of memorizer control circuit unit shown in Figure 13 is only an example, and invention is not limited thereto.

Figure 13 is please referred to, memorizer control circuit unit 104 includes memory management circuitry 202, host interface 204, deposits Memory interface 206 and error checking and correcting circuit 208.

Overall operation of the memory management circuitry 202 to control memorizer control circuit unit 104.Specifically, it deposits Reservoir, which manages circuit 202, has multiple control instructions, and when memorizer memory devices 100 operate, these control instruction meetings It is performed the running such as to carry out the write-in of data, read and erase.

In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with firmware pattern.For example, Memory management circuitry 202 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memorizer memory devices 100 operate, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.

In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also be with procedure code pattern The specific region of reproducible nonvolatile memorizer module 106 is stored in (for example, being exclusively used in storage system in memory module The system area of data) in.In addition, memory management circuitry 202 has microprocessor unit (not shown), read-only memory (not Show) and random access memory (not shown).In particular, this read-only memory has driving code, and when memory controls When circuit unit 104 is enabled, microprocessor unit can first carry out this driving code section, and will to be stored in duplicative non-volatile Control instruction in memory module 106 is loaded into the random access memory of memory management circuitry 202.Later, micro- place Reason device unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.

In addition, the control instruction of memory management circuitry 202 can also be with a hardware in another exemplary embodiment of the present invention Pattern carrys out implementation.For example, memory management circuitry 202 includes microcontroller, Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity Circuit is erased on road, memory reading circuitry, memory and data processing circuit is electrically connected to microcontroller.Wherein, it stores Entity erased cell of the Single Component Management circuit to manage reproducible nonvolatile memorizer module 106；Memory write-in electricity Road writes data into non-volatile to duplicative to assign write instruction to reproducible nonvolatile memorizer module 106 In property memory module 106；Memory reading circuitry refers to assign reading to reproducible nonvolatile memorizer module 106 It enables to read data from reproducible nonvolatile memorizer module 106；Memory erases circuit to non-to duplicative Volatile 106 assigns instruction of erasing so that data to be erased from reproducible nonvolatile memorizer module 106； And data processing circuit is intended to be written data to reproducible nonvolatile memorizer module 106 and from can make carbon copies to handle The data read in formula non-volatile memory module 106.

Host interface 204 is electrically connected to memory management circuitry 202 and to receive and identification host system 1000 instructions and data transmitted.That is, instruction and data that host system 1000 is transmitted can pass through host interface 204 are sent to memory management circuitry 202.In this exemplary embodiment, host interface 204 is to be compatible to USB standard.So And, it should be understood that the invention is not limited thereto, and host interface 204 is also possible to be compatible to PATA standard, the mark of IEEE 1394 Standard, PCI Express standard, SD standard, SATA standard, UHS-I interface standard, UHS-II interface standard, MS standard, MMC mark Standard, eMMC interface standard, UFS interface standard, CF standard, IDE standard or other suitable data transmission standards.

Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile to access duplicative Property memory module 106.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 106 can be via depositing Memory interface 206 is converted to the 106 receptible format of institute of reproducible nonvolatile memorizer module.

Error checking and correcting circuit 208 are electrically connected to memory management circuitry 202 and to execute a mistake Correction program is to ensure the correctness of data.Specifically, when memory management circuitry 202 is from duplicative non-volatile memories When reading data in device module 106, error checking and correcting circuit 208 can execute error-correcting routine to read data. For example, error checking and correcting circuit 208 are that low-density parity corrects (Low Density in this exemplary embodiment Parity Check, abbreviation LDPC) circuit, and record log-likelihood ratio (Log Likelihood Ratio, abbreviation can be stored LLR) value inquiry table.It is wrong when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106 Erroneous detection, which is looked into, can execute error correction journey according to corresponding LLR value in read data and inquiry table with correcting circuit 208 Sequence.Wherein, it is worth noting that in another exemplary embodiment, error checking and correcting circuit 208 can also be turbine code (Turbo Code) circuit.

In an exemplary embodiment of the invention, memorizer control circuit unit 104 further includes buffer storage 210 and power supply Manage circuit 212.

Buffer storage 210 is electrically connected to memory management circuitry 202 and is configured to temporarily store from host system 1000 data and instruction or the data from reproducible nonvolatile memorizer module 106.

Electric power management circuit 212 is electrically connected to memory management circuitry 202 and to control memory storage dress Set 100 power supply.

Figure 14 is according to shown by an exemplary embodiment when the multiple sequencing of storage unit and to be stored in storage after erasing single The statistics distribution diagram of grid voltage corresponding to write-in data in element array.It is noted that corresponding to this storage unit Grid voltage statistics distribution diagram be alternatively referred to as this storage unit critical voltage distribution.The present invention is general for ease of description Read, come by taking the lower entity program unit that the LSB in the storage unit of MLC NAND quick-flash memory is constituted as an example below Do example.

Figure 14 is please referred to, the grid voltage in each storage unit can divide into 2 according to the first default reading voltage VA Kind storing state (as shown in the block curve of Figure 14), and these storing states respectively represent " 1 " and " 0 ".

In general, when being intended to read data from storage unit, memorizer control circuit unit 104 (or memory pipe Reason circuit 202) reading instruction can be assigned to reproducible nonvolatile memorizer module 106, and duplicative is non-volatile The control circuit 2212 of memory module 106 can bestow default reading electricity to the character line for being connected to the storage unit to be read Pressure, to verify the channel storing state of storage unit.In addition to this, multiple scanning voltages can also be bestowed to character line, from this The verifying bit value of corresponding each scanning voltage is read in multiple storage units that character line is connected.Then, it calculates separately pair It answers in the verifying bit of multiple scanning voltages, the multiple first state bit datas for being identified as the bit data of first state increase Dosage.It finally can be according to these first state bit data incrementss to obtain the storage that this character line is recognized as first state The critical voltage of unit is distributed, and similarly, also this available character line is recognized as the critical voltage of the storage unit of the second state Distribution.However, causing critical voltage distributions shift to have several possibility, for example, data are long placed in, storage unit abrasion and reading are dry It disturbs.For being deviated caused by being long placed in this measure data, since data are placed for a long time, so that type nonvolatile The critical voltage distributions shift (as shown in the dotted line of Figure 14) of the storage unit 702 of module 106 causes the first default reading voltage VA can not correctly identify the storing state of storage unit.That is, (if hereinafter referred to as first deposits the storage unit in Figure 14 Storage unit) grid voltage when being programmed, be the verifying bit status for being programmed for " 0 " so that first storage The grid voltage of unit can be greater than the first default reading voltage VA.Therefore voltage VA is read to obtain first when presetting using first When the verifying bit of storage unit, the verifying bit status of " 0 " should be obtained originally, but because of the distribution of critical voltage Offset leads to the verifying bit status for obtaining " 1 " of mistake.

When memorizer control circuit unit 104 (or memory management circuitry 202) is to first comprising the first storage unit When character line presets reading voltage VA using first to be read, due to the distributions shift of critical voltage, it will lead to The verifying bit of multiple storage units of the first acquired character line is wrong.That is, working as a storage unit Verify bit-errors, just represent 1 stored by this storage unit bit data be it is wrong, 1 mistake will also occur Bit.As soon as representing when mistake occurs for the verifying bit read out from multiple storage units of character line from this character line The data read out have multiple error bits.And when the error bits numbers of read data are more than error checking and correction When the protective capability of circuit 208, will lead to data can not correctly be decoded, and generate wrong data.

In this exemplary embodiment, in the case where the distribution of critical voltage has deviated, memorizer control circuit unit 104 (or deposit Reservoir manages circuit 202) it can be adjusted according to the first default reading voltage VA to obtain successfully to correct and be read Data voltage (hereinafter referred to as first available read voltage VVA).That is, bestowing the first available voltage that reads to first Read data can be corrected successfully by error checking with correcting circuit 208 on character line.In particular, successful correction is logical After crossing the first available reading read data of voltage VVA (hereinafter referred to as the first page data), memorizer control circuit unit 104 (or memory management circuitry 202) judges the used first available voltage VVA and first that reads and presets reading voltage VA's Whether the first difference DV is greater than the first predetermined threshold level.When the first difference DV is greater than the first predetermined threshold level, memory control Circuit unit 104 (or memory management circuitry 202) can send an instruction sequence, indicate type nonvolatile mould Multiple storage units that first page Data programming to another character line is connected are formed by an entity program list by block In member (for example, multiple storage units that the second character line is connected are formed by first instance programmed cell).And complete In pairs after the programming operations of the first page data, (hereinafter referred to as the first logic of logical subunit belonging to the first page data Subelement) the first instance programmed cell of above-mentioned second character line can be re-mapped to.And it is above-mentioned according to judgement used The first available the first difference DV for reading the default reading voltage VA of voltage VVA and first whether be greater than the first predetermined threshold level As a result, being formed by an entity program with the multiple storage units for being connected first page Data programming to another character line Change the operation in unit, alternatively referred to as reading interference protection operation (Read disturb protection).

It is noted that in this exemplary embodiment being preset by comparing the first available voltage VVA and first that reads Read whether the first difference DV between voltage VA is greater than the first predetermined threshold level to determine whether executing reading interference protection behaviour Make, however, the invention is not limited thereto.For example, in an exemplary embodiment of the invention, when reading data, memory control electricity Road unit 104 (or memory management circuitry 202) can obtain the first available reading voltage by reading table again.Therefore, in this hair In bright another exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can also be read again according to executing Number to determine whether execute reading interference protection operation.

Figure 15 is the schematic diagram of the stressed table according to shown by this exemplary embodiment.

Figure 15 is please referred to, for ease of description, Figure 15 is a stressed table 1501 (Retrytable) simplified, note The voltage that record is adjusted every time when carrying out stressed to the LSB in the storage unit of a character line, and only define ten times and read again Operation.It will be appreciated that stressed table can store needed for the stressed operation for more numbers in other exemplary embodiments Adjustment voltage, and record the stressed adjustment voltage for other bits (for example, MSB, CSB) in storage unit.

In the stressed table 1501 of Figure 15, reading number of operations field 1503 again is to record to read number again, and adjust voltage Field 1505 is the voltage value (hereinafter referred to as first reads voltage change) for recording corresponding stressed number and being adjusted, and unit is Volt (Voltage).For example, #1 is read again for the first time, and corresponding adjustment voltage is -0.3V, and so on, #2 is Second stressed, and corresponding adjustment voltage is -0.5V.For example, (or the memory of memorizer control circuit unit 104 Management circuit 202) use the first default page data (hereinafter referred to as the first number of pages for reading voltage VA and reading from the first character line According to) can not be by error correction when, memorizer control circuit unit 104 (or memory management circuitry 202) can indicate duplicative Non-volatile memory module 106 carries out reading operation again according to stressed table 1501, that is, when carrying out the stressed operation of first time, The first default reading voltage VA is adjusted using the first reading voltage change in stressed table 1501.If default using first Read voltage VA plus first reading voltage change after voltage value (such as: VA+ (- 0.3)) be read, read The first page data out can correctly be corrected by error checking and correcting circuit 208, then this voltage value is just the first available reading Take voltage.But memorizer control circuit unit 104 (or memory management circuitry 202) is not necessarily carrying out for the first time When reading operation again, used first, which reads adjustment voltage, will allow the first page data to be correctly corrected, and store at this time Device control circuit unit 104 (or memory management circuitry 202) will carry out second and read operation # again according to stressed table 1501 2, third time reads operation #3 or the 4th time again and reads operation #4 again, and so on, until the first page data can be by correctly school Just.When used voltage can allow the first page data correctly to be corrected, then used voltage is first available at this time Read voltage VVA, that is to say, that memorizer control circuit unit 104 (or memory management circuitry 202) can be according to stressed table 1501 carry out reading operation again, available read voltage VVA to obtain first.It is noted that when using the first default reading When voltage can correctly read the first page data, then do not have to carry out reading operation again, the default voltage that reads of first at this time is First available reading voltage VVA.

In this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can be according to The number of operation read again to judge that the used first available reading voltage VVA and first is default and read the first of voltage VA Whether difference DV is greater than the first predetermined threshold level.For example, Figure 15 is please referred to, in Figure 15, reads operation #4 again the 4th time 4th to read adjustment voltage be -1V, and it is -1.3V that the 5th time, which is read again the 5th of operation #5 to read adjustment voltage, that is to say, that the Five voltage adjustment for reading the stressed operation carried out in operation #5 again are to preset to read voltage and do according to first to subtract each other, with emphatically Read number increase, the voltage value subtracted each other can be bigger, at this time institute voltage value adjusted with first preset reading voltage difference just It can be bigger.On the other hand, operation #6 to the tenth times voltage tune for reading the stressed operation that operation #10 is carried out again is read again at the 6th time Whole is to be added according to the first default voltage that reads, and as stressed number increases, the voltage value of addition can be bigger, is adjusted at this time Voltage value after whole will be bigger with the first default difference for reading voltage.And memorizer control circuit unit 104 (or memory Manage circuit 202), such as above-mentioned example can pre-define, and operate when read again to obtain the first available number for reading voltage Greater than three and when being less than or equal to five, or when being greater than eight and being less than or equal to ten, memorizer control circuit unit 104 (or is deposited at this time Reservoir management circuit 202) the used first available first for reading voltage VVA and first and presetting reading voltage VA will be recognized Difference DV is greater than the first predetermined threshold level.If conversely, memorizer control circuit unit 104 (or memory management circuitry 202) Read again operation, the first available number for reading voltage is less than or equal to three or this number is greater than five and is less than etc. to obtain When eight, memorizer control circuit unit 104 (or memory management circuitry 202) will identify the used first available reading Default the first difference DV for reading voltage VA of voltage VVA and first is non-to be greater than the first predetermined threshold level.

That is, in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) It can identify and whether execute stressed number between certain two preset times (hereinafter referred to as the first preset times and second default time Number) between, and if so, the first available reading voltage VVA and first is default used in identification reads the first of voltage VA Difference DV is non-to be greater than the first predetermined threshold level.

It is inclined between the first available default reading voltage VA of reading voltage VVA and first in addition to being identified according to number is read again It moves except range, in another exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can also The used first available first for reading voltage VVA and first and presetting reading voltage VA is judged to be distributed according to critical voltage Whether difference DV is greater than the first predetermined threshold level.

Figure 16 is the schematic diagram of the distribution of the critical voltage according to shown by another exemplary embodiment.

Specifically, Figure 16 is please referred to, in this another exemplary embodiment, memorizer control circuit unit 104 (or storage Device manages circuit 202) can search one of peak value P in established critical voltage distribution with and this peak value P it is adjacent One valley Q, and valley Q is calculated divided by peak value P ratio obtained.When the calculated ratio of institute is greater than an estimated rate, Then memorizer control circuit unit 104 (or memory management circuitry 202) can identify the first available reading electricity used in judgement Default the first difference DV for reading voltage VA of VVA and first is pressed to be greater than the first predetermined threshold level.

For example, when memorizer control circuit unit 104 (or memory management circuitry 202) is established for the first character When the critical voltage distribution of line, it can then compare the ratio of peak value P and adjacent valley Q.For example, if valley Q is divided by peak value P institute When obtained ratio is more than estimated rate, then memorizer control circuit unit 104 (or memory management circuitry 202) can recognize institute Available default the first difference DV for reading voltage VA of voltage VVA and first that reads of first used is greater than the first predetermined threshold level. Then, memorizer control circuit unit 104 (or memory management circuitry 202) can execute reading interference protection, i.e., by first page The step of face re-writes to another entity program unit.For example, can be set as 5%, but this hair in this estimated rate It is bright without being limited thereto.

Furthermore in another exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) Be recordable in the error bits numbers of read data in different scanning voltages, and calculate minimum error bits numbers with Maximum number of error bits purpose ratio is (i.e. by minimum error bits numbers divided by maximum calculated one of error bits numbers institute Ratio).Also, when this ratio is greater than estimated rate, memorizer control circuit unit 104 (or memory management circuitry 202) Just it is default to be greater than first by the first available default the first difference DV for reading voltage VA of reading voltage VVA and first used in identification Threshold value.

Figure 17 is the flow chart of the data storage method according to shown by this exemplary embodiment, wherein being in storage unit LSB for be illustrated.

Figure 17 is please referred to, in step S1701, memorizer control circuit unit 104 (or memory management circuitry 202) meeting It is received from host system and reads instruction (hereinafter referred to as first reads instruction).

Later, in step S1703, memorizer control circuit unit 104 (or memory management circuitry 202) can be according to the One reads the corresponding character line (hereinafter referred to as the first character line) of instruction identification and pre- according to first for the first character line If reading voltage VA to obtain the first available reading voltage VVA.

Then, in step S1705, memorizer control circuit unit 104 (or memory management circuitry 202) uses first The first character line can be read with voltage VVA is read, to obtain the first page data.Here, memorizer control circuit Unit 104 (or memory management circuitry 202) can be corrected successfully with the first available reading read first number of pages of voltage VVA Instruction is read by the data back after correction to host system according to and according to first.

Then, in step S1707, memorizer control circuit unit 104 (or memory management circuitry 202) judges institute It is default whether available the first difference DV read between the default reading voltage VA of voltage VVA and first of first used is greater than first Threshold value.

If the used first available default the first difference DV for reading voltage VA of voltage VVA and first that reads is greater than first When predetermined threshold level, in step S1709, memorizer control circuit unit 104 (or memory management circuitry 202) can be by first Page data sequencing into the first instance programmed cell of the second character line, and by the first logic belonging to the first page data Unit is remapped to the first instance programmed cell of the second character line.That is, carrying out above-mentioned reading interference protects operation.

It is greater than the if the used first available the first difference DV for reading the default reading voltage VA of voltage VVA and first is non- One predetermined threshold level, then memorizer control circuit unit 104 (or memory management circuitry 202) will not read the first page data Interference protection is taken to operate.

It will be appreciated that although Figure 17 is to show reading with the LSB in the storage unit of MLC NAND quick-flash memory It is illustrated for the lower entity program unit constituted, however the method can also be applied to read the storage of MLC NAND Flash In the storage unit of upper entity program unit or TLC NAND quick-flash memory that MSB in the storage unit of device is constituted The middle entity program unit that is constituted of CSB.For example, reading the upper entity program for being stored in MLC NAND quick-flash memory In the example for changing the second page data of unit, if reading ratio acquired in voltage VC by bestowing the second reading voltage VB and third Special data can not by decoding and when obtaining corresponding second page data, memorizer control circuit unit 104 (or memory management electricity Road 202) it will use the corresponding second reading voltage for reading voltage change and reading voltage VC with corresponding third for reading voltage VB Adjusted value is preset to adjust separately the second default reading voltage VB and third and reads voltage VC, and with reading voltage adjusted (that is, the second available voltage and third of reading can be with reading voltage) can error correction come the acquisition from upper entity program unit Second page data.Then from judging that the second available voltage and third of reading default can read electricity with reading voltage and whether deviate second Pressure and third is default reads except voltage to a certain range, come recognize whether will be to being stored in the of upper entity program unit Two page datas are read out interference protection operation.

In conclusion the data storage method of above-mentioned exemplary embodiment, memorizer control circuit unit and memory store up Cryopreservation device is when the critical voltage distribution for judging storage unit has been deviated more than a range, to being stored in this storage unit Data carry out efficient protection operation, thus can be effectively prevented from Missing data.In addition, the data of above-mentioned exemplary embodiment Storage method, memorizer control circuit unit and memorizer memory devices be critical voltage distribution deviated really it is excessive under It executes and reads protection operation, thus reduce the number for being read out protection operation and reduce type nonvolatile mould Block loss.Therefore, the service life of reproducible nonvolatile memorizer module can be effectively extended.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims (21)

1. a kind of data storage method is used for a reproducible nonvolatile memorizer module, which is characterized in that the duplicative Non-volatile memory module has a multiple storage units, a plurality of character line and a plurality of bit line, each of storage unit with A wherein character line for those character lines and a wherein bit line for those bit lines are electrically connected, each of storage Unit can store multiple bit datas, and each of bit data can be identified as according to an at least voltage first state or One second state, the data storage method include:

In multiple storage units that one first character line of one Data programming into those character lines is connected, wherein one The one default voltage that reads initially is set for first character line；

The first default reading voltage is adjusted to obtain the one first available reading voltage for first character line and bestow This first can with read voltage one first page data is read to first character line, wherein first page data be can by one mistake Erroneous detection is looked into correctly to be corrected with correcting circuit；

Multiple scanning voltages are bestowed, correspond to each of sweep to read from those storage units for be connected to first character line Retouch multiple scanning bit datas of voltage；And

According to multiple scanning bit data to determine whether by the first page Data programming into those character lines one the In multiple storage units that two character lines are connected.

2. data storage method according to claim 1, which is characterized in that further include:

One first logical subunit belonging to first page data is remapped to a first instance programmed cell,

Those storage units that wherein second character line is connected form multiple entity program units, and the first instance Programmed cell is one of those entity program units.

3. data storage method according to claim 1, which is characterized in that adjust the first default voltage that reads to obtain This for first character line first available read voltage and bestows the first available voltage that reads to first character line It include executing one according to a stressed table to read running again come the step of reading first page data.

4. data storage method according to claim 3, which is characterized in that read table again according to this and execute the stressed running Step includes:

Table is read again according to this after executing this and reading running at least once again and obtains one first reading voltage change；And

The first default reading voltage is adjusted according to the first reading voltage change to obtain the first available reading voltage.

5. data storage method according to claim 4, which is characterized in that further include:

Judge to execute whether the number for reading running again is greater than one first preset number and is less than or equal to one second preset number；With And

If executing the number for reading running again greater than first preset number and when being less than or equal to second preset number, identify The first available voltage and first default one first difference read between voltage of reading is greater than one first predetermined threshold level.

6. data storage method according to claim 1, which is characterized in that further include:

Respectively calculate the bit data for being identified as the first state in the scanning bit data of those corresponding scanning voltages Multiple first state bit data incrementss；

Those of first character line are obtained according to those first state bit data incrementss of those corresponding scanning voltages to deposit One critical voltage of storage unit is distributed；

Search the peak value and a valley adjacent with the peak value in critical voltage distribution；

Judge the valley obtaining whether a ratio is greater than one first estimated rate divided by the peak value；And

If the ratio is greater than first estimated rate, the first available reading voltage and the first default reading voltage are identified Between one first difference be greater than one first predetermined threshold level.

7. data storage method according to claim 1, which is characterized in that further include:

The multiple scanning bit datas for respectively corresponding those scanning voltages are read out from first character line；

Record respectively corresponds multiple error bits numbers of those scanning bit datas；

Judge to be obtained the minimal error bit number in those error bits numbers divided by a maximum error bits numbers Whether one error bits numbers ratio is greater than one second estimated rate；And

If the error bits numbers ratio is greater than second estimated rate, identify this first it is available read voltage and this first Default one first difference read between voltage is greater than one first predetermined threshold level.

8. a kind of memorizer control circuit unit, for accessing a reproducible nonvolatile memorizer module, which is characterized in that The memorizer control circuit unit includes:

One host interface is electrically connected to a host system；

One memory interface is electrically connected to the reproducible nonvolatile memorizer module, and wherein the duplicative is non- Volatile has a multiple storage units, a plurality of character line and a plurality of bit line, each of storage unit with should A wherein character line for a little character lines and a wherein bit line for those bit lines are electrically connected, and each of storage is single Member can store multiple bit datas, and each of bit data can be identified as a first state or one according to an at least voltage Second state；And

One memory management circuitry is electrically connected to the host interface and the memory interface, and to assign one first finger Enable sequence to the reproducible nonvolatile memorizer module with one first word by a Data programming into those character lines In multiple storage units that symbol line is connected, wherein the one first default voltage that reads initially is set for first character Line,

Wherein the memory management circuitry is also to adjust the first default voltage that reads to obtain for first character line One first can be used reading voltage and assign one second instruction sequence to the reproducible nonvolatile memorizer module to bestow This first can with read voltage one first page data is read to first character line, wherein first page data be can by one mistake Erroneous detection is looked into correctly to be corrected with correcting circuit,

Wherein the memory management circuitry is also to bestow multiple scanning voltages, with from be connected to first character line those deposit Multiple scanning bit datas of corresponding each of scanning voltage are read in storage unit；And

Wherein the memory management circuitry also to according to multiple scanning bit data to determine whether by first page data In multiple storage units that one second character line of the sequencing into those character lines is connected.

9. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry also to One first logical subunit belonging to first page data is remapped to a first instance programmed cell,

Those storage units that wherein second character line is connected form multiple entity program units, and the first instance Programmed cell is one of those entity program units.

10. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also used It executes one to assign one the 4th instruction sequence to the reproducible nonvolatile memorizer module according to a stressed table and reads fortune again Make, to read data from the storage unit that first character line is connected.

11. memorizer control circuit unit according to claim 10, which is characterized in that the memory management circuitry is being held Row at least once this read again running after according to this read again table obtain one first read voltage change,

Wherein the memory management circuitry adjusts the first default voltage that reads according to the first reading voltage change to obtain Obtain the first available reading voltage.

12. memorizer control circuit unit according to claim 11, which is characterized in that memory management circuitry judgement Execute whether the number for reading running again is greater than one first preset number and is less than or equal to one second preset number,

If wherein executing the number for reading running again greater than first preset number and when being less than or equal to second preset number, The memory management circuitry identifies that first available one first difference read between voltage and the first default reading voltage is big In one first predetermined threshold level.

13. memorizer control circuit unit according to claim 8, which is characterized in that

Wherein the memory management circuitry, which respectively calculates in the scanning bit data for corresponding to those scanning voltages, is identified as this Multiple first state bit data incrementss of the bit data of first state,

Wherein the memory management circuitry is obtained according to those first state bit data incrementss of those corresponding scanning voltages One critical voltage of those storage units of first character line is distributed,

Wherein the memory management circuitry searches the peak value and a valley adjacent with the peak value in critical voltage distribution,

Whether wherein the memory management circuitry judges the valley obtaining a ratio divided by the peak value is greater than one first and makes a reservation for Ratio,

If wherein the ratio is greater than first estimated rate, which identifies the first available reading voltage It is greater than one first predetermined threshold level with first default one first difference read between voltage.

14. memorizer control circuit unit according to claim 8, which is characterized in that

Wherein the memory management circuitry reads out the multiple scanning ratios for respectively corresponding those scanning voltages from first character line Special data,

Wherein memory management circuitry record respectively corresponds multiple error bits numbers of those scanning bit datas,

Wherein the memory management circuitry judges the minimal error bit number in those error bits numbers divided by one most Serious mistake bit number obtains whether an error bits numbers ratio is greater than one second estimated rate,

If wherein the error bits numbers ratio be greater than second estimated rate, the memory management circuitry identify this first One first predetermined threshold level can be greater than with one first difference read between voltage and the first default reading voltage.

15. a kind of memorizer memory devices characterized by comprising

One connecting interface unit, is electrically connected to a host system；

One reproducible nonvolatile memorizer module, wherein the reproducible nonvolatile memorizer module has multiple storages A wherein character line for unit, a plurality of character line and a plurality of bit line, each of storage unit and those character lines and A wherein bit line for those bit lines is electrically connected, and each of storage unit can store multiple bit datas, and each Those bit datas can be identified as a first state or one second state according to an at least voltage；And

One memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile mould Block, and in multiple storage units to be connected one first character line of the Data programming into those character lines, Wherein the one first default voltage that reads initially is set for first character line,

Wherein the memorizer control circuit unit is also used for first character to adjust the first default reading voltage to obtain The one first of line first to first character line can read a first page with voltage is read with reading voltage and bestowing this Data, wherein first page data is can correctly to be corrected by an error checking with correcting circuit,

Wherein the memorizer control circuit unit is also to be distributed according to a critical voltage to judge the first available reading voltage When being greater than first predetermined threshold level with first default one first difference read between voltage, the memorizer control circuit list Multiple storage units of the member also to be connected one second character line of the first page Data programming into those character lines In.

16. memorizer memory devices according to claim 15, which is characterized in that the memorizer control circuit unit is also used Remapping one first logical subunit belonging to first page data to a first instance programmed cell,

Those storage units that wherein second character line is connected form multiple entity program units, and the first instance Programmed cell is one of those entity program units.

17. memorizer memory devices according to claim 15, which is characterized in that the memorizer control circuit unit is also used Running is read again to execute one according to a stressed table, to read data from the storage unit that first character line is connected.

18. memorizer memory devices according to claim 17, which is characterized in that the memorizer control circuit unit is being held Row at least once this read again running after according to this read again table obtain one first read voltage change,

Wherein the memorizer control circuit unit adjusts the first default reading voltage according to the first reading voltage change To obtain the first available reading voltage.

19. memorizer memory devices according to claim 18, which is characterized in that the memorizer control circuit unit judges Execute whether the number for reading running again is greater than one first preset number and is less than or equal to one second preset number,

If wherein executing the number for reading running again greater than first preset number and when being less than or equal to second preset number, The memorizer control circuit unit identify this first it is available read voltage and this first it is default read between voltage this is first poor Value is greater than first predetermined threshold level.

20. memorizer memory devices according to claim 15, which is characterized in that the memorizer control circuit unit is bestowed Multiple scanning voltages are each to read correspondence from those storage units for be connected to first character line to first character line Multiple scanning bit datas of those scanning voltages,

Wherein the memorizer control circuit unit respectively calculates identified in the scanning bit data of those corresponding scanning voltages For multiple first state bit data incrementss of the bit data of the first state,

Wherein the memorizer control circuit unit is according to those first state bit data incrementss for corresponding to those scanning voltages The critical voltage distribution of those storage units of first character line is obtained,

Wherein the memorizer control circuit unit searches the peak value in critical voltage distribution and a paddy adjacent with the peak value Value,

Wherein the valley is obtained whether a ratio is greater than one first divided by the peak value by the memorizer control circuit unit judges Estimated rate,

If wherein the ratio is greater than first estimated rate, which identifies the first available reading Voltage and first default first difference read between voltage are greater than first predetermined threshold level.

21. memorizer memory devices according to claim 15, which is characterized in that

Wherein the memorizer control circuit unit bestows multiple scanning voltages to first character line, to read from first character line The multiple scanning bit datas for respectively corresponding those scanning voltages are taken out,

Wherein the memorizer control circuit unit record respectively corresponds multiple error bits numbers of those scanning bit datas,

Wherein the memorizer control circuit unit judges by the minimal error bit number in those error bits numbers divided by One maximum error bits numbers obtain whether an error bits numbers ratio is greater than one second estimated rate,

If wherein the error bits numbers ratio is greater than second estimated rate, memorizer control circuit unit identification should The first available voltage and first default first difference read between voltage of reading is greater than first predetermined threshold level.