CN106158040B - Read voltage quasi position estimating and measuring method, memory storage apparatus and control circuit unit - Google Patents

Read voltage quasi position estimating and measuring method, memory storage apparatus and control circuit unit Download PDF

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Publication number
CN106158040B
CN106158040B CN201510189551.1A CN201510189551A CN106158040B CN 106158040 B CN106158040 B CN 106158040B CN 201510189551 A CN201510189551 A CN 201510189551A CN 106158040 B CN106158040 B CN 106158040B
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unit
quasi position
decoding
voltage quasi
control circuit
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CN106158040A (en
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林纬
王天庆
赖国欣
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

The present invention provides a kind of reading voltage quasi position estimating and measuring method, memory storage apparatus and control circuit unit.The described method includes: the first area in reproducible nonvolatile memorizer module is read according to the first reading voltage quasi position, to obtain the first coding unit, wherein first coding unit belongs to block code；First decoding program is executed to first coding unit and records the first decoded information；The first area is read according to the second reading voltage quasi position, to obtain the second coding unit, wherein second coding unit belongs to the block code；Second decoding program is executed to second coding unit and records the second decoded information；And third is estimated and obtained according to first decoded information and second decoded information and reads voltage quasi position.Whereby, the managerial ability for using the reproducible nonvolatile memorizer module of block code can be promoted.

Description

Read voltage quasi position estimating and measuring method, memory storage apparatus and control circuit unit
Technical field
The invention relates to a kind of storage management methods, and in particular to a kind of reading voltage quasi position estimation side Method, memory storage apparatus and control circuit unit.
Background technique
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data It is non-volatile, power saving, small in size, and without characteristics such as mechanical structures, so being very suitable to be built into above-mentioned illustrated various In portable multimedia device.
In general, it in order to ensure the correctness of data, is deposited being written a certain data to duplicative is non-volatile Before memory modules, this data can be encoded.And the data after encoding can be written into type nonvolatile mould In block.When being intended to read this data, the data after coding can be read out and be decoded.If data can be solved successfully Code indicates that the number of error bit therein is few and these error bits can be corrected.However, if data can not be successfully Decoding (that is, decoding failure), then different reading voltage may be used to re-read data.But in some cases, Even if available multiple reading voltages were used, the data read out still can not be successfully decoded, and be caused Reading data failure.In particular, such situation is even more serious for the data for using block code to be encoded.
Summary of the invention
The present invention provides a kind of reading voltage quasi position estimating and measuring method, memory storage apparatus and control circuit unit, can mention Rise the managerial ability for using the reproducible nonvolatile memorizer module of block code.
One example of the present invention embodiment provides a kind of reading voltage quasi position estimating and measuring method, and it is non-volatile to be used for duplicative Property memory module, the reading voltage quasi position estimating and measuring method includes: to be read described to answer according to the first reading voltage quasi position The first area in formula non-volatile memory module is write, to obtain the first coding unit, wherein the first coding unit category In block code；First decoding program is executed to first coding unit and records the first decoded information；It is read according to second Voltage quasi position reads the first area, to obtain the second coding unit, wherein second coding unit belongs to the area Block code；Second decoding program is executed to second coding unit and records the second decoded information；And according to described first Decoded information is estimated and is obtained third with second decoded information and reads voltage quasi position.
In one example of the present invention embodiment, the block code is made of multiple sub- coding units, the sub- coding list The first bit in member is determined by multiple coded programs.
In one example of the present invention embodiment, the coded program has different coding directions.
In one example of the present invention embodiment, first decoded information includes the first numerical value, the second decoding letter Breath includes second value, wherein estimating and obtaining the third according to first decoded information and second decoded information The step of reading voltage quasi position includes: the first numerical value described in comparison and the second value and is determined according to comparison result described Third reads voltage quasi position.
In one example of the present invention embodiment, the first decoding result of first numerical value and first decoding program Related, the second value is related with the second decoding result of second decoding program.
In one example of the present invention embodiment, first numerical value is be positively correlated with first decoding program first Successfully decoded unit number, the second value are the second successfully decoded unit numbers for being positively correlated with second decoding program.
In one example of the present invention embodiment, the reading voltage quasi position estimating and measuring method further include: according to described first Decoding result obtains the first row successfully decoded unit number and first row successfully decoded unit number；According to the first row successfully decoded Unit number determines first numerical value with the first row successfully decoded unit number；The is obtained according to second decoding result Two row successfully decoded unit numbers and secondary series successfully decoded unit number；And according to the second row successfully decoded unit number and institute Secondary series successfully decoded unit number is stated to determine the second value.
In one example of the present invention embodiment, estimated according to first decoded information with second decoded information And obtaining the step of third reads voltage quasi position includes: to read voltage quasi position and described second for described first to read voltage One of level is determined as the third and reads voltage quasi position.
In one example of the present invention embodiment, the reading voltage quasi position estimating and measuring method further include: judge described first Whether decoding program fails, wherein reading voltage quasi position according to described second to be to determine the step of reading the first area It is executed after the first decoding program failure.
In one example of the present invention embodiment, the reading voltage quasi position estimating and measuring method further include: according to the third Voltage quasi position is read to execute predetermined registration operation related with the reproducible nonvolatile memorizer module, wherein described default Operation includes at least one of following operation: reading the first area to obtain and correspond to the multiple of third decoding unit Soft bit simultaneously executes iterative decoding to the third decoding unit according to the soft bit；It determines more in the first area The voltage's distribiuting state of the extent of deterioration of a storage unit or the storage unit；And it determines to correspond to the first area Pre-set programs voltage.
In one example of the present invention embodiment, the reading voltage quasi position estimating and measuring method further include: according to the third Voltage quasi position is read to read the first area, to obtain third coding unit；And the third coding unit is executed Third decoding program.
In one example of the present invention embodiment, first decoding program and second decoding program are all hard bit Mode decoding.
Another example of the present invention embodiment provides a kind of memory storage apparatus comprising connecting interface unit can answer Write formula non-volatile memory module and memorizer control circuit unit.The connecting interface unit is electrically connected to host System.The memorizer control circuit unit is electrically connected to the connecting interface unit and the duplicative is non-volatile deposits Memory modules.Wherein the memorizer control circuit unit is to send the first reading instruction sequence, wherein described first reads Instruction sequence is read in the reproducible nonvolatile memorizer module to indicate according to the first reading voltage quasi position First area, to obtain the first coding unit, wherein first coding unit belongs to block code, wherein the memory controls Circuit unit is also to execute the first decoding program to first coding unit and record the first decoded information, wherein described Memorizer control circuit unit is also to send the second reading instruction sequence, wherein described second reads instruction sequence to indicate The first area is read according to the second reading voltage quasi position, to obtain the second coding unit, wherein second coding is single Member belongs to the block code, wherein the memorizer control circuit unit is also to execute the second solution to second coding unit Coded program and the second decoded information of record, wherein the memorizer control circuit unit according to first decoding also to believe Breath is estimated and is obtained third with second decoded information and reads voltage quasi position.
In one example of the present invention embodiment, the block code is made of multiple sub- coding units, the sub- coding list The first bit in member is determined by multiple coded programs.
In one example of the present invention embodiment, the coded program has different coding directions.
In one example of the present invention embodiment, first decoded information includes the first numerical value, the second decoding letter Breath includes second value, wherein the memorizer control circuit unit is believed according to first decoded information and second decoding Cease read to estimate and obtain the third voltage quasi position operation include: the first numerical value described in comparison and the second value simultaneously Determine that the third reads voltage quasi position according to comparison result.
In one example of the present invention embodiment, the first decoding result of first numerical value and first decoding program Related, the second value is related with the second decoding result of second decoding program.
In one example of the present invention embodiment, first numerical value is be positively correlated with first decoding program first Successfully decoded unit number, the second value are the second successfully decoded unit numbers for being positively correlated with second decoding program.
In one example of the present invention embodiment, the memorizer control circuit unit is also to according to first decoding As a result the first row successfully decoded unit number and first row successfully decoded unit number are obtained, wherein the memorizer control circuit unit Also to determine first number according to the first row successfully decoded unit number and the first row successfully decoded unit number Value, wherein the memorizer control circuit unit is also to obtain the second row successfully decoded unit according to second decoding result Several and secondary series successfully decoded unit number, wherein the memorizer control circuit unit according to second row also to be decoded into Function unit number determines the second value with the secondary series successfully decoded unit number.
In one example of the present invention embodiment, the memorizer control circuit unit according to first decoded information with The operation that second decoded information reads voltage quasi position to estimate and obtain the third includes: to read voltage for described first One of level and the second reading voltage quasi position are determined as the third and read voltage quasi position.
In one example of the present invention embodiment, the memorizer control circuit unit is also to judge first decoding Whether program fails, wherein it is to determine that the memorizer control circuit unit, which sends the operation that described second reads instruction sequence, It is executed after the first decoding program failure.
In one example of the present invention embodiment, the memorizer control circuit unit according to the third also to read Voltage quasi position executes predetermined registration operation related with the reproducible nonvolatile memorizer module, wherein the predetermined registration operation At least one including following operation: instruction reads the first area and corresponds to the multiple of third decoding unit to obtain Soft bit simultaneously executes iterative decoding to the third decoding unit according to the soft bit；It determines more in the first area The voltage's distribiuting state of the extent of deterioration of a storage unit or the storage unit；And it determines to correspond to the first area Pre-set programs voltage.
In one example of the present invention embodiment, the memorizer control circuit unit is also to indicate according to the third Voltage quasi position is read to read the first area, to obtain third coding unit, wherein the memorizer control circuit unit Also to execute third decoding program to the third coding unit.
In one example of the present invention embodiment, first decoding program and second decoding program are all hard bit Mode decoding.
Another example of the present invention embodiment provides a kind of memorizer control circuit unit, is used to control duplicative non- Volatile, the memorizer control circuit unit include host interface, memory interface, error checking and correction Circuit and memory management circuitry.The host interface is electrically connected to host system.The memory interface is to electricity Property is connected to the reproducible nonvolatile memorizer module.The memory management circuitry is electrically connected to the host and connects Mouth, the memory interface and the error checking and correcting circuit, wherein the memory management circuitry is to send first Read instruction sequence, wherein the first reading instruction sequence to indicate to be read according to the first reading voltage quasi position it is described can First area in manifolding formula non-volatile memory module, to obtain the first coding unit, wherein first coding unit Belong to block code, wherein the error checking and correcting circuit be to execute the first decoding program to first coding unit, And the memory management circuitry is also to record the first decoded information, wherein the memory management circuitry is also to send Second reads instruction sequence, wherein the second reading instruction sequence reads voltage quasi position according to second to indicate to read First area is stated, to obtain the second coding unit, wherein second coding unit belongs to the block code, wherein the mistake It checks with correcting circuit also to execute the second decoding program, and the memory management circuitry to second coding unit Also to record the second decoded information, wherein the memory management circuitry also to according to first decoded information with it is described Second decoded information reads voltage quasi position to estimate and obtain third.
In one example of the present invention embodiment, the block code is made of multiple sub- coding units, the sub- coding list The first bit in member is determined by multiple coded programs.
In one example of the present invention embodiment, the coded program has different coding directions.
In one example of the present invention embodiment, first decoded information includes the first numerical value, the second decoding letter Breath includes second value, wherein the memory management circuitry according to first decoded information and second decoded information come Estimating and obtaining the third to read the operation of voltage quasi position includes: the first numerical value described in comparison and the second value and basis Comparison result determines that the third reads voltage quasi position.
In one example of the present invention embodiment, the first decoding result of first numerical value and first decoding program Related, the second value is related with the second decoding result of second decoding program.
In one example of the present invention embodiment, first numerical value is be positively correlated with first decoding program first Successfully decoded unit number, the second value are the second successfully decoded unit numbers for being positively correlated with second decoding program.
In one example of the present invention embodiment, the memory management circuitry is also to according to first decoding result The first row successfully decoded unit number and first row successfully decoded unit number are obtained, wherein the memory management circuitry is also to root First numerical value is determined according to the first row successfully decoded unit number and the first row successfully decoded unit number, wherein institute Memory management circuitry is stated also to obtain the second row successfully decoded unit number and secondary series solution according to second decoding result Code success unit number, wherein the memory management circuitry is also to according to the second row successfully decoded unit number and described the Two column successfully decoded unit numbers determine the second value.
In one example of the present invention embodiment, the memory management circuitry according to first decoded information with it is described The operation that second decoded information reads voltage quasi position to estimate and obtain the third includes: to read voltage quasi position for described first One of voltage quasi position, which is read, with described second is determined as the third reading voltage quasi position.
In one example of the present invention embodiment, the memory management circuitry is also to judge first decoding program Whether fail, wherein the operation that the memory management circuitry sends the second reading instruction sequence is to determine described first It is executed after decoding program failure.
In one example of the present invention embodiment, the memory management circuitry is also to read voltage according to the third Level executes predetermined registration operation related with the reproducible nonvolatile memorizer module, wherein the predetermined registration operation includes At least one operated below: instruction reads the first area to obtain the multiple soft ratios for corresponding to third decoding unit The special and described error checking and correcting circuit are also to execute iteration to the third decoding unit according to the soft bit Decoding；Determine the extent of deterioration of multiple storage units in the first area or the voltage's distribiuting state of the storage unit； And determine the pre-set programs voltage for corresponding to the first area.
In one example of the present invention embodiment, the memory management circuitry is also to indicate to be read according to the third Voltage quasi position reads the first area, to obtain third coding unit, wherein the error checking is also used with correcting circuit To execute third decoding program to the third coding unit.
In one example of the present invention embodiment, first decoding program and second decoding program are all hard bit Mode decoding.
Based on above-mentioned, reading voltage quasi position estimating and measuring method, memory storage apparatus and control provided in an embodiment of the present invention Circuit unit is being read memory using different reading voltage quasi positions and is attempting to be decoded it to data obtained Afterwards, it can be recorded corresponding to the decoded information of different decoding programs.Thereafter, these decoded informations can be used as estimating One foundation appropriate for reading voltage quasi position.Whereby, for using the reproducible nonvolatile memorizer module of block code Managerial ability can be elevated.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the signal of host system and memory storage apparatus shown by an exemplary embodiment according to the present invention Figure；
Fig. 2 is that computer shown by an exemplary embodiment according to the present invention, input/output device and memory storage fill The schematic diagram set；
Fig. 3 is the signal of host system and memory storage apparatus shown by an exemplary embodiment according to the present invention Figure；
Fig. 4 is the schematic block diagram of memory storage apparatus shown in FIG. 1；
Fig. 5 is the summary of reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention Block diagram；
Fig. 6 is the schematic diagram of memory cell array shown by an exemplary embodiment according to the present invention；
Fig. 7 is the schematic block diagram of memorizer control circuit unit shown by an exemplary embodiment according to the present invention；
Fig. 8 is management reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention Schematic diagram；
Fig. 9 is the signal of the critical voltage distribution of multiple storage units shown by an exemplary embodiment according to the present invention Figure；
Figure 10 is the schematic diagram of coding unit shown by an exemplary embodiment according to the present invention；
Figure 11 is the schematic diagram of the multiple soft bits of reading shown by an exemplary embodiment according to the present invention；
Figure 12 is the flow chart that voltage quasi position estimating and measuring method is read shown by an exemplary embodiment according to the present invention.
Description of symbols:
10: memory storage apparatus；
11: host system；
12: computer；
122: microprocessor；
124: random access memory；
126: system bus；
128: data transmission interface；
13: input/output device；
21: mouse；
22: keyboard；
23: display；
24: printer；
25: portable disk；
26: storage card；
27: solid state hard disk；
31: digital camera；
32:SD card；
33:MMC card；
34: memory stick；
35:CF card；
36: embedded storage device；
402: connecting interface unit；
404: memorizer control circuit unit；
406: reproducible nonvolatile memorizer module；
502: memory cell array；
504: character line control circuit；
506: bit line control circuit；
508: row decoder；
510: data input/output buffer；
512: control circuit；
602: storage unit；
604: bit line；
606: word-line；
608: common source line；
612,614: transistor；
702: memory management circuitry；
704: host interface；
706: memory interface；
708: error checking and correcting circuit；
710: buffer storage；
712: electric power management circuit；
800 (0)~800 (R): entity erased cell；
810 (0)~810 (D): logic unit；
802: memory block；
806: system area；
901,902,911,912,1110,1120: distribution；
913: overlapping region；
Vread-0~Vread-3、V1~V5: read voltage quasi position；
1010: coding unit；
1011~101n: sub- coding unit；
b11~bnm: bit；
1101~1106: voltage range；
b1~b5: soft bit；
S1201~S1206: step.
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module (rewritable non-volatile memory module) and controller (also referred to as, control circuit).It is commonly stored Device storage device is used together with host system, so that host system can write data into memory storage apparatus or from depositing Data are read in reservoir storage device.
Fig. 1 is the signal of host system and memory storage apparatus shown by an exemplary embodiment according to the present invention Figure.Fig. 2 is computer, input/output device and memory storage apparatus shown by an exemplary embodiment according to the present invention Schematic diagram.
Fig. 1 is please referred to, host system 11 generally comprises computer 12 and input/output (input/output, abbreviation I/O) is filled Set 13.Computer 12 includes microprocessor 122, random access memory (random access memory, abbreviation RAM) 124, is Bus 126 of uniting and data transmission interface 128.Input/output device 13 include as Fig. 2 mouse 21, keyboard 22, display 23 with Printer 24.It will be appreciated that the unrestricted input/output device 13 of device shown in Fig. 2, input/output device 13 can be also Including other devices.
In an exemplary embodiment, memory storage apparatus 10 is by data transmission interface 128 and host system 11 Other elements are electrically connected.It can be incited somebody to action by the running of microprocessor 122, random access memory 124 and input/output device 13 Data are written to memory storage apparatus 10 or read data from memory storage apparatus 10.For example, memory storage apparatus 10 can be portable disk 25 as shown in Figure 2, storage card 26 or solid state hard disk (Solid State Drive, abbreviation SSD) 27 etc. Type nonvolatile storage device.
Fig. 3 is the signal of host system and memory storage apparatus shown by an exemplary embodiment according to the present invention Figure.
In general, host system 11 is substantially to cooperate with memory storage apparatus 10 with any system of storing data System.Although host system 11 is explained with computer system in this exemplary embodiment, however, in another exemplary embodiment, Host system 11 can be the systems such as digital camera, video camera, communication device, audio player or video player.For example, When host system is digital camera (video camera) 31, type nonvolatile storage device is then its used SD Card 32, mmc card 33, memory stick (memory stick) 34, CF card 35 or embedded storage device 36 (as shown in Figure 3).Insertion Formula storage device 36 includes embedded multi-media card (Embedded MMC, abbreviation eMMC).It is noted that embedded more matchmakers Body card is directly electrically connected on the substrate of host system.
Fig. 4 is the schematic block diagram of memory storage apparatus shown in FIG. 1.
Referring to figure 4., memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.
In this exemplary embodiment, connecting interface unit 402 is to be compatible to Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, abbreviation SATA) standard.However, it is necessary to be appreciated that, the present invention is not limited to This, connecting interface unit 402 is also possible to meet parallel advanced technology annex (Parallel Advanced Technology Attachment, abbreviation PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, abbreviation IEEE) 1394 standards, Peripheral Component Interconnect (Peripheral Component Interconnect Express, abbreviation PCI Express) standard, universal serial bus (Universal Serial Bus, Abbreviation USB) standard, safety digit (Secure Digital, abbreviation SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I, abbreviation UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, abbreviation UHS-II) interface mark Quasi-, memory stick (Memory Stick, abbreviation MS) interface standard, multimedia storage card (Multi Media Card, abbreviation MMC) It is interface standard, built-in multimedia storage card (Embedded Multimedia Card, abbreviation eMMC) interface standard, general fast Flash memory (Universal Flash Storage, abbreviation UFS) interface standard, compact flash (Compact Flash, abbreviation CF) interface standard, Integrated Device Electronics (Integrated Device Electronics, abbreviation IDE) standard or other be suitble to Standard.Connecting interface unit 402 can be encapsulated in memorizer control circuit unit 404 in a chip or connecting interface Unit 402 is laid in outside a chip comprising memorizer control circuit unit 404.
Memorizer control circuit unit 404 is to execute in the form of hardware or multiple logic gates of form of firmware implementation or control System instructs and carries out writing for data in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The running such as enter, read and erase.
Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404 and uses The data being written with host system 11.Reproducible nonvolatile memorizer module 406 can be single layer cell (Single Level Cell, abbreviation SLC) NAND type flash memory module is (that is, can store 1 ratio in a storage unit The flash memory module of special data), multilevel-cell (Multi Level Cell, abbreviation MLC) NAND type flash memory mould Block (that is, flash memory module that 2 bit datas can be stored in a storage unit), three-layer unit (Triple Level Cell, abbreviation TLC) NAND type flash memory module be (that is, can store the flash memory of 3 bit datas in a storage unit Memory modules), other flash memory modules or other memory modules with the same characteristics.
Fig. 5 is the summary of reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention Block diagram.Fig. 6 is the schematic diagram of memory cell array shown by an exemplary embodiment according to the present invention.
Referring to figure 5., reproducible nonvolatile memorizer module 406 includes memory cell array 502, character line traffic control Circuit 504, bit line control circuit 506, row decoder (column decoder) 508, data input/output buffer 510 With control circuit 512.
In this exemplary embodiment, memory cell array 502 may include to storing data multiple storage units 602, Multiple select grid drain electrode (select gate drain, abbreviation SGD) transistors 612 and multiple select grid source electrode (select Gate source, abbreviation SGS) transistor 614 and connect a plurality of bit line 604 of these storage units, a plurality of word-line 606, with common source line 608 (as shown in Figure 6).Storage unit 602 is by array manner (or in a manner of three-dimensional stacking) configuration On the crosspoint of bit line 604 and word-line 606.When receiving write instruction or reading from memorizer control circuit unit 404 When instruction fetch, control circuit 512 can control character line control circuit 504, bit line control circuit 506, row decoder 508, number Memory cell array 502 is write data to according to input/output (i/o) buffer 510 or reads data from memory cell array 502, Wherein character line control circuit 504 is to control the voltage bestowed to word-line 606, and bit line control circuit 506 is to control It bestows to the voltage of bit line 604, row decoder 508 selects corresponding bit line, and number according to the column address in instruction Data are configured to temporarily store according to input/output (i/o) buffer 510.
Each of reproducible nonvolatile memorizer module 406 storage unit (is hereinafter also referred to faced with voltage Boundary's voltage) change store one or more bits.Specifically, the control grid (control of each storage unit Gate) there is an electric charge capture layer between channel.By bestowing a write-in voltage to controlling grid, thus it is possible to vary charge-trapping The amount of electrons of layer, thus change the critical voltage of storage unit.This program for changing critical voltage also referred to as " writes the data to To storage unit " or " sequencing storage unit ".With the change of critical voltage, each storage of memory cell array 502 Unit has multiple storage states.And it may determine that storage unit is which storage shape belonged to by bestowing reading voltage State obtains one or more bits that storage unit is stored whereby.
Fig. 7 is the schematic block diagram of memorizer control circuit unit shown by an exemplary embodiment according to the present invention.
Fig. 7 is please referred to, memorizer control circuit unit 404 includes memory management circuitry 702, host interface 704, storage Device interface 706 and error checking and correcting circuit 708.
Overall operation of the memory management circuitry 702 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 702, has multiple control instructions, and when memory storage apparatus 10 operates, these control instructions can quilt It executes the running such as to carry out the write-in of data, read and erase.It is equivalent when illustrating the operation of memory management circuitry 702 below In the operation for illustrating memorizer control circuit unit 404.
In this exemplary embodiment, the control instruction of memory management circuitry 702 is to carry out implementation with form of firmware.For example, Memory management circuitry 702 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 10 operates, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.
In another exemplary embodiment, the control instruction of memory management circuitry 702 can also be stored in the form of procedure code The specific region of reproducible nonvolatile memorizer module 406 is (for example, be exclusively used in storage system data in memory module System area) in.In addition, memory management circuitry 702 have microprocessor unit (not shown), read-only memory (not shown) and Random access memory (not shown).In particular, this read-only memory has boot code (boot code), and work as memory When control circuit unit 404 is enabled, microprocessor unit can first carry out this boot code, and will to be stored in duplicative non-volatile Control instruction in property memory module 406 is loaded into the random access memory of memory management circuitry 702.Later, micro- Processor unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.
In addition, the control instruction of memory management circuitry 702 can also be come in another exemplary embodiment with an example, in hardware Implementation.For example, memory management circuitry 702 includes microcontroller, solid element management circuit, memory write circuit, storage Device reading circuit, memory are erased circuit and data processing circuit.Solid element manages circuit, memory write circuit, storage Device reading circuit, memory erase circuit and data processing circuit is electrically connected to microcontroller.Wherein, solid element management Entity erased cell of the circuit to manage reproducible nonvolatile memorizer module 406；Memory write circuit is to right Reproducible nonvolatile memorizer module 406 assigns write instruction sequence to write data into duplicative is non-volatile and deposit In memory modules 406；Memory reading circuitry is to assign reading sequence of instructions to reproducible nonvolatile memorizer module 406 Column are to read data from reproducible nonvolatile memorizer module 406；Memory erases circuit to non-to duplicative Volatile 406 assign erase instruction sequence with by data from reproducible nonvolatile memorizer module 406 It erases；And data processing circuit to handle be intended to be written data to reproducible nonvolatile memorizer module 406 and from The data read in reproducible nonvolatile memorizer module 406.Write instruction sequence reads instruction sequence and instruction of erasing Sequence can be distinctly including one or more procedure codes or instruction code and to indicate reproducible nonvolatile memorizer module 406 It executes corresponding write-in, the operation such as read and erase.
Host interface 704 is electrically connected to memory management circuitry 702 and to receive and identification host system 11 The instruction and data transmitted.That is, the instruction that host system 11 is transmitted can be passed with data by host interface 704 It send to memory management circuitry 702.In this exemplary embodiment, host interface 704 is to be compatible to SATA standard.However, it is necessary to It is appreciated that the invention is not limited thereto, host interface 704 is also possible to be compatible to PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS mark Standard, CF standard, IDE standard or other suitable data transmission standards.
Memory interface 706 is electrically connected to memory management circuitry 702 and non-volatile to access duplicative Property memory module 406.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 406 can be via depositing Memory interface 706 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.Specifically, if storage Device management circuit 702 will access reproducible nonvolatile memorizer module 406, and memory interface 706 can transmit corresponding finger Enable sequence.These instruction sequences may include one or more signals, or the data in bus.For example, reading instruction sequence In, it will include the information such as identification code, the storage address of reading.
Error checking and correcting circuit 708 are electrically connected to memory management circuitry 702 and to execute wrong inspection It looks into and correction program is to ensure the correctness of data.Specifically, when memory management circuitry 702 is received from host system 11 When to write instruction, error checking can be the corresponding error correction of data generation of this corresponding write instruction with correcting circuit 708 Code (error correcting code, abbreviation ECC) and/or error checking code (error detecting code, abbreviation EDC), and memory management circuitry 702 can be by the data of this corresponding write instruction and corresponding error correcting code and/or mistake Check code is written into reproducible nonvolatile memorizer module 406.Later, when memory management circuitry 702 is from can make carbon copies The corresponding error correcting code of this data and/or mistake can be read simultaneously when reading data in formula non-volatile memory module 406 Check code, and error checking and correcting circuit 708 can be according to this error correcting codes and/or error checking code to read number According to execution error checking and correction program.
In an exemplary embodiment, memorizer control circuit unit 404 further includes buffer storage 710 and power management electricity Road 712.Buffer storage 710 is electrically connected to memory management circuitry 702 and is configured to temporarily store from host system 11 Data and instruction or from reproducible nonvolatile memorizer module 406 data.Electric power management circuit 712 is electrically It is connected to memory management circuitry 702 and the power supply to control memory storage apparatus 10.
Fig. 8 is management reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention Schematic diagram.It will be appreciated that being described herein the running of the entity erased cell of reproducible nonvolatile memorizer module 406 When, carrying out application entity erased cell with the words such as " selection ", " grouping ", " division ", " association " is concept in logic.Namely It says, the physical location of the entity erased cell of reproducible nonvolatile memorizer module is not changed, but in logic to can The entity erased cell of manifolding formula non-volatile memory module is operated.
The storage unit of reproducible nonvolatile memorizer module 406 can constitute multiple entity program units, and These entity program units can constitute multiple entity erased cells.Specifically, the storage unit meeting on same word-line Form one or more entity program units.If each storage unit can store 2 or more bits, same word-line On entity program unit can at least be classified as lower entity program unit and upper entity program unit.For example, one deposits The minimum effective bit (Least Significant Bit, abbreviation LSB) of storage unit be belong to lower entity program unit, and And one the highest significant bit (Most Significant Bit, abbreviation MSB) of storage unit be to belong to entity program list Member.In general, in MLC NAND type flash memory, the writing speed of lower entity program unit can be greater than upper entity journey The reliability of the writing speed of sequence unit or lower entity program unit is above the reliability of entity program unit. In this exemplary embodiment, entity program unit is the minimum unit of sequencing.That is, entity program unit is write-in data Minimum unit.For example, entity program unit is physical page or entity fan (sector).If entity program unit is Physical page, then each entity program unit generally includes data bit area and redundancy ratio special zone.Data bit area includes Multiple entities fan, to store the data of user, and redundancy ratio special zone to storage system data (for example, error correction Code).In this exemplary embodiment, data bit area includes 32 entity fans, and the size of entity fan is 512 bit groups (byte, abbreviation B).However, in other exemplary embodiments, also may include in data bit area 8,16 or number it is more or Less entity fan, the present invention are not intended to limit the size and number of entity fan.On the other hand, entity erased cell is erased Minimum unit.Also that is, each entity erased cell contains the storage unit of minimal amount being erased together.For example, entity is smeared Except unit is physical blocks.
Fig. 8 is please referred to, memory management circuitry 702 can smear the entity of reproducible nonvolatile memorizer module 406 Except unit 800 (0)~800 (R) is logically divided into multiple regions, for example, memory block 802 and system area 806.
The entity erased cell of memory block 802 is to store the data from host system 11.It can be deposited in memory block 802 Store up valid data and invalid data.For example, deleted data may be still when host system will delete a valid data It is stored in memory block 802, but invalid data can be marked as.The entity erased cell for not storing valid data is also referred to as Idle (spare) entity erased cell.It erase list for example, being erased later entity erased cell and will become idle entity Member.If have the damage of entity erased cell in memory block 802 or system area 806, the entity erased cell in memory block 802 can also To be used to replace the entity erased cell of damage.If there is no available entity erased cell in memory block 802 to replace damage Entity erased cell when, then memory management circuitry 702 whole memory storage device 10 may be declared as write-in protect (write protect) state of shield, and data can not be written again.In addition, have storage valid data entity erased cell also by Referred to as non-idle (non-spare) entity erased cell.
The entity erased cell of system area 806 is to record system data, and wherein this system data includes about storage The manufacturer of device chip and model, the entity erased cell number of memory chip, each entity erased cell entity program Unit number etc..
Memory block 802 and the quantity of the entity erased cell of system area 806 can according to different memory specifications and It is different.Further, it is necessary to be appreciated that, in the running of memory storage apparatus 10, entity erased cell is associated with to memory block 802 It can dynamically be changed with the grouping relationship of system area 806.For example, when the entity erased cell damage in system area 806 is deposited When the entity erased cell of storage area 802 replaces, then the entity erased cell originally in memory block 802 can be associated to system area 806。
Memory management circuitry 702 can the reality of configuration logic unit 810 (0)~810 (D) to map in memory block 802 Body erased cell 800 (0)~800 (A).For example, host system 11 is accessed by logical address in this exemplary embodiment Data in memory block 802, therefore, each logic unit 810 (0)~810 (D) refer to a logical address.In addition, one In exemplary embodiment, each logic unit 810 (0)~810 (D) may also mean that logic fan, a logical program Unit, a logic erased cell are made of multiple continuous logical addresses.Each logic unit 810 (0)~810 It (D) is to map to one or more solid elements.In this exemplary embodiment, a solid element refers to that an entity is erased list Member.However, a solid element is also possible to a physical address, entity fan, a reality in another exemplary embodiment Body programmed cell is either made of multiple continuous physical address, and the present invention is without restriction.Memory management circuitry 702 Mapping relations between logic unit and solid element can be recorded in one or more logic-entity mappings.Work as host system 11 are intended to read data from memory storage apparatus 10 or when writing data to memory storage apparatus 10, memory management circuitry 702 can execute the data access for memory storage apparatus 10 according to this one or more logic-entity mapping.
Fig. 9 is the signal of the critical voltage distribution of multiple storage units shown by an exemplary embodiment according to the present invention Figure.
Please refer to Fig. 9, the critical voltage of horizontal axis representative memory cell, and longitudinal axis representative memory cell number.For example, Fig. 9 It is the critical voltage for indicating each storage unit in a solid element.It is assumed herein that working as the critical voltage of some storage unit It is when falling in distribution 901, what this storage unit was stored is bit " 1 "；On the contrary, if the critical voltage of some storage unit It is when falling in distribution 902, what this storage unit was stored is bit " 0 ".It is noted that in this exemplary embodiment, often One storage unit is to store a bit, therefore there are two types of may for the distribution of critical voltage.However, implementing in other examples In example, if a storage unit be to store multiple bits, the distribution of corresponding critical voltage then may there are four types of, eight kinds Or it is any other a possible.In addition, the present invention does not limit the representative bit of each distribution yet.
When to read data from reproducible nonvolatile memorizer module 406, memory management circuitry 702 can be sent One reads instruction sequence to reproducible nonvolatile memorizer module 406.It includes one or more instructions that this, which reads instruction sequence, Or procedure code.This reads instruction sequence to indicate to read multiple storage units in a certain solid element to obtain multiple ratios It is special.For example, reading instruction sequence according to this, reproducible nonvolatile memorizer module 406, which will use, reads voltage Vread-0Come It reads these storage units and sends corresponding bit data to memory management circuitry 702.For example, if some is stored The critical voltage of unit, which is less than, reads voltage Vread-0(for example, the storage unit for belonging to distribution 901), then memory management circuitry 702 can read bit " 1 "；If the critical voltage of some storage unit, which is greater than, reads voltage Vread-0(for example, belonging to distribution 902 Storage unit), then memory management circuitry 702 can read bit " 0 ".
However, being changed using time increase and/or operating environment with reproducible nonvolatile memorizer module 406 Become, performance degradation (degradation) can occur for distribution 901 and 902.After performance degradation occurs, distribution 901 and 902 may It is gradually close to each other or even overlapped.For example, distribution 911 is respectively intended to the distribution 901 after expression performance degradation with distribution 912 With 902.Distribution 911 includes an overlapping region 913 with distribution 912.Overlapping region 913 indicates to be deposited in some storage units Storage should be bit " 1 ", but its critical voltage is greater than reading voltage Vread-0；It is stored in some storage units alternatively, having It should be bit " 0 ", but its critical voltage is less than reading voltage Vread-0.After performance degradation occurs, if continuing using reading voltage Vread-0Belong to the storage unit for being distributed 911 or distribution 912 to read, then the bit read may include more mistake.Example Such as, the storage unit for belonging to distribution 911 is mistaken for belonging to distribution 912, or the storage unit for belonging to distribution 912 is mistaken for Belong to distribution 911.Therefore, in this exemplary embodiment, error checking can solve the bit read with correcting circuit 708 Code, to correct mistake therein.In exemplary embodiment below, reads voltage and also referred to as read voltage quasi position (read voltage level).Each, which reads voltage quasi position, has at least one voltage value.
In this exemplary embodiment, error checking can be encoded with correcting circuit 708 be intended to store it is non-volatile to duplicative The data of memory module 406 simultaneously generate a coding unit.This coding unit is to belong to block code.Memory management circuitry 702 can send a write instruction sequence to reproducible nonvolatile memorizer module 406.This write instruction sequence includes extremely A few instruction or procedure code.This write instruction sequence this coding unit is written to indicate to duplicative non-volatile memories An appropriate area (hereinafter also referred to first area) in device module 406.For example, first area can be at least one entity Unit.According to this write instruction sequence, reproducible nonvolatile memorizer module 406 can store this coding unit so far First area.Thereafter, when memory management circuitry 702 indicates to read the data of first area, duplicative is non-volatile to be deposited Memory modules 406 can read this coding unit from first area, and error checking and correcting circuit 708 can execute a decoding Program is to decode this coding unit.
Figure 10 is the schematic diagram of coding unit shown by an exemplary embodiment according to the present invention.
Figure 10 is please referred to, coding unit 1010 includes bit b11~bnm.If by bit b11~bnmIt is grouped into sub- coding unit 1011~101n, then each sub- 1011~101n of coding unit has m bit.N and m all may be greater than 1 it is any just Integer.In this exemplary embodiment, the bit of part is determined by multiple coded programs.For example, can be row by coding direction (row) coded program of direction (for example, from left to right) is considered as first kind coded program, and is column direction (example by coding direction Such as, from top to bottom coded program) is considered as the second class coded program.In an exemplary embodiment, first kind coded program is also referred to as For row (row) coded program, and the second class coded program also referred to as arranges (column) coded program.
In this exemplary embodiment, first kind coded program can be first performed, and according to the coding of first kind coded program As a result, the second class coded program can be connected and is performed.For example, it is assumed that the user's data to be stored include bit b11~b1p、b21 ~b2p、…、br1~brp, then in first kind coded program, bit b11~b1p、b21~b2p、…、br1~brpIt can be compiled respectively Code is to obtain bit b11~b1m(that is, sub- coding unit 1011), b21~b2m(that is, sub- coding unit 1012) ..., br1~brm (that is, sub- coding unit 101r).Bit b1q~b1mFor corresponding to bit b11~b1pError correcting code, bit b2q~b2mIt is right It should be in bit b21~b2pError correcting code, and so on, wherein q be equal to p+1.Obtaining sub- 1011~101r of coding unit Later, the second class coded program can be performed.For example, in the second class coded program, bit b11~br1(that is, each height is compiled First bit in code unit 1011~101r), bit b12~br2(that is, in each sub- 1011~101r of coding unit Second bit) ..., bit b1m~brm(that is, m-th of bit in each sub- 1011~101r of coding unit) can be distinguished It is encoded to obtain bit b11~bn1、b12~bn2、…、b1m~bnm.Bit bs1~bn1For corresponding to bit b11~br1Mistake More code, bit bs2~bn2For corresponding to bit b12~br2Error correcting code, and so on, wherein s be equal to r+1.
After reading out coding unit 1010, correspond to used coded sequence, coding unit 1010 can quilt Decoding.For example, decoding direction is decoding program (also referred to as the second class decoding program) meeting of column direction in this exemplary embodiment First it is performed, and according to the decoding result of the second class decoding program, decode the decoding program (also referred to as first that direction is line direction Class decoding program) it can connect and be performed.For example, in the second class decoding program, bit bs1~bn1、bs2~bn2、…、bsm~bnm It can be respectively used to bit b11~br1、b12~br2、…、b1m~brmIt is decoded.Obtaining decoded bit b11~ br1、b12~br2、…、b1m~brmLater, first kind decoding program can be performed.For example, in first kind decoding program, by Bit b after two class decoding process1q~b1m、b2q~b2m、…、brq~brmIt can be used, respectively, to decode journey to by the second class The decoded bit b of sequence11~b1p、b21~b2p、…、br1~brpIt is decoded to obtain decoded user's data.
It is noted that composition and the coding/decoding sequence of the coding unit referred in above-mentioned exemplary embodiment are One example rather than to limit the present invention.For example, generated error correcting code is also possible in another exemplary embodiment Before being arranged in corresponding user's data or it is interspersed in corresponding user's data.Alternatively, in an exemplary embodiment, When encoding user's data, it is also possible to first carry out the second class coded program, then further in accordance with the volume of the second class coded program Code result executes first kind coded program；It is corresponding, when decoding coding unit, it is also possible to first carry out first kind decoding journey Then sequence executes the second class decoding program further according to the decoding result of first kind decoding program.In addition, first kind coded program (or first kind decoding program) is different from the coding direction of the second class coded program (or second class decoding program), but the first kind Coded program (or first kind decoding program) can be used identical or different with the second class coded program (or second class decoding program) Coding/decoding algorithm.For example, first kind coded program can be with corresponding first kind decoding program comprising low-density parity Check correcting code (low density parity code, abbreviation LDPC), BCH code and Reed Solomon code (Reed- Solomon code, abbreviation RS code), the various coding/decoding such as square turbine code (block turbo code, abbreviation BTC) drills At least one of algorithm；And the second class coded program and corresponding second class decoding program be also possible to comprising above-mentioned volume/ At least one or other kinds of coding/decoding algorithm of decoding algorithm.
In this exemplary embodiment, memory management circuitry 702 can send a reading instruction sequence (hereinafter also referred to first Read instruction sequence) to reproducible nonvolatile memorizer module 406.This first reading instruction sequence is to indicate from above-mentioned Read data in first area.After receiving this first reading instruction sequence, reproducible nonvolatile memorizer module 406 Multiple storages in this first area can be read according to a reading voltage quasi position (the hereinafter also referred to first reading voltage quasi position) Unit is to obtain a coding unit (hereinafter also referred to the first coding unit).This first coding unit belongs to block code.About volume The introduction of code unit has been specified in, therefore is not just repeated herein.Then, error checking and correcting circuit 708 can be encoded to first Unit executes a decoding program (hereinafter also referred to the first decoding program) and records corresponding decoded information (hereinafter also referred to the One decoded information).
In this exemplary embodiment, the first decoding program is to belong to iterative decoding procedures.For example, in the first decoding program In, error checking and correcting circuit 708 can execute iterative decoding operation at least once, iteratively to update the first coding Reliability information (for example, decoding initial value) first coding unit of Lai Tigao of unit is decoded into power.Iteration each time Decoding operation may include the same or similar decoding operate introduced in the exemplary embodiment of Figure 10.In general, according to coding The number of wrong (also referred to as error bit), the first decoding program may success or failures in unit.For example, by least once Iterative decoding operation after, if successfully decoded, for example, error checking and correcting circuit 708 determine in the first coding unit Mistake has all been corrected, then error checking and correcting circuit 708 can export decoded (or after corrigendum) first coding unit. Conversely, if because the number of error bit is excessively in the first coding unit and/or the distribution of these error bits is just at nothing The factors such as the position that method is corrected have led to the number of iterative decoding operation performed by error checking and correcting circuit 708 Reach a preset times, then error checking and correcting circuit 708 can determine decoding failure.
It is noted that from the exemplary embodiment of Figure 10 it is found that corresponding to the first kind decoding program or right of certain a line It should be in all possible success or failure of the second class decoding program of a certain column.The first kind decoding program executed each time is respectively only Vertical, and the second class decoding program executed each time is also independent.For example, for sub- coding unit 1011 A kind of decoding program may success or failure, and may also succeed for the second class decoding program of sub- coding unit 1012 or Failure, the two may be unrelated.Therefore, even if the decoding failure of first coding unit, but wherein still there may be successfully decoded Row, column or bit.
The information that these can be successfully decoded for memory management circuitry 702 is recorded as the first decoded information.For example, This first decoded information may include a numerical value (hereinafter also referred to the first numerical value).The solution of first numerical value and the first coding unit Code result (hereinafter also referred to the first decoding result) is related.For example, the first numerical value is determined according to the first decoding result.Example Such as, the first numerical value be positively correlated with (positively correlated) the first decoding program successfully decoded unit number it is (following Also referred to as the first successfully decoded unit number).In this exemplary embodiment, the first successfully decoded unit number refers to the first coding unit In the number of unit that is successfully decoded.For example, a unit being successfully decoded can refer to the row being successfully decoded, One column being successfully decoded or a bit being successfully decoded.Memory management circuitry 702 can directly first solve this Code success unit number is as this first numerical value.For example, memory management circuitry 702 can directly by the first coding unit by The column being successfully decoded in the number (hereinafter also referred to the first row successfully decoded unit number) of the decoded row of function, the first coding unit Number (hereinafter also referred to first row successfully decoded unit number) or the first coding unit in the number of bit that is successfully decoded Mesh is as this first numerical value.Alternatively, memory management circuitry 702 can also be according to the first row successfully decoded unit number and first row Successfully decoded unit number executes a logical operation to determine this first numerical value.For example, memory management circuitry 702 can be by A line successfully decoded unit number is multiplied by weight (hereinafter also referred to the first weight) and obtains parameter (hereinafter also referred to first Parameter) and first row successfully decoded unit number is multiplied by another weight (hereinafter also referred to the second weight) obtains another ginseng Number (hereinafter also referred to the second parameter)；First parameter can be added with the second parameter to determine this by memory management circuitry 702 First numerical value.By taking the exemplary embodiment of Figure 10 as an example, the first weight can be n/ (n+m), and the second weight can be m/ (n+ m).However, the first weight can also distinctly be set according to the demand in practice with the second weight, the present invention is without restriction. In addition, the first successfully decoded unit number can also be input to one and looked by memory management circuitry 702 in another exemplary embodiment Look for table and using the output of this look-up table as the first numerical value.
After determining for the decoding failure of the first coding unit, memory management circuitry 702 can indicate that duplicative is non- Voltage is read in the adjustment of volatile 406.For example, by electricity is read from first to the reading voltage for reading first area Pressure level is adjusted to another reading voltage quasi position (hereinafter also referred to second reads voltage quasi position).702 meeting of memory management circuitry Another reading instruction sequence (hereinafter also referred to second reads instruction sequence) is sent to reproducible nonvolatile memorizer module 406.Second reading instruction sequence reads above-mentioned first area according to the second reading voltage quasi position to indicate.Receiving After second reading instruction fetch sequence, reproducible nonvolatile memorizer module 406 can read voltage quasi position according to second come again The storage unit in this first area is read to obtain another coding unit (hereinafter also referred to the second coding unit).Second coding Unit is equally to belong to block code.Reading voltage quasi position due to being used to read data changes, therefore the second coding unit partial Bit may from the first coding unit be located at the bit of same position it is different.For example, the bit in the second coding unit b11It may be with the bit b in the first coding unit11It is different.
Error checking and correcting circuit 708 can execute another decoding program (hereinafter also referred to second to the second coding unit Decoding program) and record corresponding decoded information (hereinafter also referred to the second decoded information).On how to execute for coding The decoding program of unit has been specified in, therefore is not just repeated herein.
It is noted that even if the second coding unit decoding failure, but wherein still there may be the row being successfully decoded, Column or bit.The information that these can be successfully decoded for memory management circuitry 702 is recorded as the second decoded information.Example Such as, this second decoded information may include a numerical value (hereinafter also referred to second value).Second value and the second coding unit Decoding result (hereinafter also referred to the second decoding result) it is related.For example, second value is determined according to the second decoding result. For example, second value is successfully decoded unit number (hereinafter also referred to the second successfully decoded list for being positively correlated with the second decoding program First number).In this exemplary embodiment, the second successfully decoded unit number refer to the unit that is successfully decoded in the second coding unit it Number.For example, memory management circuitry 702 can be directly (following by the number for the row being successfully decoded in the second coding unit Also referred to as the second row successfully decoded unit number), the number (hereinafter also referred to second of column that is successfully decoded in the second coding unit Column successfully decoded unit number) or the second coding unit in the number of bit that is successfully decoded as this second value.Or Person, memory management circuitry 702 can also be held according to the second row successfully decoded unit number with secondary series successfully decoded unit number One logical operation of row is to determine this second value.In addition, memory management circuitry 702 can also be by the second successfully decoded unit number It is input to a look-up table and using the output of this look-up table as second value.On how to determine that it is above-mentioned that second value can refer to About the explanation of the first numerical value, therefore just do not repeat herein.
After obtaining the first decoded information and the second decoded information, memory management circuitry 702 can be according to this first solution Code information estimates another reading voltage quasi position (hereinafter also referred to third reading voltage quasi position) with this second decoded information.At this In exemplary embodiment, third, which reads voltage quasi position, can be considered as one that estimates to come for first area best reading electricity Press level.It is evaluated according to past historical record for example, this best reading voltage quasi position can refer to can be used to read Take out the reading voltage quasi position for being decoded into the highest coding unit of power.For example, memory management circuitry 702 can compare first Numerical value and second value and determine that third reads voltage quasi position according to comparison result.For example, if the first numerical value is greater than second Numerical value, memory management circuitry 702 can determine that third reads voltage quasi position according to the first reading voltage quasi position.For example, In this exemplary embodiment, if the first numerical value is greater than second value, memory management circuitry 702 directly can read voltage for first Level is set as third and reads voltage quasi position.Alternatively, if the first numerical value is greater than second value, being deposited in another exemplary embodiment Reservoir management circuit 702 can also execute a logical operation according to the first reading voltage quasi position and determine third and read voltage standard Position, the present invention are without restriction.In addition, memory management circuitry 702 can be according to second if the first numerical value is less than second value Voltage quasi position is read to determine that third reads voltage quasi position.For example, in this exemplary embodiment, if the first numerical value is less than the second number Second reading voltage quasi position directly can be set as third and read voltage quasi position by value, memory management circuitry 702.Alternatively, In another exemplary embodiment, if the first numerical value is less than second value, memory management circuitry 702 can also read electricity according to second Pressure level determines that third reads voltage quasi position to execute a logical operation, and the present invention is without restriction.
Although it is noted that above-mentioned exemplary embodiment be with continuous read operation twice and decoding operate as Example is illustrated, however, in another exemplary embodiment, the twi-read operation and decoding that are referred in above-mentioned exemplary embodiment Operation is also possible to discontinuous.More read operations and decoding operate can be used to be directed to what the same region was stored Data are handled.For example, in an exemplary embodiment of Fig. 9, multiple reading voltage quasi position V that can be usedread-0~ Vread-3It may be recorded in a look-up table.According to this look-up table, voltage quasi position V is readread-0It can first be used to read Take the data of above-mentioned first area.Thereafter, if being read for the coding unit decoding failure read out according to this look-up table Take voltage quasi position Vread-1Data for reading above-mentioned first area can be connected.Thereafter, if coding for reading out Unit still decodes failure, then reads voltage quasi position Vread-2Can be connected data for reading above-mentioned first area and Corresponding decoding operate can be performed.Thereafter, if still decoding failure for the coding unit read out, voltage standard is read Position Vread-3The data for being used to read above-mentioned first area can be connected and corresponding decoding operate can be performed.Above-mentioned model The the first reading voltage quasi position referred in example embodiment can be reading voltage quasi position V shown in Fig. 9read-0~Vread-2In Any one, and the second reading voltage quasi position referred in above-mentioned exemplary embodiment then can be after the first reading voltage quasi position Any reading voltage quasi position bestowed.For example, if the first reading voltage quasi position is to read voltage quasi position Vread-0, then second read Voltage quasi position, which can be, reads voltage quasi position Vread-1~Vread-3Any one of, and so on.In addition, reading voltage quasi position Vread-0~Vread-3The sequence used can also be adjusted, and the present invention is without restriction.For example, in another exemplary embodiment In, read voltage quasi position Vread-0~Vread-3It is also possible to sequentially be used from small to large according to voltage value.
In an exemplary embodiment, for the same region in reproducible nonvolatile memorizer module 406, if looking into The coding unit for being all previously used and being read out according to reading voltage quasi position documented in table can not be all successfully decoded, Then the above-mentioned operation that third reading voltage quasi position is determined according to multiple used reading voltage quasi positions can be just performed.So And in another exemplary embodiment, it also can be set as, attempting to use certain reading voltage quasi positions or changed to read voltage The number of level is more than that can be performed after a preset times above-mentioned to determine third according to multiple used reading voltage quasi positions The operation of voltage quasi position is read, the present invention is without restriction.In addition, although above-mentioned exemplary embodiment is all that iterative decoding procedures are made For the example of the first decoding program and the second decoding program, however, in another exemplary embodiment, the first decoding program and/or Second decoding program is also possible to belong to non-iterative decoding program, and the present invention is without restriction.
In an exemplary embodiment, coding unit is being read using some reading voltage quasi position and is being executed corresponding During decoding program, the bit value on the decoded position of success of part can be considered to be correctly and be recorded Come.For example, the bit value of each position can be recorded in this row or column if some row or column is decoded into function Come.In decoding program next time, the bit value being recorded may act as additional decoded information.For example, one In exemplary embodiment, it is assumed that the decoding for some coding unit is the ratio in failure but decoding result presentation code unit Special b11It is correctly then bit b11Bit value can be recorded.Voltage quasi position is read in adjustment to read same data And to the bit b in coding unit in the decoding next time for the data execution read out, read out11It can directly be corrected For the bit value being previously recorded.Alternatively, the bit value being recorded can be skipped in decoding program next time, thus Reduce the number that examined bit is needed in the coding unit obtained each time.Whereby, quasi- according to different reading voltage During position executes corresponding decoding program, the bit of part can be gradually corrected in coding unit, to increase decoding Success rate.In addition, the present invention is not intended to limit the type for the additional decoded information that can be handed on, it is any to pass to down The decoded information that primary decoding program uses can be recorded and be used in decoding program next time.
After determining that third reads voltage quasi position, it is quasi- that memory management circuitry 702 can read voltage according to this third Position executes an at least predetermined registration operation related with reproducible nonvolatile memorizer module 406.This predetermined registration operation can be For optimizing reproducible nonvolatile memorizer module 406 for the storage of data, reading or for the pipe of solid element Reason.
In an exemplary embodiment, error checking and correcting circuit 708 can execute hard bit mode decoding and soft bit Mode decoding.By taking SLC type flash memory as an example, in hard bit mode decoding, a reading voltage quasi position can be imparted to One storage unit.This reading voltage quasi position whether is reacted on according to this storage unit and is switched on, and duplicative is non-volatile Memory module 406 can return a bit (also referred to as verifying bit).Thereafter, error checking and correcting circuit 708 can bases This verifies bit to be decoded.In hard bit mode decoding, verifying bit obtained is also referred to as hard bit.Equally with For SLC type flash memory, in soft bit mode decoding, it is single that multiple reading voltage quasi positions can be imparted to a storage Member.These on states for reading voltage quasi position, reproducible nonvolatile memorizer module are reacted on according to this storage unit 406 can return multiple verifying bits.Thereafter, error checking can be decoded with correcting circuit 708 according to these verifying bits. In soft bit mode decoding, verifying bit obtained is also referred to as soft bit.In the iterative decoding journey of hard bit mode decoding In sequence, the decoding initial value of a storage unit is can be divided into two according to a verifying bit for corresponding to this storage unit A numerical value.For example, the decoding initial value of corresponding storage unit can be set to "-n " if verifying bit is " 1 "；If verifying ratio Spy is " 0 ", then the decoding initial value of corresponding storage unit can be set to "-n ".The iterative decoding procedures of hard bit mode decoding It is to be executed based on this two kinds of numerical value.However, in the iterative decoding procedures of soft bit mode decoding, the solution of a storage unit Code initial value is determined according to the multiple verifying bits for corresponding to this storage unit.
In an exemplary embodiment, multiple reading voltage quasi positions in above-mentioned look-up table are all used up finish before, it is wrong It is all to belong to hard bit mode decoding that erroneous detection, which is looked into decoding performed by correcting circuit 708,.If multiple readings in above-mentioned look-up table It takes voltage quasi position to be all used up to finish and still the data read out from the same region can not be successfully decoded, then mistake inspection Looking into may be switched to correcting circuit 708 using soft bit mode decoding.In soft bit mode decoding, memory management electricity Road 702 can indicate to read voltage quasi position according to third to read above-mentioned first area to obtain a decoding unit (hereinafter also referred to Third decoding unit).In addition, memory management circuitry 702 can also indicate to read voltage quasi position according to this third to determine voltage Value is located at multiple reading voltage quasi positions near the voltage value of this third reading voltage quasi position, and (the hereinafter also referred to the 4th reads voltage Level) and this first area is read according to these the 4th reading voltage quasi positions, to obtain multiple soft bits.These the 4th readings It takes voltage quasi position to may include or do not include third and reads voltage quasi position.Each soft bit can be provided in third decoding unit A bit additional decoded information.Error checking can be to the corresponding solution of third decoding unit execution with correcting circuit 708 Coded program (also referred to as third decoding program).
Figure 11 is the schematic diagram of the multiple soft bits of reading shown by an exemplary embodiment according to the present invention.
Please refer to Figure 11, it is assumed that it includes reading voltage quasi position V that the 4th determined, which reads voltage quasi position,1~V5, then in soft ratio In special mode decoding, voltage quasi position V is read1~V5It can be used to read in above-mentioned first area and belong to distribution 1110 and 1120 Storage unit.It reacts on and reads voltage quasi position V1~V5, multiple soft bit b1~b5It can be obtained.For example, if some storage is single The critical voltage of member is located at voltage range 1101, then the soft bit b read1~b5It can be " 11111 "；If some is stored The critical voltage of unit is located at voltage range 1102, then the soft bit b read1~b5It can be " 01111 "；If some is deposited The critical voltage of storage unit is located at voltage range 1103, then the soft bit b read1~b5It can be " 00111 "；If some The critical voltage of storage unit is located at voltage range 1104, then the soft bit b read1~b5It can be " 00011 "；If a certain The critical voltage of a storage unit is located at voltage range 1105, then the soft bit b read1~b5It can be " 00001 "；If certain The critical voltage of one storage unit is located at voltage range 1106, then the soft bit b read1~b5It can be " 00000 ".? In soft bit mode decoding, the soft bit b that is read1~b5It can be used to carry out corresponding iterative solution to third decoding unit Code.For example, corresponding to each voltage range, the probability that storage unit belongs to distribution 1110 can with the probability for belonging to distribution 1120 To be computed in advance.According to the two probability can calculate log likelihood ratio (Log Likelihood Ratio, Abbreviation LLR).This log likelihood ratio can be used to determine the size of the absolute value of decoding initial value.For example, each voltage range Corresponding decoding initial value can be computed in advance and be stored in a look-up table.Soft bit b obtained1~ b5It can be entered in this look-up table, and corresponding decoding initial value can be obtained.Thereafter, error checking and correcting circuit 708 can execute subsequent decoding according to decoding initial value obtained.
In other words, relative to hard bit mode decoding, decoded information used in soft bit mode decoding is (for example, verifying Bit) it is more.Increased based on used decoded information, soft bit mode decoding is decoded into power and would generally be higher than hard bit Mode decoding is decoded into power.Therefore, soft bit mode decoding be possible to hard bit mode decoding failure in the case where at Complete to decode to function.
In an exemplary embodiment, it is above-mentioned to determine that memory management circuitry 702 can read voltage quasi position according to third The extent of deterioration of multiple storage units in first area or the voltage's distribiuting state of these storage units.For example, in the model of Fig. 9 In example embodiment, for belonging to for the storage unit of distribution 911 and 912, reading voltage quasi position V is utilizedread-0To read these Storage unit can read the lower data of error rate；And after performance degradation occurs, for belong to distribution 911 with For 912 storage unit, reading voltage quasi position V is utilizedread-3Can read reading these storage units then error rate compared with Low data.Therefore, voltage quasi position is read according to the third that is determined, memory management circuitry 702 can and also by looking into The modes such as table obtain the current extent of deterioration of these storage units or the current voltage's distribiuting state of these storage units.Example Such as, the reading voltage quasi position V in Fig. 9read-0~Vread-3It can be respectively corresponding to an extent of deterioration or voltage's distribiuting state.Value It obtains one and is mentioned that in an exemplary embodiment, the behaviour in service or current operation environment of the extent of deterioration and storage unit have It closes.For example, if the number increase of erasing of the write-in number of the reading times of storage unit, storage unit, storage unit, stores The extent of deterioration of unit may synchronize increase.For example, being stored if the time interval of data storage in the memory unit increases The extent of deterioration of unit may synchronize increase.For example, if the operation ring of current reproducible nonvolatile memorizer module 406 The temperature or humidity in border is too high, then the extent of deterioration of storage unit may also can synchronize increase.In addition, the extent of deterioration can also It can be related with the correctness/error rate for the data being stored in a storage unit.For example, the extent of deterioration of storage unit is higher, The correctness for the data being then stored in a storage unit is lower or the error rate of data that is stored in a storage unit is higher.
In an exemplary embodiment, memory management circuitry 702 can read voltage quasi position according to third to determine to correspond to A pre-set programs voltage in above-mentioned first area.For example, if reproducible nonvolatile memorizer module 406 is using one Incremental step pulse is erased, and to carry out sequencing storage single for (Incremental Step Pulse Program, abbreviation ISPP) model Member, then memory management circuitry 702 can read voltage quasi position according to third to indicate type nonvolatile mould Block 406 adjusts the initial program voltage in this incremental step pulse model.This initial program voltage is this increment step The programming voltage of the storage unit in above-mentioned first area is imparted in impulse model at first.In addition, it is any with adjust this Initial program voltage in relation to and/or can achieve the sequencing parameter of similar effect or parameter of erasing and can also be adjusted.
It is noted that the present invention can not read voltage quasi position according to third is performed predetermined registration operation restriction In above-mentioned.For example, in another exemplary embodiment, it is any can be according to the performance degradation of storage unit, extent of deterioration or voltage Distribution and correspond to adjustment parameter or memory setting can react on third read voltage quasi position and suitably adjusted It is whole, so as to improve the managerial ability for reproducible nonvolatile memorizer module 406.For example, in an exemplary embodiment, Voltage quasi position is read according to third, solid element belonging to above-mentioned first area can also be marked as damage etc..In addition, In one exemplary embodiment, voltage quasi position, the service life etc. of reproducible nonvolatile memorizer module 406 are read according to third The information of any management for being conducive to reproducible nonvolatile memorizer module 406 can also be obtained.
It should be noted that although above-mentioned exemplary embodiment be all stored using storage unit a bit as example into Row explanation, however, in another exemplary embodiment, the operation of above-mentioned reading coding unit, the operation of above-mentioned decoding coding unit And the operation of estimation reading voltage quasi position is readily applicable to a storage unit and can store the use situation of multiple bits. For example, the reading voltage quasi position estimated is also likely to be the storage unit to read operation under MLC mode or TLC mode The data stored.
Figure 12 is the flow chart that voltage quasi position estimating and measuring method is read shown by an exemplary embodiment according to the present invention.
Figure 12 is please referred to, in step S1201, reads voltage quasi position according to first, the duplicative is non-volatile to be deposited First area in memory modules can be read to obtain the first coding unit, wherein first coding unit belongs to block Code.In step S1202, the first decoding program of first coding unit can be performed and the first decoded information meeting It is recorded.In step S1203, voltage quasi position is read according to second, the first area can be read to obtain the second coding Unit, wherein second coding unit belongs to the block code.In step S1204, for second coding unit Second decoding program can be performed and the second decoded information can be recorded.In step S1205, believed according to first decoding Breath and second decoded information, third read voltage quasi position and can be estimated and be obtained.In step S1206, according to described Third reads voltage quasi position, and an at least predetermined registration operation related with the reproducible nonvolatile memorizer module can be held Row.
However, each step has been described in detail as above in Figure 12, just repeat no more herein.It is worth noting that, each in Figure 12 Step can be implemented as multiple procedure codes or circuit, and the present invention is without restriction.In addition, more than the method for Figure 12 can arrange in pairs or groups Exemplary embodiment uses, and also can be used alone, and the present invention is without restriction.
In conclusion read using different reading voltage quasi positions memory and attempt to data obtained into After row decoding, the decoded information corresponding to different coding unit can be recorded.Thereafter, these decoded informations can be used to As estimation one foundation appropriate for reading voltage quasi position, and at least one predetermined registration operation can be accordingly performed.By This, for using the managerial ability of reproducible nonvolatile memorizer module of block code that can be elevated.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims (33)

1. a kind of reading voltage quasi position estimating and measuring method, which is characterized in that it is used for reproducible nonvolatile memorizer module, it is described Reading voltage quasi position estimating and measuring method includes:
The first area in the reproducible nonvolatile memorizer module is read according to the first reading voltage quasi position, to obtain The first coding unit is obtained, wherein first coding unit belongs to block code；
First decoding program is executed to first coding unit and records the first decoded information；
The first area is read according to the second reading voltage quasi position, to obtain the second coding unit, wherein described second compiles Code unit belongs to the block code；
Second decoding program is executed to second coding unit and records the second decoded information；
Third is estimated and obtained according to first decoded information and second decoded information reads voltage quasi position；
Voltage quasi position is read according to the third to read the first area, to obtain third coding unit；And
Third decoding program is executed to the third coding unit.
2. reading voltage quasi position estimating and measuring method according to claim 1, which is characterized in that the block code is by multiple sub- volumes Code unit forms, and the first bit in a little coding unit is determined by multiple coded programs.
3. reading voltage quasi position estimating and measuring method according to claim 2, which is characterized in that those coded programs have difference Coding direction.
4. reading voltage quasi position estimating and measuring method according to claim 1, which is characterized in that first decoded information includes First numerical value, second decoded information includes second value,
The third is wherein estimated and obtained according to first decoded information and second decoded information reads voltage standard Position the step of include:
Compare first numerical value and the second value and determines that the third reads voltage quasi position according to comparison result.
5. reading voltage quasi position estimating and measuring method according to claim 4, which is characterized in that first numerical value and described the First decoding result of one decoding program is related, and the second decoding result of the second value and second decoding program has It closes.
6. reading voltage quasi position estimating and measuring method according to claim 5, which is characterized in that first numerical value is to be positively correlated In the first successfully decoded unit number of first decoding program, the second value is to be positively correlated with second decoding program The second successfully decoded unit number.
7. reading voltage quasi position estimating and measuring method according to claim 6, which is characterized in that further include:
The first row successfully decoded unit number and first row successfully decoded unit number are obtained according to first decoding result；
First numerical value is determined according to the first row successfully decoded unit number and the first row successfully decoded unit number；
The second row successfully decoded unit number and secondary series successfully decoded unit number are obtained according to second decoding result；And
The second value is determined according to the second row successfully decoded unit number and the secondary series successfully decoded unit number.
8. reading voltage quasi position estimating and measuring method according to claim 1, which is characterized in that according to first decoded information Estimating and obtain the step of third reads voltage quasi position with second decoded information includes:
One of the first reading voltage quasi position and the second reading voltage quasi position are determined as the third to read Voltage quasi position.
9. reading voltage quasi position estimating and measuring method according to claim 1, which is characterized in that further include:
Judge whether first decoding program fails,
It is wherein to determine first decoding the step of reading the first area according to the second reading voltage quasi position It is executed after procedure failure.
10. reading voltage quasi position estimating and measuring method according to claim 1, which is characterized in that further include:
It is related with the reproducible nonvolatile memorizer module default to execute to read voltage quasi position according to the third Operation,
Wherein the predetermined registration operation includes at least one of following operation:
Read the first area with obtain correspond to third decoding unit multiple soft bits and according to those soft bits come pair The third decoding unit executes iterative decoding；
Determine the extent of deterioration of multiple storage units in the first area or the voltage's distribiuting state of those storage units；With And
Determine the pre-set programs voltage for corresponding to the first area.
11. reading voltage quasi position estimating and measuring method according to claim 1, which is characterized in that first decoding program with Second decoding program is all hard bit mode decoding.
12. a kind of memory storage apparatus characterized by comprising
Connecting interface unit, is electrically connected to host system；
Reproducible nonvolatile memorizer module；And
Memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile Module,
Wherein the memorizer control circuit unit is to send the first reading instruction sequence, wherein described first reads sequence of instructions Column read the firstth area in the reproducible nonvolatile memorizer module according to the first reading voltage quasi position to indicate Domain, to obtain the first coding unit, wherein first coding unit belongs to block code,
Wherein the memorizer control circuit unit is also to execute the first decoding program to first coding unit and remember The first decoded information is recorded,
Wherein the memorizer control circuit unit is also to send the second reading instruction sequence, wherein described second reads instruction Sequence reads the first area according to the second reading voltage quasi position to indicate, to obtain the second coding unit, wherein institute It states the second coding unit and belongs to the block code,
Wherein the memorizer control circuit unit is also to execute the second decoding program to second coding unit and remember The second decoded information is recorded,
Wherein the memorizer control circuit unit also to according to first decoded information and second decoded information come Estimate and obtain third and reads voltage quasi position,
Wherein the memorizer control circuit unit also reads instruction sequence to send a third, wherein third reading refers to Sequence is enabled to read the first area according to third reading voltage quasi position to indicate, to obtain third coding unit,
Wherein the memorizer control circuit unit is also to execute third decoding program to the third coding unit.
13. memory storage apparatus according to claim 12, which is characterized in that the block code is by multiple sub- coding lists Member forms, and the first bit in a little coding unit is determined by multiple coded programs.
14. memory storage apparatus according to claim 13, which is characterized in that those coded programs have different volumes Code direction.
15. memory storage apparatus according to claim 12, which is characterized in that first decoded information includes first Numerical value, second decoded information includes second value,
Wherein the memorizer control circuit unit is estimated simultaneously according to first decoded information and second decoded information It obtains the third and reads the operation of voltage quasi position and include:
Compare first numerical value and the second value and determines that the third reads voltage quasi position according to comparison result.
16. memory storage apparatus according to claim 15, which is characterized in that first numerical value and first solution First decoding result of coded program is related, and the second value is related with the second decoding result of second decoding program.
17. memory storage apparatus according to claim 16, which is characterized in that first numerical value is to be positively correlated with institute The first successfully decoded unit number of the first decoding program is stated, the second value is be positively correlated with second decoding program Two successfully decoded unit numbers.
18. memory storage apparatus according to claim 17, which is characterized in that the memorizer control circuit unit is also To obtain the first row successfully decoded unit number and first row successfully decoded unit number according to first decoding result,
Wherein the memorizer control circuit unit is also to according to the first row successfully decoded unit number and the first row Successfully decoded unit number determines first numerical value,
Wherein the memorizer control circuit unit is also to obtain the second row successfully decoded list according to second decoding result First number and secondary series successfully decoded unit number,
Wherein the memorizer control circuit unit is also to according to the second row successfully decoded unit number and the secondary series Successfully decoded unit number determines the second value.
19. memory storage apparatus according to claim 12, which is characterized in that the memorizer control circuit unit root The operation packet that the third reads voltage quasi position is estimated and obtained according to first decoded information and second decoded information It includes:
One of the first reading voltage quasi position and the second reading voltage quasi position are determined as the third to read Voltage quasi position.
20. memory storage apparatus according to claim 12, which is characterized in that the memorizer control circuit unit is also To judge whether first decoding program fails,
It is to determine described first that wherein the memorizer control circuit unit, which sends the operation of the second reading instruction sequence, It is executed after decoding program failure.
21. memory storage apparatus according to claim 12, which is characterized in that the memorizer control circuit unit is also It is executed to read voltage quasi position according to the third related with the reproducible nonvolatile memorizer module default Operation,
Wherein the predetermined registration operation includes at least one of following operation:
Indicate that reading the first area corresponds to multiple soft bits of third decoding unit and according to those soft bits to obtain To execute iterative decoding to the third decoding unit；
Determine the extent of deterioration of multiple storage units in the first area or the voltage's distribiuting state of those storage units；With And
Determine the pre-set programs voltage for corresponding to the first area.
22. memory storage apparatus according to claim 12, which is characterized in that first decoding program and described the Two decoding programs are all hard bit mode decoding.
23. a kind of memorizer control circuit unit, which is characterized in that for controlling reproducible nonvolatile memorizer module, The memorizer control circuit unit includes:
Host interface is electrically connected to host system；
Memory interface is electrically connected to the reproducible nonvolatile memorizer module；
Error checking and correcting circuit；And
Memory management circuitry is electrically connected to the host interface, the memory interface and the error checking and correction Circuit,
Wherein the memory management circuitry is to send the first reading instruction sequence, wherein described first reads instruction sequence use The first area in the reproducible nonvolatile memorizer module is read according to the first reading voltage quasi position with instruction, with The first coding unit is obtained, wherein first coding unit belongs to block code,
Wherein the error checking and correcting circuit be to execute the first decoding program to first coding unit, and described Memory management circuitry also to record the first decoded information,
Wherein the memory management circuitry is also to send the second reading instruction sequence, wherein described second reads instruction sequence To indicate to read the first area according to the second reading voltage quasi position, to obtain the second coding unit, wherein described the Two coding units belong to the block code,
Wherein the error checking and correcting circuit are also to execute the second decoding program, and institute to second coding unit State memory management circuitry also to record the second decoded information,
Wherein the memory management circuitry according to first decoded information with second decoded information also to estimate And obtain third and read voltage quasi position,
Wherein the memory management circuitry also reads instruction sequence to send third, wherein the third reads instruction sequence The first area is read to indicate to read voltage quasi position according to the third, to obtain third coding unit,
Wherein the error checking and correcting circuit are also to execute third decoding program to the third coding unit.
24. memorizer control circuit unit according to claim 23, which is characterized in that the block code is by multiple sub- volumes Code unit forms, and the first bit in a little coding unit is determined by multiple coded programs.
25. memorizer control circuit unit according to claim 24, which is characterized in that those coded programs have difference Coding direction.
26. memorizer control circuit unit according to claim 23, which is characterized in that first decoded information includes First numerical value, second decoded information includes second value,
Wherein the memory management circuitry is estimated and is obtained with second decoded information according to first decoded information The operation that the third reads voltage quasi position includes:
Compare first numerical value and the second value and determines that the third reads voltage quasi position according to comparison result.
27. memorizer control circuit unit according to claim 26, which is characterized in that first numerical value and described the First decoding result of one decoding program is related, and the second decoding result of the second value and second decoding program has It closes.
28. memorizer control circuit unit according to claim 27, which is characterized in that first numerical value is to be positively correlated In the first successfully decoded unit number of first decoding program, the second value is to be positively correlated with second decoding program The second successfully decoded unit number.
29. memorizer control circuit unit according to claim 28, which is characterized in that the memory management circuitry is also To obtain the first row successfully decoded unit number and first row successfully decoded unit number according to first decoding result,
Wherein the memory management circuitry according to the first row successfully decoded unit number and the first row also to decode Success unit number determines first numerical value,
Wherein the memory management circuitry is also to obtain the second row successfully decoded unit number according to second decoding result With secondary series successfully decoded unit number,
Wherein the memory management circuitry according to the second row successfully decoded unit number and the secondary series also to decode Success unit number determines the second value.
30. memorizer control circuit unit according to claim 23, which is characterized in that the memory management circuitry root The operation packet that the third reads voltage quasi position is estimated and obtained according to first decoded information and second decoded information It includes:
One of the first reading voltage quasi position and the second reading voltage quasi position are determined as the third to read Voltage quasi position.
31. memorizer control circuit unit according to claim 23, which is characterized in that the memory management circuitry is also To judge whether first decoding program fails,
It is to determine first decoding that wherein the memory management circuitry, which sends the operation of the second reading instruction sequence, It is executed after procedure failure.
32. memorizer control circuit unit according to claim 23, which is characterized in that the memory management circuitry is also It is executed to read voltage quasi position according to the third related with the reproducible nonvolatile memorizer module default Operation,
Wherein the predetermined registration operation includes at least one of following operation:
It indicates to read the first area to obtain the multiple soft bits for corresponding to third decoding unit and the error checking With correcting circuit also to execute iterative decoding to the third decoding unit according to those soft bits；
Determine the extent of deterioration of multiple storage units in the first area or the voltage's distribiuting state of those storage units；With And
Determine the pre-set programs voltage for corresponding to the first area.
33. memorizer control circuit unit according to claim 23, which is characterized in that first decoding program and institute Stating the second decoding program is all hard bit mode decoding.
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