CN109901784A - Data access method, memorizer control circuit unit and memorizer memory devices - Google Patents

Abstract

A kind of data access method, memorizer control circuit unit and memorizer memory devices.The method includes: to read voltage using first to read first instance programmed cell to obtain the first data；Voltage, which is read, using second reads first instance programmed cell to obtain the second data；Second state parameter of the first state parameter of corresponding first data and corresponding second data is input to numerical operation engine, and determines that the third for reading first instance programmed cell reads voltage by numerical operation engine.

Description

Data access method, memorizer control circuit unit and memorizer memory devices

Technical field

The present invention relates to a kind of data access method, memorizer control circuit unit and memorizer memory devices, especially It is related to a kind of using the data access method of numerical operation engine, memorizer control circuit unit and memorizer memory devices.

Background technique

Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data It is non-volatile, power saving, small in size, and without characteristics such as mechanical structures, so being very suitable to be built into above-mentioned illustrated various In portable multimedia device.In particular, recently as numerical operation (for example, artificial intelligence, neural network or depth Practise network) rise, how by numerical operation be applied to reproducible nonvolatile memorizer module it is non-to promote duplicative The service efficiency of volatile and one of the problem of those skilled in the art to be solved.

Summary of the invention

The present invention provides a kind of data access method, memorizer control circuit unit and memorizer memory devices.It is described Data access method can be in the access efficiency for promoting reproducible nonvolatile memorizer module by numerical operation engine.

The present invention provides a kind of data access method, is used for reproducible nonvolatile memorizer module.Duplicative is non- Volatile have multiple entity erased cells, the multiple entity erased cell each of entity erase Unit has multiple entity program units.The data access method includes: using at least 1 the in multiple reading voltages One reading voltage reads the first instance programmed cell in the multiple entity program unit to obtain the first data；It uses At least one second reading voltage in the multiple reading voltage reads the first instance programmed cell to obtain the second number According to；Second state parameter of the first state parameter of correspondence first data and corresponding second data is input to number It is worth computation engine；According to the first state parameter and second state parameter, determined by the numerical operation engine Voltage is read for reading the third of the first instance programmed cell in the multiple reading voltage；And use described the Three reading voltage readings take the first instance programmed cell to obtain third data.

In one embodiment of this invention, it is read wherein reading voltage using described first in the multiple reading voltage The step of first instance programmed cell in the multiple entity program unit is to obtain first data include: The first decoding operate is executed to correct the mistake in first data according to first coding data, and works as first data It is middle when there is the mistake that can not be corrected, it executes and reads voltage using described second in the multiple reading voltage and read described the The step of one entity program unit is to obtain second data.Wherein using described second in the multiple reading voltage Reading voltage and reading the step of first instance programmed cell is to obtain second data includes: to execute first solution Code is operated to correct the mistake in second data according to the second coded data, and can not when existing in second data When the mistake of corrigendum, the institute by the first state parameter of correspondence first data and corresponding second data is executed State the step of the second state parameter is input to the numerical operation engine.

In one embodiment of this invention, wherein it is to read the first instance programmed cell that the third, which reads voltage, Best reading voltage.

In one embodiment of this invention, the method also includes: execute first decoding operate to compile according to third Mistake in third data described in code data correcting；When mistake is not present in the third data, the third data are exported； When the mistake in the third data is corrected, the third data righted the wrong are exported；And work as the third number When according to the middle mistake that exists and can not correct, judge reading the first instance programmed cell using first decoding operate During fail.

In one embodiment of this invention, wherein the first state parameter includes first data, first number The first of bit value is 0 in total, described first data for being 1 according to middle bit value sum or corresponding first data The summation of syndrome.

In one embodiment of this invention, second state parameter includes second data, in second data Second verification of bit value is 0 in total, described second data that bit value is 1 sum or corresponding second data The summation of son.

In one embodiment of this invention, the method also includes: in the reproducible nonvolatile memorizer module When just powering on, it is loaded into from the reproducible nonvolatile memorizer module and joins via an at least operation obtained from preparatory training Number is into the numerical operation engine.

In one embodiment of this invention, wherein the operational parameter includes predefined weight or offset, wherein root According to the first state parameter and second state parameter, the multiple reading electricity is determined by the numerical operation engine The step of in pressure for reading the third reading voltage of the first instance programmed cell includes: to be transported by the numerical value Engine is calculated to be determined according to the first state parameter, second state parameter and the predefined weight or the offset The fixed third reads voltage.

In one embodiment of this invention, the method also includes: from host system receive the first write instruction；It will correspond to The third state parameter of first write instruction is input in the numerical operation engine；And drawn by the numerical operation Hold up the type that the first write-in data of corresponding first write instruction are determined according to the third state parameter.

In one embodiment of this invention, wherein the third state parameter includes corresponding to the first write-in data First logical address, location parameter or instruction kenel, wherein by the numerical operation engine according to the third state parameter The step of determining the type of the first write-in data of corresponding first write instruction includes: to be drawn by the numerical operation It holds up and the first write-in data is judged for dsc data or cold data, wherein the dsc data is deposited according to the third state parameter The frequency taken is higher than the frequency that the cold data is accessed.

A kind of memorizer control circuit unit is provided in the present invention, is used for reproducible nonvolatile memorizer module.Institute Stating reproducible nonvolatile memorizer module has multiple entity erased cells, every among the multiple entity erased cell One entity erased cell has multiple entity program units, and the memorizer control circuit unit includes: host interface, deposits Memory interface, numerical operation engine and memory management circuitry.Host interface is electrically connected to host system.Memory Interface is electrically connected to the reproducible nonvolatile memorizer module.Memory management circuitry is electrically connected to described Host interface, the memory interface and the numerical operation engine.The memory management circuitry is to use multiple readings At least one first reading voltage in voltage is taken to read the first instance programmed cell in the multiple entity program unit To obtain the first data.The memory management circuitry is also to use at least one second in the multiple reading voltage to read Voltage reads the first instance programmed cell to obtain the second data.The memory management circuitry will be also will correspond to institute Second state parameter of the first state parameter and corresponding second data of stating the first data is input to the numerical operation Engine.The numerical operation engine is the multiple to be determined according to the first state parameter and second state parameter It reads in voltage and reads voltage for reading the third of the first instance programmed cell.The memory management circuitry is also used The first instance programmed cell is read to use the third to read voltage to obtain third data.

In one embodiment of this invention, wherein reading voltage reading using described first in the multiple reading voltage It takes in running of the first instance programmed cell in the multiple entity program unit to obtain first data, The memory management circuitry executes the first decoding operate to correct the mistake in first data according to first coding data, And when there is the mistake that can not be corrected in first data, execute using described second in the multiple reading voltage It reads voltage and reads the first instance programmed cell to obtain the running of second data.Wherein using the multiple The the second reading voltage read in voltage reads the first instance programmed cell to obtain the fortune of second data In work, the memory management circuitry executes first decoding operate to correct second data according to the second coded data In mistake, and when there is the mistake that can not be corrected in second data, execute the institute of correspondence first data Second state parameter for stating first state parameter and corresponding second data is input to the numerical operation engine Running.

In one embodiment of this invention, it is read the first instance programmed cell one that the third, which reads voltage, It is best to read voltage.

In one embodiment of this invention, the memory management circuitry executes first decoding operate according to third Coded data corrects the mistake in the third data.When mistake is not present in the third data, the memory management Third data described in circuit output.When the mistake in the third data is corrected, the memory management circuitry output is The third data righted the wrong.When there is the mistake that can not be corrected in the third data, the memory management electricity Road judges to fail during reading the first instance programmed cell using first decoding operate.

In one embodiment of this invention, wherein the first state parameter includes first data, first number The first of bit value is 0 in total, described first data for being 1 according to middle bit value sum or corresponding first data The summation of syndrome.

In one embodiment of this invention, second state parameter includes second data, in second data Second verification of bit value is 0 in total, described second data that bit value is 1 sum or corresponding second data The summation of son.

In one embodiment of this invention, wherein when the reproducible nonvolatile memorizer module just powers on, institute State memory management circuitry from the reproducible nonvolatile memorizer module be loaded into via obtained from preparatory training at least One operational parameter is into the numerical operation engine.

In one embodiment of this invention, wherein the operational parameter includes predefined weight or offset, wherein root According to the first state parameter and second state parameter, the numerical operation engine is determined in the multiple reading voltage For read the first instance programmed cell the third read voltage running in, the numerical operation engine according to The first state parameter, second state parameter and the predefined weight or the offset determine the third Read voltage.

In one embodiment of this invention, wherein the memory management circuitry receives the first write-in from the host system The third state parameter of correspondence first write instruction is input to the numerical operation by instruction, the memory management circuitry In engine and the numerical operation engine determines to correspond to the first of first write instruction according to the third state parameter The type of data is written.

In one embodiment of this invention, wherein the third state parameter includes corresponding to the first write-in data First logical address, location parameter or instruction kenel, wherein being determined in the numerical operation engine according to the third state parameter Surely in the running for corresponding to the type of the first write-in data of first write instruction, the numerical operation engine is according to institute It states third state parameter and judges the first write-in data for dsc data or cold data, wherein the frequency that the dsc data is accessed The frequency being accessed higher than the cold data.

A kind of memorizer memory devices are proposed in the present invention.Memorizer memory devices include connecting interface unit, can make carbon copies Formula non-volatile memory module and memorizer control circuit unit.Connecting interface unit is electrically connected to host system System.Reproducible nonvolatile memorizer module has multiple entity erased cells, among the multiple entity erased cell Each entity erased cell has multiple entity program units.Memorizer control circuit unit is electrically connected to the connection Interface unit is with the reproducible nonvolatile memorizer module and with numerical operation engine.The memory control electricity Road unit is read in the multiple entity program unit to use at least one first in multiple reading voltages to read voltage A first instance programmed cell to obtain one first data.The memorizer control circuit unit is also described more to use At least one second in a reading voltage, which reads voltage, reads the first instance programmed cell to obtain the second data.It is described First state parameter and corresponding second data of the memorizer control circuit unit also first data will be corresponded to The second state parameter be input to the numerical operation engine, and joined by the numerical operation engine according to the first state Several and described second state parameter determines in the multiple reading voltage for reading the first instance programmed cell Third reads voltage.The memorizer control circuit unit also reads the first instance to use the third to read voltage Programmed cell is to obtain third data.

In one embodiment of this invention, wherein reading voltage reading using described first in the multiple reading voltage It takes in running of the first instance programmed cell in the multiple entity program unit to obtain first data, The memorizer control circuit unit executes the first decoding operate to correct in first data according to first coding data Mistake, and when there is the mistake that can not be corrected in first data, execute using the institute in the multiple reading voltage It states the second reading voltage and reads the first instance programmed cell to obtain the running of second data.Wherein using institute It states the second reading voltage in multiple reading voltages and reads the first instance programmed cell to obtain second number According to running in, the memorizer control circuit unit executes first decoding operate to correct institute according to the second coded data State the mistake in the second data, and when there is the mistake that can not be corrected in second data, executing will corresponding described the Second state parameter of the first state parameter of one data and corresponding second data is input to the numerical value The running of computation engine.

In one embodiment of this invention, wherein it is to read the first instance programmed cell that the third, which reads voltage, Best reading voltage.

In one embodiment of this invention, the memorizer control circuit unit executes first decoding operate with basis Third coded data corrects the mistake in the third data.When mistake is not present in the third data, the memory Control circuit unit exports the third data.When the mistake in the third data is corrected, the memory control electricity Road unit exports the third data righted the wrong.It is described when there is the mistake that can not be corrected in the third data Memorizer control circuit unit judges are in the process for reading the first instance programmed cell using first decoding operate It is middle to fail.

In one embodiment of this invention, the first state parameter includes first data, in first data First verification of bit value is 0 in total, described first data that bit value is 1 sum or corresponding first data The summation of son.

In one embodiment of this invention, second state parameter includes second data, in second data Second verification of bit value is 0 in total, described second data that bit value is 1 sum or corresponding second data The summation of son.

In one embodiment of this invention, described to deposit when the reproducible nonvolatile memorizer module just powers on Memory control circuit unit from the reproducible nonvolatile memorizer module be loaded into via obtained from preparatory training at least One operational parameter is into the numerical operation engine.

In one embodiment of this invention, the operational parameter includes predefined weight or offset, wherein the number Value computation engine determines to be used in the multiple reading voltage according to the first state parameter and second state parameter The third for reading the first instance programmed cell is read in the running of voltage, and the numerical operation engine is according to First state parameter, second state parameter and the predefined weight or the offset determine that the third is read Voltage.

In one embodiment of this invention, the memorizer control circuit unit receives the first write-in from the host system The third state parameter of correspondence first write instruction is input to the numerical value by instruction, the memorizer control circuit unit In computation engine, and determine that corresponding first write-in refers to according to the third state parameter by the numerical operation engine The type of the first write-in data enabled.

In one embodiment of this invention, wherein the third state parameter includes corresponding to the first write-in data First logical address, a location parameter or instruction kenel, wherein by the numerical operation engine according to the third state Parameter determines in the running of the type of the first write-in data of corresponding first write instruction that the memory storage fills It sets and judges the first write-in data for dsc data or cold number according to the third state parameter by the numerical operation engine According to wherein the frequency that the dsc data is accessed is higher than the frequency that the cold data is accessed.

It can read from reproducible nonvolatile memorizer module based on above-mentioned, of the invention data access method When data, by the judgement of numerical operation engine for reading the best reading voltage of an entity program unit, reduce whereby The time it takes in (Retry-Read) mechanism is re-read, and promotes the access of reproducible nonvolatile memorizer module Efficiency.In addition, can judge to write by numerical operation engine when reproducible nonvolatile memorizer module is written Enter whether data are cold data or dsc data, can also judge to be written whether data can be compressed by numerical operation engine, by This can make memory management circuitry can choose optimal mode when executing the write-in of data and be written.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.

Detailed description of the invention

Fig. 1 is host system, memorizer memory devices and input/output shown in an exemplary embodiment according to the present invention (I/O) schematic diagram of device.

Fig. 2 is host system shown in another exemplary embodiment according to the present invention, memorizer memory devices and I/O device Schematic diagram.

Fig. 3 is the signal of host system and memorizer memory devices shown in another exemplary embodiment according to the present invention Figure.

Fig. 4 is the schematic block diagram of memorizer memory devices shown in an exemplary embodiment according to the present invention.

Fig. 5 is the schematic block diagram of the reproducible nonvolatile memorizer module according to shown in an exemplary embodiment.

Fig. 6 is the schematic diagram of the memory cell according to shown in an exemplary embodiment.

Fig. 7 is grid voltage corresponding to the write-in data that are stored in memory cell according to an exemplary embodiment Statistics distribution diagram.

Fig. 8 is the schematic diagram for reading data from memory cell according to shown in an exemplary embodiment.

Fig. 9 is the schematic diagram for reading data from memory cell according to shown in another exemplary embodiment.

Figure 10 is the example schematic of the entity erased cell according to shown in this exemplary embodiment.

Figure 11 is the schematic block diagram of memorizer control circuit unit shown in an exemplary embodiment according to the present invention.

Figure 12 is the schematic diagram of more frame codes shown in an exemplary embodiment according to the present invention.

Figure 13 is the model of multiple entity program unit groups in the entity erased cell according to shown in this exemplary embodiment It illustrates and is intended to.

Figure 14 is to show shown in an exemplary embodiment according to the present invention for re-reading the reading voltage group of mechanism It is intended to.

Figure 15 is the flow chart of the data access method according to shown in an exemplary embodiment.

Symbol description:

10: memorizer memory devices；

11: host system；

110: system bus；

111: processor；

112: random access memory；

113: read-only memory；

114: data transmission interface；

12: input/output (I/O) device；

20: motherboard；

201: portable disk；

202: memory card；

203: solid state hard disk；

204: radio memory storage device；

205: GPS module；

206: network interface card；

207: radio transmitting device；

208: keyboard；

209: screen；

210: loudspeaker；

32:SD card；

33:CF card；

34: embedded storage device；

341: embedded multi-media card；

342: embedded type multi-core piece encapsulates storage device；

402: connecting interface unit；

404: memorizer control circuit unit；

406: reproducible nonvolatile memorizer module；

2202: memory cell；

2204: character line control circuit；

2206: bit line control circuit；

2208: row decoder；

2210: data input/output buffer；

2212: control circuit；

502: memory cell；

504: bit line；

506: word-line；

508: common source line；

512: select grid drain electrode transistor；

514: select grid source electrode transistor；

LSB: minimum effective bit；

CSB: intermediate significant bit；

MSB: highest significant bit；

VA、VB、VC、VD、VE、VF、VG、VA_1、VB_1、VC_1、VD_1、VE_1、VF_1、VG_1、VA_2、VB_2、VC_ 2、VD_2、VE_2、VF_2、VG_2、VA_3、VB_3、VC_3、VD_3、VE_3、VF_3、VG_3、VA_n、VB_n、VC_n、VD_n、 VE_n, VF_n, VG_n: voltage is read；

L_0~L_N: lower entity program unit；

M_0~M_N: middle entity program unit；

U_0~U_N: upper entity program unit；

1301,1303,1305,1307,1309,1311: entity program unit group；

702: memory management circuitry；

704: host interface；

706: memory interface；

708: error checking and correcting circuit；

710: buffer storage；

712: electric power management circuit；

714: numerical operation engine；

801 (1)~801 (r): position；

820: coded data；

810 (0)~810 (E): entity program unit；

RR_1~RR_n: voltage group is read；

S1501: first in multiple entity program units is read using the first reading voltage in multiple reading voltages The step of entity program unit is to obtain the first data；

S1503: first instance programmed cells are read to obtain the using the second reading voltages in multiple reading voltages The step of two data；

S1505: the second state parameter of the first state parameter of corresponding first data and corresponding second data is inputted The step of to numerical operation engine；

S1507: the multiple reading is determined according to first state parameter and the second state parameter by numerical operation engine It takes in voltage for reading the step of third of first instance programmed cell reads voltage；

S1509: voltage is read using the third and reads the step of first instance programmed cell is to obtain third data.

Specific embodiment

In general, memorizer memory devices (also referred to as, memory storage system) include duplicative non-volatile memories Device module (rewritable non-volatile memory module) and controller (also referred to as, control circuit).It is commonly stored Device storage device is used together with host system, so that host system can write data into memorizer memory devices or from depositing Data are read in reservoir storage device.

Fig. 1 is host system, memorizer memory devices and input/output shown in an exemplary embodiment according to the present invention (I/O) schematic diagram of device.Fig. 2 is host system shown in another exemplary embodiment according to the present invention, memory storage dress It sets and the schematic diagram of I/O device.

Fig. 1 and Fig. 2 are please referred to, host system 11 generally comprises processor 111, random access memory (random Access memory, RAM) 112, read-only memory (read only memory, ROM) 113 and data transmission interface 114.Place Reason device 111, random access memory 112, read-only memory 113 and data transmission interface 114 are all electrically connected to system bus (system bus)110。

In this exemplary embodiment, host system 11 is by 10 electricity of data transmission interface 114 and memorizer memory devices Property connection.For example, host system 11 can be via data transmission interface 114 by data storage to memorizer memory devices 10 or from depositing Data are read in reservoir storage device 10.In addition, host system 11 is electrically connected by system bus 110 and I/O device 12. For example, output signal can be sent to I/O device 12 via system bus 110 or received from I/O device 12 defeated by host system 11 Enter signal.

In this exemplary embodiment, processor 111, random access memory 112, read-only memory 113 and data transmission Interface 114 may be provided on the motherboard 20 of host system 11.The number of data transmission interface 114 can be one or more.It is logical Data transmission interface 114 is crossed, motherboard 20 can be electrically connected to memorizer memory devices 10 via wired or wireless way.It deposits Reservoir storage device 10 can be for example portable disk 201, memory card 202, solid state hard disk (Solid State Drive, SSD) 203 Or radio memory storage device 204.Radio memory storage device 204 can be for example close range wireless communication (Near Field Communication, NFC) memorizer memory devices, radio facsimile (WiFi) memorizer memory devices, bluetooth (Bluetooth) memorizer memory devices or low-power consumption bluetooth memorizer memory devices (for example, iBeacon) etc. are with various wireless Memorizer memory devices based on mechanics of communication.In addition, motherboard 20 can also be electrically connected to entirely by system bus 110 Ball positioning system (Global Positioning System, GPS) module 205, network interface card 206, radio transmitting device 207, the various I/O device such as keyboard 208, screen 209, loudspeaker 210.For example, motherboard 20 can pass through in an exemplary embodiment 207 access wireless memorizer memory devices 204 of radio transmitting device.

In an exemplary embodiment, mentioned host system is substantially to cooperate with memorizer memory devices to store The arbitrary system of data.Although host system is explained with computer system, however, Fig. 3 is in above-mentioned exemplary embodiment The schematic diagram of host system and memorizer memory devices shown in another exemplary embodiment according to the present invention.Referring to figure 3., exist In another exemplary embodiment, host system 31 is also possible to digital camera, video camera, communication device, audio player, video and broadcasts The systems such as device or tablet computer are put, and memorizer memory devices 30 can be its used SD card 32, CF card 33 or embedded storage The various non-volatile memory storage device such as cryopreservation device 34.Embedded storage device 34 includes embedded multi-media card (embedded MMC, eMMC) 341 and/or embedded type multi-core piece encapsulate storage device (embedded Multi Chip Package, eMCP) embedded storage on all types of substrates that memory module is directly electrically connected to host system such as 342 Cryopreservation device.

Fig. 4 is the schematic block diagram of memorizer memory devices shown in an exemplary embodiment according to the present invention.

Referring to figure 4., memorizer memory devices 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.

In this exemplary embodiment, connecting interface unit 402 is to be compatible to serial advanced attachment (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, connecting interface unit 402 are also possible to meet parallel advanced attachment (Parallel Advanced Technology Attachment, PATA) mark Quasi-, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, secure digital (Secure Digital, SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multi-chip envelope Fill (Multi-Chip Package) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, down Enter formula Multi Media Card (Embedded Multimedia Card, eMMC) interface standard, general flash memory (Universal Flash Storage, UFS) interface standard, embedded type multi-core piece encapsulate (embedded Multi Chip Package, eMCP) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.Connecting interface unit 402 can with deposit Memory control circuit unit 404 is encapsulated in a chip or connecting interface unit 402 is to be laid in one to include memory control Outside the chip of circuit unit 404 processed.

Memorizer control circuit unit 404 is to execute multiple logic gates or control with hardware pattern or firmware pattern implementation System instructs and carries out writing for data in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The running such as enter, read and erase.

Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404 and uses To store the data that host system 11 is written.Reproducible nonvolatile memorizer module 406 can be single-order memory cell (Single Level Cell, SLC) NAND type flash memory module is (that is, can store the fast of 1 bit in a memory cell Flash memory module), multistage memory cell (Multi Level Cell, MLC) NAND type flash memory module (that is, one note Recall the flash memory module that 2 bits can be stored in born of the same parents), Complex Order memory cell (Triple Level Cell, TLC) NAND Type flash memory module (that is, flash memory module that 3 bits can be stored in a memory cell), other flash memories Module or other memory modules with the same characteristics.

Memory cell in reproducible nonvolatile memorizer module 406 is to be arranged in array fashion.Below with two dimension Array is illustrated memory cell.But herein it is noted that following exemplary embodiment is memory cell A kind of example, in other exemplary embodiments, the configuration mode of memory cell can be adjusted to meet the need in practice It asks.

Fig. 5 is the schematic block diagram of the reproducible nonvolatile memorizer module according to shown in an exemplary embodiment.Fig. 6 It is the schematic diagram of the memory cell according to shown in an exemplary embodiment.

Referring to Fig. 5 and Fig. 6, reproducible nonvolatile memorizer module 406 includes memory cell 2202, word First line control circuit 2204, bit line control circuit 2206, row decoder (column decoder) 2208, data input/defeated Buffer 2210 and control circuit 2212 out.

In this exemplary embodiment, memory cell 2202 may include to store multiple memory cells 502 of data, multiple Select grid drain electrode (select gate drain, SGD) transistor 512 and multiple select grid source electrodes (select gate Source, SGS) transistor 514 and connect a plurality of bit line 504, a plurality of word-line 506 and common source of these memory cells Polar curve 508 (as shown in Figure 6).Memory cell 502 is by array manner (or in a manner of solid stacks) configuration in bit line 504 and word On the crosspoint of first line 506.When receiving write instruction from memorizer control circuit unit 404 or reading instruction, control electricity It road 2212 can control character line control circuit 2204, bit line control circuit 2206, row decoder 2208, data input/output Buffer 2210 writes data to memory cell 2202 or reads from memory cell 2202 data, wherein character line traffic control Circuit 2204 processed is bestowed to control to bit to control the voltage bestowed to word-line 506, bit line control circuit 2206 The voltage of line 504, row decoder 2208 select corresponding bit line according to the column address in instruction, and data input/defeated Buffer 2210 is configured to temporarily store data out.

Memory cell in reproducible nonvolatile memorizer module 406 is to store more bits with the change of critical voltage (bits).Specifically, there is a charge-trapping between the control grid (control gate) and channel of each memory cell Layer.By bestowing a write-in voltage to controlling grid, thus it is possible to vary charge mends the amount of electrons for catching layer, thus changes memory cell Critical voltage.This program for changing critical voltage is also referred to as " writing the data to memory cell " or " programmable memory cell ".With Each memory cell of the change of critical voltage, memory cell 2202 has multiple storing states.And it can by reading voltage To judge memory cell is which storing state belonged to, the bit stored by memory cell is obtained whereby.

Fig. 7 is grid voltage corresponding to the write-in data that are stored in memory cell according to an exemplary embodiment Statistics distribution diagram.

Fig. 7 is please referred to, by taking MLC NAND type flash memory as an example, with different critical voltages, each memory cell tool There are 4 kinds of storing states, and these storing states respectively represent bits such as " 11 ", " 10 ", " 00 " and " 01 ".In other words, often One storing state includes minimum effective bit (Least Significant Bit, LSB) and highest significant bit (Most Significant Bit, MSB).In this exemplary embodiment, from a left side in storing state (that is, " 11 ", " 10 ", " 00 " and " 01 ") The 1st bit that side is counted is LSB, and the 2nd bit counted from left side is MSB.Therefore, in this exemplary embodiment, often One memory cell can store 2 bits.It will be appreciated that critical voltage shown in Fig. 7 and its storing state to should be only one A example.In another exemplary embodiment of the present invention, critical voltage is corresponding with storing state to be can also be as critical voltage is got over It arranges greatly and with " 11 ", " 10 ", " 01 " and " 00 " or other is arranged.In addition, also can define in another exemplary embodiment The 1st bit counted from left side is MSB, and the 2nd bit counted from left side is LSB.

The example of multiple bits (for example, MLC or TLC NAND quick-flash memory module) can be stored in a memory cell In embodiment, the entity program unit for belonging to same word-line can at least be classified as lower entity program unit and upper reality Body programmed cell.For example, in MLC NAND quick-flash memory module, the minimum effective bit (Least of a memory cell Significant Bit, LSB) it is to belong to lower entity program unit, and the highest significant bit (Most of this memory cell Significant Bit, MSB) it is to belong to entity program unit.In an exemplary embodiment, lower entity program unit Also referred to as fast page (fast page), and upper entity program unit is also referred to as slow page (slow page).In addition, in TLC NAND In flash memory module, the minimum effective bit (Least Significant Bit, LSB) of a memory cell is to belong to lower reality The intermediate significant bit (Center Significant Bit, CSB) of body programmed cell, this memory cell is to belong to middle entity journey Sequence unit, and the highest significant bit (Most Significant Bit, MSB) of this memory cell is to belong to entity program Change unit.

Fig. 8 is the schematic diagram for reading data from memory cell according to shown in an exemplary embodiment, is with MLC NAND For type flash memory.

Please refer to Fig. 8, the reading running of the memory cell of memory cell 2202 be by bestow read voltage VA~VC in Grid is controlled, by the on state in memory cell channel, carrys out the data of recognition memory born of the same parents storage.Verifying bit (VA) is to refer to Show and bestows whether memory cell channel when reading voltage VA is conducting；Verifying bit (VC) is to read voltage VC to indicate to bestow When, whether memory cell channel is conducting；Verifying bit (VB) is when reading voltage VB to indicate to bestow, and whether memory cell channel For conducting.It is assumed herein that verifying bit indicates corresponding memory cell channel conductive when being " 1 ", and verifying when bit is " 0 " indicates Corresponding memory cell channel is not turned on.As shown in figure 8, may determine that memory cell is to be in by verifying bit (VA)~(VC) Which storing state, and then obtain stored bit.

Fig. 9 is the schematic diagram for reading data from memory cell according to shown in another exemplary embodiment.

Fig. 9 is please referred to, by taking a TLC NAND type flash memory as an example, each storing state includes that left side is counted Intermediate significant bit (the Center of the minimum effective bit LSB of 1 bit, the 2nd counted from left side bit Significant Bit, CSB) and the highest significant bit MSB of the 3rd bit counted from left side.In this example, according to According to different critical voltages, memory cell have 8 kinds of storing states (that is, " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " with " 011 ").It, can be with the ratio stored by recognition memory born of the same parents by application reading voltage VA~VG in control grid It is special.

Wherein, it is worth noting that, putting in order for 8 kinds of storing states of Fig. 9 can be ordered according to the design of manufacturer, non- It is limited with the arrangement mode of this example.

In addition, the memory cell of reproducible nonvolatile memorizer module 406 can constitute multiple entity program units, and And these entity program units can constitute multiple entity erased cells.Specifically, the memory in Fig. 6 on same word-line Born of the same parents can form one or more entity program units.For example, if reproducible nonvolatile memorizer module 406 is MLC NAND Type flash memory module, then the memory cell on the staggered place of same word-line and a plurality of bit line can constitute 2 entity journeys Sequence unit namely upper entity program unit and lower entity program unit.And a upper entity program unit and one Lower entity program unit may be collectively referred to as an entity program unit group.If in particular, the data bit to be read is real one It, can be real under this using being identified such as the reading voltage VA in Fig. 8 when the unit of entity program once of body programmed cell group The value of each bit in body programmed cell.If the data to be read are located at entity journey on the one of an entity program unit group When sequence unit, it can be identified using voltage VB and reading voltage VC is read in such as Fig. 8 every in entity program unit on this The value of one bit.

Alternatively, if reproducible nonvolatile memorizer module 406 is TLC NAND type flash memory module, it is same Memory cell on the staggered place of word-line and a plurality of bit line can constitute 3 entity program units namely upper entity program Change unit, middle entity program unit and lower entity program unit.And upper an entity program unit, a middle entity journey Sequence unit and a lower entity program unit may be collectively referred to as an entity program unit group.If in particular, being intended to read Data bit in the unit of entity program once of an entity program unit group, can be using such as the reading voltage in Fig. 9 VA identifies the value of each bit in this lower entity program unit.If the data to be read are located at an entity program unit In the one of group when entity program unit, it can be identified in this in fact using such as the reading voltage VB in Fig. 9 with voltage VC is read The value of each bit in body programmed cell.If the data bit to be read entity journey on the one of an entity program unit group When sequence unit, can using as in Fig. 9 reading voltage VD, read voltage VE, read voltage VF and know with reading voltage VG Not on this in entity program unit each bit value.

In this exemplary embodiment, entity program unit is the minimum unit of sequencing.That is, entity program unit is The minimum unit of data is written.For example, entity program unit is physical page (page) or entity fan (sector).If real Body programmed cell is physical page, then these entity program units generally include data bit area and redundancy (redundancy) bit area.Data bit area is fanned comprising multiple entities, and to store user's data, and redundancy ratio special zone is used With stocking system data (for example, error correcting code).In this exemplary embodiment, data bit area includes 32 entity fans, and The size of one entity fan is 512 bytes (byte, B).However, can also be wrapped in data bit area in other exemplary embodiments Containing 8,16 or number more or fewer entities fan, and the size of each entity fan be also possible to it is greater or lesser. On the other hand, entity erased cell is the minimum unit erased.That is, each entity erased cell contains minimal amount together The memory cell being erased.For example, entity erased cell is physical blocks (block).

Figure 10 is the example schematic of the entity erased cell according to shown in this exemplary embodiment.

Figure 10 is please referred to, in this exemplary embodiment, it is assumed that an entity erased cell is by multiple entity program lists Tuple is formed, wherein each entity program unit group includes several memory cell institutes group by being arranged on same word-line At lower entity program unit, middle entity program unit and upper entity program unit.For example, in entity erased cell In, belong to the 0th entity program unit of lower entity program unit, belong to the 1st entity of middle entity program unit Programmed cell and the 2nd entity program unit for belonging to entity program unit can be considered as an entity program list Tuple.Similarly, the 3rd, 4,5 entity program unit can be considered as an entity program unit group, and and so on Other entity program units are also that multiple entity program unit groups are divided into according to this mode.

Figure 11 is the schematic block diagram of memorizer control circuit unit shown in an exemplary embodiment according to the present invention.

Figure 11 is please referred to, memorizer control circuit unit 404 includes memory management circuitry 702, host interface 704, deposits Memory interface 706 and error checking and correcting circuit 708.

Overall operation of the memory management circuitry 702 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 702, has multiple control instructions, and when memorizer memory devices 10 operate, these control instructions can quilt It executes the running such as to carry out the write-in of data, read and erase.Illustrate that memory management circuitry 702 or any be contained in are deposited below When the operation of the circuit element in memory control circuit unit 404, it is equal to the behaviour for illustrating memorizer control circuit unit 404 Make.

In this exemplary embodiment, the control instruction of memory management circuitry 702 is to carry out implementation with firmware pattern.For example, Memory management circuitry 702 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memorizer memory devices 10 operate, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.

In another exemplary embodiment, the control instruction of memory management circuitry 702 can also be stored in procedure code pattern The specific region of reproducible nonvolatile memorizer module 406 is (for example, be exclusively used in storage system data in memory module System area) in.In addition, memory management circuitry 702 have microprocessor unit (not shown), read-only memory (not shown) and Random access memory (not shown).In particular, this read-only memory has boot code (boot code), and work as memory When control circuit unit 404 is enabled, microprocessor unit can first carry out this boot code, and will to be stored in duplicative non-volatile Control instruction in property memory module 406 is loaded into the random access memory of memory management circuitry 702.Later, micro- Processor unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.

In addition, the control instruction of memory management circuitry 702 can also be come in another exemplary embodiment with a hardware pattern Implementation.For example, memory management circuitry 702 includes microcontroller, memory cell management circuit, memory write circuit, memory Reading circuit, memory are erased circuit and data processing circuit.Memory cell manages circuit, memory write circuit, memory and reads Sense circuit, memory erase circuit and data processing circuit is electrically connected to microcontroller.Memory cell manages circuit to pipe Manage memory cell or its group of reproducible nonvolatile memorizer module 406.Memory write circuit is to duplicative Non-volatile memory module 406 assigns write instruction sequence to write data into reproducible nonvolatile memorizer module In 406.Memory reading circuitry reads instruction sequence to assign to reproducible nonvolatile memorizer module 406 with from can Data are read in manifolding formula non-volatile memory module 406.Memory erases circuit to deposit to duplicative is non-volatile Memory modules 406, which are assigned, erases instruction sequence so that data to be erased from reproducible nonvolatile memorizer module 406.Data Processing circuit to handle be intended to be written data to reproducible nonvolatile memorizer module 406 and from duplicative it is non-easily The data read in the property lost memory module 406.Write instruction sequence reads instruction sequence and instruction sequence of erasing can be wrapped distinctly Include one or more procedure codes or instruction code and to indicate that it is corresponding that reproducible nonvolatile memorizer module 406 executes The operation such as be written, read and erase.In an exemplary embodiment, memory management circuitry 702 can also be assigned other kinds of Instruction sequence indicates to execute corresponding operation to reproducible nonvolatile memorizer module 406.

Host interface 704 is electrically connected to memory management circuitry 702 and to receive and identification host system 11 The instruction and data transmitted.That is, the instruction that host system 11 is transmitted can be passed with data by host interface 704 It send to memory management circuitry 702.In this exemplary embodiment, host interface 704 is to be compatible to SATA standard.However, it is necessary to It is appreciated that the invention is not limited thereto, host interface 704 is also possible to be compatible to PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS mark Standard, CF standard, IDE standard or other suitable data transmission standards.

Memory interface 706 is electrically connected to memory management circuitry 702 and non-volatile to access duplicative Property memory module 406.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 406 can be via depositing Memory interface 706 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.Specifically, if storage Device management circuit 702 will access reproducible nonvolatile memorizer module 406, and memory interface 706 can transmit corresponding finger Enable sequence.For example, the reading that these instruction sequences may include the write instruction sequence of instruction write-in data, instruction reading data refers to Enable sequence, instruction erase data erase instruction sequence and to indicate various storage operations (for example, change read electricity Press level or execute garbage reclamation program etc.) corresponding instruction sequence.These instruction sequences are, for example, by memory pipe Reason circuit 702 generates and is sent to reproducible nonvolatile memorizer module 406 by memory interface 706.These refer to Enabling sequence may include one or more signals, or the data in bus.These signals or data may include instruction code or program Code.For example, will include the information such as identification code, the storage address of reading in reading instruction sequence.

Error checking and correcting circuit 708 are electrically connected to memory management circuitry 702 and to execute wrong inspection It looks into and correction program is to ensure the correctness of data.Specifically, when memory management circuitry 702 is received from host system 11 When to write instruction, error checking can be the corresponding error correction of data generation of this corresponding write instruction with correcting circuit 708 Code (error correcting code, ECC) and/or error checking code (error detecting code, EDC), and deposit Reservoir manages circuit 702 and the data of this corresponding write instruction can be written with corresponding error correcting code and/or error checking code Into reproducible nonvolatile memorizer module 406.Later, when memory management circuitry 702 is non-volatile from duplicative The corresponding error correcting code of this data and/or error checking code can be read simultaneously when reading data in memory module 406, and Error checking and correcting circuit 708 can execute mistake to read data according to this error correcting code and/or error checking code Inspection and correction program.

In an exemplary embodiment, memorizer control circuit unit 404 further includes buffer storage 710, power management electricity Road 712 and numerical operation engine 714.

Buffer storage 710 is electrically connected to memory management circuitry 702 and is configured to temporarily store from host system 11 data and instruction or the data from reproducible nonvolatile memorizer module 406.Electric power management circuit 712 is electricity Property is connected to memory management circuitry 702 and the power supply to control memorizer memory devices 10.

In this exemplary embodiment, numerical operation engine 714 is, for example, that will use machine learning algorithm (or deep learning Algorithm) neural network (not shown) or other numerical operation algorithms be embodied in the form of hardware memory control electricity In road unit 404.In addition, the manufacturer of memorizer control circuit unit 404 can dispatch from the factory in memorizer control circuit unit 404 Before, the neural network in logarithm computation engine 714 is trained to obtain each layer (layer) inside the neural network The required weight used and offset (bias) in operation.For example, in having planned numerical operation engine 714 After neural network, it is necessary to input a large amount of input data and the marked answer for corresponding to each input data well to numerical value and transport Calculate the neural network in engine 714.And the neural network in numerical operation engine 714 can be according to above-mentioned input data And each layer in neural network of weight and offset is adjusted corresponding to the answer of each input data.

For example, in one embodiment, the input data can be one read from an entity program unit The sum or the corresponding stroke count evidence that bit value is 0 in bit value is 1 in data, this data sum, this data The summation of one syndrome.In addition, the answer of the corresponding input data is, for example, for reading the entity program unit most Good reading voltage.However in other embodiments, the input data be also possible to corresponding to a write instruction logical address, The counting of sector or the instruction kenel of write instruction, and what the answer of the corresponding input data e.g. said write instructed writes Entering data is dsc data or cold data.In another embodiment, the input data is also possible to corresponding to a write instruction Data are written, and it is compressible or incompressible that the answer of the corresponding input data, which can be the write-in data,.

After adjusting above-mentioned each layer of weight and offset reaches a certain level, if wherein by above-mentioned input data One of neural network in (referred to here as the first input data) input numerical operation engine 714 when, then this neural network Output can answer corresponding to very close first input data.At this point it is possible to the class referred to as in numerical operation engine 714 Neural network has learnt to complete, or has restrained for the neural network in numerical operation engine 714.

It is noted that each layer of weight and offset may be collectively referred to as " operation ginseng in above-mentioned neural network Number ", and before the factory of memorizer control circuit unit 404, it is non-that this operational parameter can be stored in duplicative by manufacturer System area (not shown) in volatile 406.Later, when reproducible nonvolatile memorizer module 406 is rigid When powering on, memory management circuitry 702 can be loaded into via preparatory training from reproducible nonvolatile memorizer module 406 Operational parameter (also referred to as, predefined weight and offset) obtained from (or study) is into numerical operation engine 714 to hold Running needed for line number value computation engine 714.

In addition, error checking and correcting circuit 708 can be directed to and be stored in the same entity journey in this exemplary embodiment Data in sequence unit carry out single frame (single-frame) coding, can also be directed to and be stored in multiple entity program lists Data in member carry out more frame (multi-frame) codings.Single frame coding can be respectively adopted low close with more frame codes Spend odd-even check correcting code (low density parity code, LDPC), BCH code, convolution code (convolutional Code) or the coding algorithm such as turbine code (turbo code) at least one.Alternatively, in an exemplary embodiment, it is more Frame codes can also using Reed Solomon code (Reed-solomon codes, RS codes) algorithm or mutual exclusion or (XOR) algorithm.In addition, the coding algorithm not being listed in more can also be used, herein in another exemplary embodiment Just it does not repeat.According to used coding algorithm, error checking can encode the data to be protected with correcting circuit 708 to produce Raw corresponding error correcting code and/or error checking code.For convenience of description, the error correction that will be generated below via coding Code and/or error checking code are referred to as coded data.

Figure 12 is the schematic diagram of more frame codes shown in an exemplary embodiment according to the present invention.

Figure 12 is please referred to, it is corresponding to generate with the data stored by coding entity programmed cell 810 (0)~810 (E) Coded data 820 for, at least partly data stored by each of entity program unit 810 (0)~810 (E) It can be considered a frame.It in more frame codes, is come for foundation to entity with the position where each bit (or, byte) Data in programmed cell 810 (0)~810 (E) are encoded.For example, being located at the bit b of position 801 (1)₁₁、b₂₁、…、 b_p1The bit b that can be encoded as in coded data 820_o1, it is located at the bit b of position 801 (2)₁₂、b₂₂、…、b_p2It can be encoded as Bit b in coded data 820_o2；And so on, it is located at the bit b of position 801 (r)_1r、b_2r、…、b_prIt can be encoded as encoding Bit b in data 820_or.It thereafter, can be to from entity program unit 810 (0)~810 (E) according to coded data 820 The data of reading are decoded, to attempt to correct mistake that may be present in read data.

In addition, the data for generating coded data 820 may also include entity in another exemplary embodiment of Figure 12 Redundant bit corresponding to data bit (data bits) in data stored by programmed cell 810 (0)~810 (E) (redundancy bits).With the data instance stored by entity program unit 810 (0), redundant bit therein is, for example, The coded data that single frame coding is carried out to the data bit being stored in entity program unit 810 (0) and is generated.In this model In example embodiment, it is assumed that when reading the data in entity program unit 810 (0), from entity program unit 810 (0) The data read out can first (be produced using the redundant bit in entity program unit 810 (0) for example, being encoded using single frame Raw coded data) it decodes to carry out error detection and corrigendum to the data that are read out.However, when using entity program Redundant bit in unit 810 (0) is decoded generation failure (for example, being stored up in entity program unit 810 (0) after decoding The number of error bits for the data deposited is greater than a threshold value) when, it can be used and re-read (Retry-Read) mechanism to select simultaneously Voltage trial is read using others, and correct data are read out from entity program unit 810 (0).And weight can not be passed through by working as When new reading (Retry-Read) mechanism reads out correct data from entity program unit 810 (0), coding can be read The data of data 820 and entity program unit 810 (1)~810 (E), and according to coded data 820 and entity program The data of unit 810 (1)~810 (E) are decoded, to attempt data stored in corrigendum entity program unit 810 (0) Present in mistake.That is, in this exemplary embodiment, when the coded data generated using single frame coding is decoded Occur failure and when use re-reads (Retry-Read) mechanism and be read out generation failure, the productions of more frame codes can be used instead Raw coded data is decoded.

In this exemplary embodiment, memory management circuitry 702 can match for reproducible nonvolatile memorizer module 406 Set a default reading voltage group.For example, being 8 rank memory cell nand type memories in non-the waving property memory module 406 of duplicative It include the multiple voltages of reading voltage VA~VG in such as Fig. 9 in the example of module, in default reading voltage group.Also, right When being read out in reproducible nonvolatile memorizer module 406, memory management circuitry 702 can first use this preset reading The reading voltage in voltage group is taken to read the data being stored in reproducible nonvolatile memorizer module 406.

For example, Figure 13 is multiple entity program unit groups in the entity erased cell according to shown in this exemplary embodiment Example schematic.

Figure 13 is please referred to, when being intended to read data stored in an entity program unit, memory management circuitry 702 Data can be read using default reading voltage group (for example, reading voltage VA~VG in Fig. 9) first.

For example, if memory management circuitry 702 is intended to the lower entity program list from entity program unit group 1301 When first L_0 (also referred to as, first instance programmed cell) reads data, memory management circuitry 702 can be read first using default The reading voltage VA (also referred to as, the first reading voltage) in voltage group is taken to read out number from lower entity program unit L_0 According to (hereinafter referred to as the first data).For example, memory management circuitry 702 can be using the default reading voltage VA read in voltage group To identify the value of each bit in this entity program unit.

After the reading for completing data, memory management circuitry 702 can be used directly another reading voltage and be read again (Retry-Read) mechanism is taken to read data from lower entity program unit L_0.

However in another exemplary embodiment, it can also be read with correcting circuit 708 according to corresponding first with error checking The first data error checking and correcting code (that is, redundant bit) Lai Jinhang error checking and correction program.Wherein, redundancy ratio Special (also referred to as, first coding data) is produced by being encoded by single frame.In error checking and correction program, memory pipe Reason circuit 702 can execute the decoding operate (also referred to as, the first decoding operate) corresponding to single frame coding according to the first coding Mistake in above-mentioned first data of data correcting.Assuming that first coding data can not correct the error bit in the first data completely When, memory management circuitry 702 judges the data that can not correctly obtain in lower entity program unit L_0.At this point, memory Management circuit 702, which just will use, re-reads (Retry-Read) mechanism, reads number from lower entity program unit L_0 again According to.

For example, Figure 14 is shown in an exemplary embodiment according to the present invention for re-reading the reading voltage group of mechanism Schematic diagram.

Referring to Figure 13 and Figure 14, in this exemplary embodiment, memory management circuitry 702 can be pre-configured with (or Setting) for re-reading the reading voltage group RR_1 to reading voltage group RR_n of mechanism.Voltage group RR_1 is read to reading electricity Each of pressure group RR_n, which reads voltage group, will include multiple reading voltages.For example, reading voltage group RR_1 may include using In read lower entity program unit readings voltage VA_1, for entity program unit in reading reading voltage VB_1 and Read voltage VC_1 and reading voltage VD_1, reading voltage VE_1, reading voltage for reading upper entity program unit VF_1 and reading voltage VG_1.Reading voltage group RR_2 may include the reading voltage for reading lower entity program unit VA_2, for entity program unit in reading reading voltage VB_2 and read voltage VC_2 and for reading upper entity journey The reading voltage VD_2 of sequence unit, voltage VE_2 is read, voltage VF_2 is read and reads voltage VG_2.Read voltage group RR_3 It may include for reading the reading voltage VA_3 of lower entity program unit, for the reading of entity program unit in reading Reading voltage VD_3, reading voltage VE_ of the voltage VB_3 with voltage VC_3 is read and for reading upper entity program unit 3, it reads voltage VF_3 and reads voltage VG_3.Reading voltage group RR_n may include for reading lower entity program unit Read voltage VA_n, for the reading voltage VB_n and reading voltage VC_n of entity program unit in reading and for reading The reading voltage VD_n of upper entity program unit, voltage VE_n is read, voltage VF_n is read and reads voltage VG_n.It must explanation , in other embodiments, it is more or less a for weight that memory management circuitry 702 can also be pre-configured with (or setting) The reading voltage group of new reading mechanism.

In re-reading (Retry-Read) mechanism, memory management circuitry 702 can be from above-mentioned reading voltage group RR_ 1 to read voltage group RR_n in sequentially selection read voltage group, and according to it is selected reading voltage group in voltage again from Data are read in lower entity program unit L_0.For example, memory management circuitry 702 can first select reading voltage group RR_1 to come Execute re-reading for first time.Memory management circuitry 702 can be according to the reading voltage VA_1 (also referred to as, second in RR_1 Read voltage) read lower entity program unit L_0 to obtain a data (also referred to as, the second data).Herein notably It is, when reading the same entity program unit (for example, lower entity program unit L_0) using different reading voltage When, the number of error bits (or probability of mistake generation) of acquired data may not be identical.

In one embodiment, reading voltage VA_1 is stated in use reads out the second number from lower entity program unit L_0 According to rear, memory management circuitry 702 can be selected by numerical operation engine 714 for reading lower entity program unit The best reading voltage of L_0 (also referred to as, third reads voltage).Specifically, memory management circuitry 702 can will be in correspondence One second state parameter of a first state parameter and corresponding above-mentioned second data for stating the first data is input to numerical operation Engine 714.Later, numerical operation engine 714 can be according to above-mentioned first state parameter, the second above-mentioned state parameter and elder generation Before be loaded into predefined weight and offset in numerical operation engine 714, such as from reading in voltage group RR_1~RR_n Determine the best reading voltage for reading lower entity program unit L_0.It is assumed herein that numerical operation engine 714 can root The optimal reading for reading lower entity program unit L_0 is reasoned out according to above-mentioned first state parameter and the second state parameter Voltage is the reading voltage VA_n for reading voltage group RR_n.

Herein it should be noted that, first state parameter may include the first data, in the first data bit value be 1 it is total (also referred to as, first school syndrome (syndrome) of bit value is 0 in number, the first data sum or corresponding first data Test son) summation.Wherein, the first syndrome is, for example, and makes during low-density parity checks that correcting code (LDPC) is decoded Multiple syndromes caused by the first read out data are multiplied by with a parity check matrix.Due to the calculation of syndrome It can be learnt by the prior art, herein and be repeated no more.

Similarly, the second state parameter includes the second data, the sum that bit value is 1 in the second data, the second data The summation of the syndrome (also referred to as, the second syndrome) of sum or corresponding second data that middle bit value is 0.Wherein, second Syndrome is, for example, to be multiplied by institute using a parity check matrix during low-density parity checks that correcting code (LDPC) is decoded Multiple syndromes caused by the second data read out.Since the calculation of syndrome can be learnt by the prior art, Herein and repeat no more.

It is noted that first state parameter is identical as the type of the second state parameter in this exemplary embodiment.More For body, when first state parameter is the first above-mentioned data, the second state parameter is the second above-mentioned data；When the first shape State parameter be in the first data bit value be 1 sum when, the second state parameter be in the second data bit value be 1 it is total Number；When first state parameter is the sum that bit value is 0 in the first data, the second state parameter is bit in the second data The sum that numerical value is 0；When first state parameter is the summation of the syndrome of corresponding first data, the second state parameter is corresponding The summation of the syndrome of second data.However the invention is not limited thereto, and in other embodiments, first state parameter and the second shape The type of state parameter can also be different.

However, can also be read with correcting circuit 708 according to corresponding first with error checking in another exemplary embodiment The second data error checking and correcting code (that is, redundant bit, hereon referred to as the second coded data) Lai Jinhang error checking With correction program.Wherein, this first coding data is produced by being encoded by single frame.In error checking and correction program, Memory management circuitry 702 can execute the decoding operate (also referred to as, the first decoding operate) corresponding to single frame coding with basis Second coded data corrects the mistake in above-mentioned second data.Assuming that memory management circuitry 702 execute the first decoding operate but When can not correct completely the error bit in above-mentioned second data according to the second coded data, memory management circuitry 702 just can It executes above-mentioned the second state parameter by the first state parameter of corresponding first data and corresponding second data and is input to numerical value Computation engine 714 is to reason out the running of the best reading voltage for reading lower entity program unit L_0.

In other words, in one embodiment, above-mentioned first is obtained using voltage VA is read when memory management circuitry 702 Data and using reading after voltage VA_1 obtains the second above-mentioned data, memory management circuitry 702 will be i.e. executable to be corresponded to Second state parameter of the first state parameter of the first data and corresponding second data is input to numerical operation engine 714 to push away By the running gone out for reading the best reading voltage of lower entity program unit L_0.And in another embodiment, when the first number When there is accordingly and all the mistake that can not be corrected in the second data, memory management circuitry 702 can just be executed corresponding first number According to first state parameter and the second state parameter of corresponding second data be input to numerical operation engine 714 to reason out use In the running for the best reading voltage for reading lower entity program unit L_0.

It is noted that in the foregoing embodiments, the first reading voltage be in predeterminated voltage group reading voltage (that is, Read voltage VA) and the second reading voltage be the reading voltage (that is, read voltage VA_1) read in voltage group RR_1.However this Invent it is without being limited thereto, in another embodiment, first reading voltage is also possible to read voltage group RR_1~RR_N in a reading It takes voltage (for example, reading voltage VA_1) and the second reading voltage can be another reading read in voltage group RR_1~RR_N Voltage (for example, reading voltage VA_2).The present invention is not used to limit the first source for reading voltage and the second reading voltage.

That is, re-read in (Retry-Read) mechanism in traditional, memory management circuitry 702 may need to be according to Sequence is attempted to obtain last for entity journey under reading using all reading voltage group RR_1 to voltage group RR_n is read The best reading voltage (that is, the reading voltage VA_n for reading voltage group RR_n) of sequence unit L_0.However, through the invention Numerical operation engine 714 can allow memory management circuitry 702 being not required to attempt all reading voltage group RR_1 to reading electricity Under pressure group RR_n, the best reading voltage for reading lower entity program unit L_0 is rapidly obtained.It is noted that this Invention is not used to limit the number re-read, in other embodiments, is also possible to work as execution (or less time) more times Re-read, first state parameter and the second state parameter (or other more state parameters) are just input to numerical operation Engine 714 carries out inference to obtain best reading voltage.

When numerical operation engine 714 is obtaining the best reading voltage (example for entity program unit L_0 under reading Such as, voltage VA_n is read) after, numerical operation engine 714, which can export, reads voltage VA_n to memory management circuitry 702.It Afterwards, memory management circuitry 702 can be used memory management circuitry 702 and read lower entity program unit L_0 to obtain one Data (also referred to as, third data).

Later, error checking and correcting circuit 708 can error checking according to corresponding read out third data and schools Code (that is, redundant bit, hereon referred to as third coded data) Lai Jinhang error checking and correction program.Wherein, this third is compiled Code data are produced by being encoded by single frame.In error checking and correction program, memory management circuitry 702 can be executed pair It should be in the decoding operate (also referred to as, the first decoding operate) that single frame encodes to correct above-mentioned third number according to third coded data Mistake in.

When memory management circuitry 702 checks third data according to third coded data and judges to be not present in third data When mistake, memory management circuitry 702 can export read third data to host system 11.In addition, working as memory pipe When the mistake in third data can be corrected according to third coded data by managing circuit 702, memory management circuitry 702 can also be defeated The third data righted the wrong out are to host system 11.However, third coded data can not be passed through when existing in third data When the mistake of corrigendum, memory management circuitry 702 judges the entity program unit L_0 in the case where reading using the first decoding operate During fail.In other words, judge can not be by re-reading (Retry-Read) for memory management circuitry 702 When mechanism reads out correct data from lower entity program unit L_0.Memory management circuitry 702 is judged using single frame The coded data that frame coding generates, which is decoded, to fail.Later, memory management circuitry 702 can use more frame codes instead and produce Raw coded data is decoded.

It can be seen from the above content that the present invention from reproducible nonvolatile memorizer module 406 read data when, Numerical operation engine 714 can be used to judge at least one best reading voltage for reading an entity program unit, whereby The time it takes in re-reading (Retry-Read) mechanism is reduced, and promotes reproducible nonvolatile memorizer module 406 access efficiency.

It is noted that although above-mentioned exemplary embodiment is to be reasoned out with numerical operation engine 714 for reading The best reading voltage of entity program unit, however the invention is not limited thereto.In other embodiments, numerical operation engine 714 can be used for reasoning out the best reading electricity for reading entity program unit on entity program unit or one in one Pressure.Although in addition, above-mentioned exemplary embodiment be by taking TLC NAND type flash memory module as an example, the present invention is not limited to This.In other embodiments, data access method of the invention also can be applied to SLC NAND type flash memory module or In MLC NAND type flash memory module.

In particular, in one embodiment, numerical operation engine 714 can also be used in host system 11 assign write instruction to The case where memory management circuitry 702.Specifically, when memory management circuitry 702 receives a write-in from host system 11 When instructing (also referred to as, the first write instruction), memory management circuitry 702 can be by a state of this corresponding the first write instruction Parameter (also referred to as, third state parameter) is input in numerical operation engine 714.Later, numerical operation engine 714 can basis This third state parameter determines the type of the write-in data (also referred to as, the first write-in data) of corresponding above-mentioned first write instruction.

Specifically, in one embodiment, third state parameter includes patrolling for being written the one of above-mentioned first write-in data Collect the instruction kenel of address (also referred to as, the first logical address), physical address, the counting of sector or the first write instruction.Numerical value Computation engine 714 can be judged according to above-mentioned one of third state parameter above-mentioned first write-in data for dsc data or Cold data.The frequency that wherein dsc data is accessed can be higher than the frequency that cold data is accessed.In one embodiment, memory management Circuit 702 can for example will be identified that the data storage of dsc data in the memory control electricity that relatively often (or more strong) is accessed The data storage for temporarily this not being identified as dsc data in the buffer storage 710 of road unit 404 is non-to duplicative In volatile 406.However in another embodiment, memory management circuitry 702 can for example use a single page journey The data that this is identified as dsc data are written to reproducible nonvolatile memorizer module 406 sequence mode.Wherein, may be used One can be only stored by the memory cell for using single page sequencing mode to be written in manifolding formula non-volatile memory module 406 The data of bit.In addition, memory management circuitry 702 can for example will be identified that the data of cold data directly (or immediately) Storage is deleted the pen kept in buffer storage 710 and is known into reproducible nonvolatile memorizer module 406 Not Wei cold data data.In one embodiment, memory management circuitry 702 for example can directly use a multipage sequencing mould The data that this is identified as cold data are written into reproducible nonvolatile memorizer module 406 formula, and more by using The memory cell that page sequencing mode is written can store the data of multiple bits.

In addition, in one embodiment, third state parameter also may include the first above-mentioned write-in data.Numerical operation draws Holding up 714 can judge this first write-in data to be compressible or incompressible according to the first write-in data.It is noted that Judge whether a data are compressible or incompressible can learn that details are not described herein by existing mode.And work as Numerical operation engine 714 judge first write-in data for it is compressible when, numerical operation engine 714 may determine that the first write-in number According to compression ratio, and export this compression ratio to memory management circuitry 702.Later, memory management circuitry 702 can be according to number The compression ratio that value computation engine 714 exports compresses the first write-in data.

Figure 15 is the flow chart of the data access method according to shown in an exemplary embodiment.

Figure 15 is please referred to, in step S1501, memory management circuitry 702 is read using first in multiple reading voltages Voltage is taken to read the first instance programmed cell in multiple entity program units to obtain the first data.In step S1503 In, memory management circuitry 702 using it is multiple reading voltages in second read voltages read first instance programmed cells with Obtain the second data.In step S1505, memory management circuitry 702 by the first state parameter of corresponding first data and Second state parameter of corresponding second data is input to numerical operation engine 714.Then, in step S1507, numerical operation draws 714 are held up to be determined in the multiple reading voltage according to first state parameter and the second state parameter for reading first instance journey The best reading voltage of sequence unit.Finally in step S1509, memory management circuitry 702 uses the best reading electricity Pressure reads first instance programmed cell to obtain third data.

In conclusion data access method of the invention can read from reproducible nonvolatile memorizer module When data, by the judgement of numerical operation engine for reading the best reading voltage of an entity program unit, reduce whereby The time it takes in (Retry-Read) mechanism is re-read, and promotes the access of reproducible nonvolatile memorizer module Efficiency.In addition, can also be judged by numerical operation engine when reproducible nonvolatile memorizer module is written Whether write-in data are cold data or dsc data, can also judge to be written whether data can be compressed by numerical operation engine, Memory management circuitry can be made to can choose optimal mode when executing the write-in of data whereby to be written.

Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention Range is subject to view the attached claims institute defender.

Claims (30)

1. a kind of data access method is used for reproducible nonvolatile memorizer module, the duplicative is non-volatile to be deposited Memory modules have multiple entity erased cells, the multiple entity erased cell each of entity erased cell have Multiple entity program units, the data access method include:

First in the multiple entity program unit is read using at least one first reading voltage in multiple reading voltages Entity program unit is to obtain the first data；

Voltage, which is read, using at least one second in the multiple reading voltage reads the first instance programmed cell to take Obtain the second data；

Second state parameter of the first state parameter of correspondence first data and corresponding second data is input to Numerical operation engine；

According to the first state parameter and second state parameter, determined by the numerical operation engine the multiple It reads in voltage and reads voltage for reading the third of the first instance programmed cell；And

Voltage, which is read, using the third reads the first instance programmed cell to obtain third data.

2. data access method according to claim 1, wherein being read using described first in the multiple reading voltage Voltage is taken to read the first instance programmed cell in the multiple entity program unit to obtain first data The step of include:

The first decoding operate is executed to correct the mistake in first data according to first coding data, and works as described first When there is the mistake that can not be corrected in data, executes and read institute using the second reading voltage in the multiple reading voltage The step of first instance programmed cell is to obtain second data is stated,

Wherein using described second in the multiple reading voltage read voltage read the first instance programmed cell with The step of obtaining second data include:

First decoding operate is executed to correct the mistake in second data according to the second coded data, and when described When there is the mistake that can not be corrected in the second data, execute the first state parameter of correspondence first data and right The step of answering second state parameter of second data to be input to the numerical operation engine.

3. data access method according to claim 1, wherein it is to read the first instance that the third, which reads voltage, The best reading voltage of programmed cell.

4. data access method according to claim 2, further includes:

First decoding operate is executed to correct the mistake in the third data according to third coded data；

When mistake is not present in the third data, the third data are exported；

When the mistake in the third data is corrected, the third data righted the wrong are exported；And

When there is the mistake that can not be corrected in the third data, judge using first decoding operate reading described the Fail during one entity program unit.

5. data access method according to claim 1, wherein the first state parameter includes first data, institute State the sum or corresponding first number that bit value is 0 in total, described first data that bit value in the first data is 1 According to the first syndrome summation.

6. data access method according to claim 1, wherein second state parameter includes second data, institute State the sum or corresponding second number that bit value is 0 in total, described second data that bit value in the second data is 1 According to the second syndrome summation.

7. data access method according to claim 1, further includes:

When the reproducible nonvolatile memorizer module just powers on, from the reproducible nonvolatile memorizer module It is loaded into via an at least operational parameter obtained from preparatory training into the numerical operation engine.

8. data access method according to claim 7, wherein the operational parameter includes predefined weight or offset Amount, wherein according to the first state parameter and second state parameter, by described in numerical operation engine decision Include: for reading the step of third of the first instance programmed cell reads voltage in multiple reading voltages

By the numerical operation engine according to the first state parameter, second state parameter and described predefined Weight or the offset determine that the third reads voltage.

9. data access method according to claim 1, further includes:

The first write instruction is received from host system；

The third state parameter of correspondence first write instruction is input in the numerical operation engine；And

Determine that the first of corresponding first write instruction writes according to the third state parameter by the numerical operation engine Enter the type of data.

10. data access method according to claim 9, wherein the third state parameter includes corresponding to described first The first logical address of data, location parameter or instruction kenel is written, wherein by the numerical operation engine according to described the Three condition parameter determines that the step of type of the first write-in data of corresponding first write instruction includes:

Judge the first write-in data for dsc data or cold according to the third state parameter by the numerical operation engine Data, wherein the frequency that the dsc data is accessed is higher than the frequency that the cold data is accessed.

11. a kind of memorizer control circuit unit, is used for reproducible nonvolatile memorizer module, the duplicative is non-easily The property lost memory module has multiple entity erased cells, the multiple entity erased cell each of entity erase list Member has multiple entity program units, and the memorizer control circuit unit includes:

Host interface is electrically connected to host system；

Memory interface is electrically connected to the reproducible nonvolatile memorizer module；

Numerical operation engine；And

Memory management circuitry is electrically connected to the host interface, the memory interface and the numerical operation engine,

Wherein the memory management circuitry is to use at least one first in multiple reading voltages to read described in voltage reading First instance programmed cell in multiple entity program units to obtain the first data,

Wherein the memory management circuitry is also to use at least one second in the multiple reading voltage to read voltage reading Take the first instance programmed cell to obtain the second data,

Wherein the memory management circuitry also to the first state parameter that will correspond to first data and it is corresponding described in Second state parameter of the second data is input to the numerical operation engine,

The numerical operation engine is the multiple to be determined according to the first state parameter and second state parameter It reads in voltage and reads voltage for reading the third of the first instance programmed cell,

Wherein the memory management circuitry also reads the first instance sequencing list to use the third to read voltage Member is to obtain third data.

12. memorizer control circuit unit according to claim 11, wherein using in the multiple reading voltage The first reading voltage reads the first instance programmed cell in the multiple entity program unit to obtain In the running for stating the first data,

The memory management circuitry executes the first decoding operate to correct in first data according to first coding data Mistake, and when there is the mistake that can not be corrected in first data, execute using the institute in the multiple reading voltage It states the second reading voltage and reads the first instance programmed cell to obtain the running of second data,

Wherein the voltage reading first instance programmed cell is being read using described second in the multiple reading voltage In running to obtain second data,

The memory management circuitry executes first decoding operate to correct second data according to the second coded data In mistake, and when there is the mistake that can not be corrected in second data, execute the institute of correspondence first data Second state parameter for stating first state parameter and corresponding second data is input to the numerical operation engine Running.

13. memorizer control circuit unit according to claim 11, wherein it is described in reading that the third, which reads voltage, The best reading voltage of first instance programmed cell.

14. memorizer control circuit unit according to claim 12, wherein

The memory management circuitry executes first decoding operate to correct the third data according to third coded data In mistake,

When mistake is not present in the third data, the memory management circuitry exports the third data,

When the mistake in the third data is corrected, the memory management circuitry exports the third righted the wrong Data, and

When there is the mistake that can not be corrected in the third data, the memory management circuitry judges using described first Decoding operate fails during reading the first instance programmed cell.

15. memorizer control circuit unit according to claim 11, wherein the first state parameter includes described The sum or correspondence that bit value is 0 in total, described first data that bit value is 1 in one data, first data The summation of first syndrome of first data.

16. memorizer control circuit unit according to claim 11, wherein second state parameter includes described The sum or correspondence that bit value is 0 in total, described second data that bit value is 1 in two data, second data The summation of second syndrome of second data.

17. memorizer control circuit unit according to claim 11, wherein

When the reproducible nonvolatile memorizer module just powers on, the memory management circuitry is from the duplicative Non-volatile memory module is loaded into via an at least operational parameter obtained from preparatory training into the numerical operation engine.

18. memorizer control circuit unit according to claim 17, wherein the operational parameter includes predefined power Weight or offset, wherein the numerical operation engine determines according to the first state parameter and second state parameter It is read in the running of voltage in the multiple reading voltage for reading the third of the first instance programmed cell,

The numerical operation engine is according to the first state parameter, second state parameter and the predefined weight Or the offset determines that the third reads voltage.

19. memorizer control circuit unit according to claim 11, wherein

The memory management circuitry receives the first write instruction from the host system,

The third state parameter of correspondence first write instruction is input to the numerical operation by the memory management circuitry In engine, and

The numerical operation engine determines the first write-in number of corresponding first write instruction according to the third state parameter According to type.

20. memorizer control circuit unit according to claim 19, wherein the third state parameter includes corresponding to First write-in, first logical address of data, location parameter or instruction kenel, wherein the numerical operation engine according to The third state parameter determines to correspond in the running of the type of the first write-in data of first write instruction,

The numerical operation engine according to the third state parameter judge it is described first write-in data for dsc data or cold data, The frequency that wherein dsc data is accessed is higher than the frequency that the cold data is accessed.

21. a kind of memorizer memory devices, comprising:

Connecting interface unit, is electrically connected to host system；

Reproducible nonvolatile memorizer module has multiple entity erased cells, among the multiple entity erased cell Each entity erased cell have multiple entity program units；And

Memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile Module and have numerical operation engine,

Wherein the memorizer control circuit unit is read to use at least one first in multiple reading voltages to read voltage First instance programmed cell in the multiple entity program unit to obtain the first data,

Wherein the memorizer control circuit unit is also to use at least one second in the multiple reading voltage to read electricity Press the reading first instance programmed cell to obtain the second data,

Wherein first state parameter and correspondence of the memorizer control circuit unit also first data will be corresponded to Second state parameter of second data is input to the numerical operation engine, and by the numerical operation engine according to institute It states first state parameter and second state parameter determines in the multiple reading voltage for reading the first instance The third of programmed cell reads voltage,

Wherein the memorizer control circuit unit also reads the first instance program to use the third to read voltage Change unit to obtain third data.

22. memorizer memory devices according to claim 21, wherein described in using the multiple reading voltage First reading voltage reads the first instance programmed cell in the multiple entity program unit to obtain described the In the running of one data,

The memorizer control circuit unit executes the first decoding operate to correct first data according to first coding data In mistake, and when there is the mistake that can not be corrected in first data, execute using in the multiple reading voltage The second reading voltage read the first instance programmed cell to obtain the running of second data,

Wherein the voltage reading first instance programmed cell is being read using described second in the multiple reading voltage In running to obtain second data,

The memorizer control circuit unit executes first decoding operate according to the second coded data corrigendum described second Mistake in data, and when there is the mistake that can not be corrected in second data, executing will corresponding first data The first state parameter and second state parameters of corresponding second data be input to the numerical operation and draw The running held up.

23. memorizer memory devices according to claim 21, wherein it is to read described first that the third, which reads voltage, The best reading voltage of entity program unit.

24. memorizer memory devices according to claim 22, wherein

The memorizer control circuit unit executes first decoding operate to correct the third according to third coded data Mistake in data,

When mistake is not present in the third data, the memorizer control circuit unit exports the third data,

When the mistake in the third data is corrected, the memorizer control circuit unit output has been righted the wrong described Third data, and

When there is the mistake that can not be corrected in the third data, the memorizer control circuit unit judges are described in the use First decoding operate fails during reading the first instance programmed cell.

25. memorizer memory devices according to claim 21, wherein the first state parameter includes first number Bit value is 0 in total, described first data for being 1 according to bit value in, first data sum or it is corresponding described in The summation of first syndrome of the first data.

26. memorizer memory devices according to claim 21, wherein second state parameter includes second number Bit value is 0 in total, described second data for being 1 according to bit value in, second data sum or it is corresponding described in The summation of second syndrome of the second data.

27. memorizer memory devices according to claim 21, wherein

When the reproducible nonvolatile memorizer module just powers on, the memorizer control circuit unit is answered from described It writes formula non-volatile memory module and is loaded into and draw via an at least operational parameter to the numerical operation obtained from preparatory training In holding up.

28. memorizer memory devices according to claim 27, wherein the operational parameter include predefined weight or Offset, wherein the numerical operation engine is described more according to the first state parameter and second state parameter decision It is read in the running of voltage in a reading voltage for reading the third of the first instance programmed cell,

The numerical operation engine is according to the first state parameter, second state parameter and the predefined weight Or the offset determines that the third reads voltage.

29. memorizer memory devices according to claim 21, wherein

The memorizer control circuit unit receives the first write instruction from the host system,

The third state parameter of correspondence first write instruction is input to the numerical value by the memorizer control circuit unit In computation engine, and determine that corresponding first write-in refers to according to the third state parameter by the numerical operation engine The type of the first write-in data enabled.

30. memorizer memory devices according to claim 29, wherein the third state parameter includes corresponding to described First write-in the first logical address of data, location parameter or instruction kenel, wherein by the numerical operation engine according to The third state parameter determines to correspond in the running of the type of the first write-in data of first write instruction,

The memorizer memory devices judge that described first writes according to the third state parameter by the numerical operation engine Entering data is dsc data or cold data, wherein the frequency that the dsc data is accessed is higher than the frequency that the cold data is accessed.