CN106297883A - Coding/decoding method, memory storage apparatus and memorizer control circuit unit - Google Patents

Coding/decoding method, memory storage apparatus and memorizer control circuit unit Download PDF

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Publication number
CN106297883A
CN106297883A CN201510304308.XA CN201510304308A CN106297883A CN 106297883 A CN106297883 A CN 106297883A CN 201510304308 A CN201510304308 A CN 201510304308A CN 106297883 A CN106297883 A CN 106297883A
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Prior art keywords
soft decision
voltage level
read voltage
memory element
state
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CN201510304308.XA
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CN106297883B (en
Inventor
林纬
王天庆
赖国欣
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

The present invention provides a kind of coding/decoding method, memory storage apparatus and memorizer control circuit unit.Described method includes: read multiple first memory element to obtain the first soft decision coding unit belonging to block code according to the first soft decision read voltage level；Described first soft decision coding unit is performed the first soft decision decoding program；If described first soft decision decoding program failure, reading described first memory element according to the second soft decision read voltage level and belong to the second soft decision coding unit of block code with acquisition, the difference between described first soft decision read voltage level with described second soft decision read voltage level is relevant with the extent of deterioration of described first memory element；And described second soft decision coding unit is performed the second soft decision decoding program.Whereby, the decoding efficiency for block code can be improved.

Description

Coding/decoding method, memory storage apparatus and memorizer control circuit unit
Technical field
The invention relates to a kind of decoding technique, and in particular to a kind of coding/decoding method, memorizer Storage device and memorizer control circuit unit.
Background technology
Digital camera, mobile phone and MP3 player are the rapidest in growth over the years so that disappear The demand of storage media is increased by expense person the most rapidly.Due to reproducible nonvolatile memorizer module (example Such as, flash memory) to have data non-volatile, power saving, volume little, and the spy such as mechanical structure Property, so being especially suitable for being built in above-mentioned illustrated various portable multimedia devices.
In general, in order to ensure the correctness of data, by non-to duplicative for the write of a certain pen data Before volatile, these data can be encoded.And the data after encoding can be written into answering Write in formula non-volatile memory module.When being intended to read this pen data, the data after coding can be read Out and be decoded.If data can be successfully decoded, represent that the number of error bit therein is few And these a little error bits can be corrected.But, if data cannot be successfully decoded (that is, decoding unsuccessfully), Then more read voltage (also referred to as soft decision read voltage) may be used to read and more assists solution Code information (also referred to as Soft Inform ation).According to this auxiliary decoder information, the probability that data are successfully decoded can carry Rise.
In general, multiple soft decision read voltage voltage difference each other is fixing and can pass through Table look-up and obtain.But, for the reproducible nonvolatile memorizer module that usage degree differs, Multiple soft decision read voltage with fixed voltage difference are used to may result in decoding efficiency low.
Summary of the invention
The present invention provides a kind of coding/decoding method, memory storage apparatus and memorizer control circuit unit, can Improve the decoding efficiency for block code.
One example of the present invention embodiment provides a kind of coding/decoding method, and it is used for, and duplicative is non-volatile to be deposited Memory modules, described reproducible nonvolatile memorizer module includes multiple memory element, described decoding Method includes: determine that first is soft according to the extent of deterioration of the first memory element multiple in described memory element Decision-making read voltage level and the second soft decision read voltage level, wherein said first soft decision reads electricity Between voltage level and described second soft decision read voltage level, there is difference；Read with described first soft decision Power taking voltage level reads described first memory element to obtain the first soft decision coding unit, wherein said First soft decision coding unit belongs to block code；Described first soft decision coding unit is performed first soft certainly Plan decoding program；If described first soft decision decoding program failure, with described second soft decision read voltage Level reads described first memory element to obtain the second soft decision coding unit, wherein said second soft Decision-making coding unit belongs to described block code；And it is soft that described second soft decision coding unit is performed second Decision-making decoding program.
In one example of the present invention embodiment, described coding/decoding method also includes: receive read instruction and Described first memory element is read to obtain hard decision coding unit with hard decision read voltage level, its Described in hard decision coding unit belong to described block code；And described hard decision coding unit is performed hard Decision-making decoding program, wherein reads described first storage with described first soft decision read voltage level single The step of unit is to perform after the failure of described hard decision decoding program.
In one example of the present invention embodiment, described coding/decoding method also includes: perform described second soft Before decision-making decoding program, at least one bit in described second soft decision coding unit is set as in institute State the bit value of corrigendum in the first soft decision decoding program.
In one example of the present invention embodiment, come according to the described extent of deterioration of described first memory element Determine the step bag of described first soft decision read voltage level and described second soft decision read voltage level Including: obtain the voltage's distribiuting state of described first memory element, wherein said voltage's distribiuting state is at least wrapped Include the first state and the second state；And according to the gap between described first state and described second state With the overlapping degree of described second state, width or described first state determine that described first soft decision reads Voltage level and described second soft decision read voltage level.
In one example of the present invention embodiment, described first soft decision read voltage level and described second Described difference between soft decision read voltage level is that negative is about described first state and described second shape Described overlapping degree between state.
In one example of the present invention embodiment, described first soft decision read voltage level and described second Described difference between soft decision read voltage level is to be positively correlated with and described first state and described second Described gap width between state.
In one example of the present invention embodiment, described first soft decision read voltage level and described second Described difference between soft decision read voltage level is the negative described damage about described first memory element Consumption degree, wherein determines described first soft decision according to the described extent of deterioration of described first memory element Read voltage level includes with the step of described second soft decision read voltage level: deposit according to described first The reading times of storage unit, write number of times, the wiping of described first memory element of described first memory element Except at least one of a bit error rate of number of times and described first memory element, determine described One soft decision read voltage level and described second soft decision read voltage level.
In one example of the present invention embodiment, described first soft decision read voltage level and described second One of them of soft decision read voltage level is the optimal read voltage corresponding to described first memory element According to the described extent of deterioration of described first memory element, level, wherein determines that described first soft decision is read Power taking voltage level includes with the step of described second soft decision read voltage level: perform optimal read voltage Level tracing program (optimal read voltage level tracking process) is to determine described optimal reading Voltage level.
In one example of the present invention embodiment, described block code is made up of many sub-coding units, described Predetermined bit in sub-coding unit is to be determined by multiple encoding procedures.
In one example of the present invention embodiment, described encoding procedure has different coding directions.
Another example of the present invention embodiment provides a kind of memory storage apparatus, and it includes connecting interface list Unit, reproducible nonvolatile memorizer module and memorizer control circuit unit.Described connection interface list Unit is electrically connected to host computer system.Described reproducible nonvolatile memorizer module includes multiple depositing Storage unit.Described memorizer control circuit unit is electrically connected to described connection interface unit and answers with described Writing formula non-volatile memory module, wherein said memorizer control circuit unit is in order to according to described storage In unit, the extent of deterioration of multiple first memory element determines the first soft decision read voltage level and second Soft decision read voltage level, wherein said first soft decision read voltage level and described second soft decision Having difference between read voltage level, wherein said memorizer control circuit unit is also in order to send first Soft decision reads job sequence, and wherein said first soft decision reads job sequence in order to indicate with described the It is single to obtain the first soft decision coding that one soft decision read voltage level reads described first memory element Unit, wherein said first soft decision coding unit belongs to block code, wherein said memorizer control circuit list Unit also in order to described first soft decision coding unit is performed the first soft decision decoding program, if the most described First soft decision decoding program failure, described memorizer control circuit unit is also in order to send the second soft decision Read job sequence, wherein said second soft decision read job sequence in order to indicate with described second soft certainly Plan read voltage level reads described first memory element to obtain the second soft decision coding unit, wherein Described memorizer control circuit unit is also in order to perform the second soft decision to described second soft decision coding unit Decoding program.
In one example of the present invention embodiment, described memorizer control circuit unit is also in order to receive reading Instructing and send hard decision and read job sequence, wherein said hard decision reads job sequence in order to indicate Described first memory element is read to obtain hard decision coding unit with hard decision read voltage level, its Described in hard decision coding unit belong to described block code, wherein said memorizer control circuit unit is also used So that described hard decision coding unit is performed hard decision decoding program, wherein said memorizer control circuit list It is in described hard decision decoding program failure that unit sends the operation of described first soft decision reading job sequence Rear execution.
In one example of the present invention embodiment, before performing described second soft decision decoding program, institute State memorizer control circuit unit also in order to by ad hoc at least one ratio in described second soft decision coding unit It is set in described first soft decision decoding program the bit value of corrigendum.
In one example of the present invention embodiment, described memorizer control circuit unit is deposited according to described first The described extent of deterioration of storage unit determine described first soft decision read voltage level with described second soft certainly The operation of plan read voltage level includes: obtain the voltage's distribiuting state of described first memory element, wherein Described voltage's distribiuting state includes the first state and the second state；And according to described first state with described Gap width between second state or described first state determine with the overlapping degree of described second state Described first soft decision read voltage level and described second soft decision read voltage level.
In one example of the present invention embodiment, described first soft decision read voltage level and described second Described difference between soft decision read voltage level is that negative is about described first state and described second shape Described overlapping degree between state.
In one example of the present invention embodiment, described first soft decision read voltage level and described second Described difference between soft decision read voltage level is to be positively correlated with and described first state and described second Described gap width between state.
In one example of the present invention embodiment, described first soft decision read voltage level and described second Described difference between soft decision read voltage level is the negative described damage about described first memory element Consumption degree, wherein said memorizer control circuit unit is according to the described loss journey of described first memory element Degree determines the behaviour of described first soft decision read voltage level and described second soft decision read voltage level Work includes: according to the reading times of described first memory element, the write number of times of described first memory element, The erasing times of described first memory element and the bit error rate of described first memory element are at least within One of, determine described first soft decision read voltage level and described second soft decision read voltage level.
In one example of the present invention embodiment, described first soft decision read voltage level and described second One of them of soft decision read voltage level is the optimal read voltage corresponding to described first memory element Level, wherein said memorizer control circuit unit is according to the described extent of deterioration of described first memory element Determine the operation of described first soft decision read voltage level and described second soft decision read voltage level Including: perform optimal read voltage level tracing program to determine described optimal read voltage level.
In one example of the present invention embodiment, described block code is made up of many sub-coding units, described Predetermined bit in sub-coding unit is to be determined by multiple encoding procedures.
In one example of the present invention embodiment, described encoding procedure has different coding directions.
Another example of the present invention embodiment provides a kind of memorizer control circuit unit, and it can for control Manifolding formula non-volatile memory module, wherein said reproducible nonvolatile memorizer module includes many Individual memory element, described memorizer control circuit unit includes that HPI, memory interface, mistake are examined Look into and correcting circuit and memory management circuitry.Described HPI is electrically connected to host computer system. Described memory interface is electrically connected to described reproducible nonvolatile memorizer module.Described deposit Reservoir management circuit be electrically connected to described HPI, described memory interface and described error checking with Correcting circuit, wherein said memory management circuitry is in order to according to the first storages multiple in described memory element The extent of deterioration of unit determines the first soft decision read voltage level and the second soft decision read voltage electricity Flat, between wherein said first soft decision read voltage level and described second soft decision read voltage level There is difference, wherein said memory management circuitry also in order to send first soft decision read job sequence, Wherein said first soft decision reads job sequence in order to indicate with described first soft decision read voltage level Read described first memory element to obtain the first soft decision coding unit, wherein said first soft decision Coding unit belongs to block code, and wherein said error checking and correcting circuit are in order to described first soft decision Coding unit performs the first soft decision decoding program, if the most described first soft decision decoding program failure, Described memory management circuitry also reads job sequence in order to sending the second soft decision, wherein said second soft Decision-making reads job sequence in order to indicate with described second soft decision read voltage level to read described first Memory element is to obtain the second soft decision coding unit, and wherein said second soft decision coding unit belongs to institute Stating block code, wherein said error checking and correcting circuit are also in order to described second soft decision coding unit Perform the second soft decision decoding program.
In one example of the present invention embodiment, described memory management circuitry is also in order to receive reading instruction And sending hard decision and read job sequence, wherein said hard decision reads job sequence in order to indicate with firmly Decision-making read voltage level reads described first memory element to obtain hard decision coding unit, Qi Zhongsuo Stating hard decision coding unit and belong to described block code, wherein said error checking and correcting circuit are also in order to right Described hard decision coding unit performs hard decision decoding program, and wherein said memory management circuitry sends institute The operation stating the first soft decision reading job sequence is to perform after the failure of described hard decision decoding program.
In one example of the present invention embodiment, before performing described second soft decision decoding program, institute State memory management circuitry also in order to be set as by least one bit in described second soft decision coding unit The bit value of corrigendum in described first soft decision decoding program.
In one example of the present invention embodiment, described memory management circuitry is single according to described first storage The described extent of deterioration of unit determines that described first soft decision read voltage level is read with described second soft decision The operation of power taking voltage level includes: obtain the voltage's distribiuting state of described first memory element, wherein said Voltage's distribiuting state includes the first state and the second state；And according to described first state and described second Gap width or described first state between state determine described with the overlapping degree of described second state First soft decision read voltage level and described second soft decision read voltage level.
In one example of the present invention embodiment, described first soft decision read voltage level and described second Described difference between soft decision read voltage level is that negative is about described first state and described second shape Described overlapping degree between state.
In one example of the present invention embodiment, described first soft decision read voltage level and described second Described difference between soft decision read voltage level is to be positively correlated with and described first state and described second Described gap width between state.
In one example of the present invention embodiment, described first soft decision read voltage level and described second Described difference between soft decision read voltage level is the negative described damage about described first memory element Consumption degree, wherein said memory management circuitry is come according to the described extent of deterioration of described first memory element Determine the operation bag of described first soft decision read voltage level and described second soft decision read voltage level Include: according to the reading times of described first memory element, the write number of times of described first memory element, institute State the erasing times of the first memory element and the bit error rate of described first memory element at least within it One, determine described first soft decision read voltage level and described second soft decision read voltage level.
In one example of the present invention embodiment, described first soft decision read voltage level and described second One of them of soft decision read voltage level is the optimal read voltage corresponding to described first memory element Level, wherein said memory management circuitry is come certainly according to the described extent of deterioration of described first memory element Fixed described first soft decision read voltage level and the operation bag of described second soft decision read voltage level Include: perform optimal read voltage level tracing program to determine described optimal read voltage level.
In one example of the present invention embodiment, described block code is made up of many sub-coding units, described Predetermined bit in sub-coding unit is to be determined by multiple encoding procedures.
In one example of the present invention embodiment, described encoding procedure has different coding directions.
Based on above-mentioned, the present invention can be according to having the of the difference relevant with the extent of deterioration of memory element One soft decision read voltage level and the second soft decision read voltage level read respectively and broadly fall into block code The first soft decision coding unit and the second soft decision coding unit, and perform respectively correspondence soft decision Decoding program.Whereby, the decoding efficiency for block code can be improved.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate Accompanying drawing is described in detail below.
Accompanying drawing explanation
Fig. 1 is host computer system shown by one example of the present invention embodiment and the showing of memory storage apparatus It is intended to；
Fig. 2 is that the computer shown by one example of the present invention embodiment, input/output device are deposited with memorizer The schematic diagram of storage device；
Fig. 3 is host computer system shown by one example of the present invention embodiment and the showing of memory storage apparatus It is intended to；
Fig. 4 is the schematic block diagram illustrating the memory storage apparatus shown in Fig. 1；
Fig. 5 is the reproducible nonvolatile memorizer module shown by one example of the present invention embodiment Schematic block diagram；
Fig. 6 is the schematic diagram of the memory cell array shown by one example of the present invention embodiment；
Fig. 7 is the summary square of the memorizer control circuit unit shown by one example of the present invention embodiment Figure；
Fig. 8 is the management type nonvolatile mould shown by one example of the present invention embodiment The schematic diagram of block；
Fig. 9 is the critical voltage distribution of the multiple memory element shown by one example of the present invention embodiment Schematic diagram；
Figure 10 is the schematic diagram of the block code shown by one example of the present invention embodiment；
Figure 11 is that the soft decision read voltage level shown by one example of the present invention embodiment is single with storage The schematic diagram of the critical voltage distribution of unit；
Figure 12 is the flow chart of the coding/decoding method shown by one example of the present invention embodiment.
Description of reference numerals:
10: memory storage apparatus；
11: host computer system；
12: computer；
122: microprocessor；
124: random access memory (RAM)；
126: system bus；
128: data transmission interface；
13: input/output (I/O) device；
21: mouse；
22: keyboard；
23: display；
24: printer；
25: Portable disk；
26: memory card；
27: solid state hard disc；
31: digital camera；
32:SD card；
33:MMC card；
34: memory stick；
35:CF card；
36: embedded storage device；
402: connect interface unit；
404: memorizer control circuit unit；
406: reproducible nonvolatile memorizer module；
502: memory cell array；
504: word-line control circuit；
506: bit line control circuit；
508: row decoder；
510: data input/output buffer；
512: control circuit；
602: memory element；
604: bit line；
606: word-line；
608: common source line；
612,614: transistor；
702: memory management circuitry；
704: HPI；
706: memory interface；
708: error checking and correcting circuit；
710: buffer storage；
712: electric power management circuit；
800 (0)～800 (R): physics erasing unit；
810 (0)～810 (D): logical block；
802: memory block；
806: system area；
901,902,911,912: distribution；
913: overlapping region；
1010: coding unit；
1020 (1)～1020 (n): sub-coding unit；
1110,1120,1130,1140: voltage's distribiuting state；
1111,1112,1121,1122,1131,1132,1141,1142: state；
Vread-0: read voltage level；
VRead-1～VRead-18: soft decision read voltage level；
S1201～S1211: step；
b11～bnm: bit.
Detailed description of the invention
It is said that in general, memory storage apparatus (also referred to as, storage system) includes that duplicative is non-volatile Property memory module (rewritable non-volatile memory module) with controller (also referred to as, control electricity Road).Being commonly stored device storage device is to be used together with host computer system, so that data can be write by host computer system Enter to memory storage apparatus or from memory storage apparatus, read data.
Fig. 1 is host computer system shown by one example of the present invention embodiment and the showing of memory storage apparatus It is intended to.Fig. 2 is the computer shown by one example of the present invention embodiment, input/output device and memorizer The schematic diagram of storage device.
Refer to Fig. 1, host computer system 11 generally comprises computer 12 and input/output (input/output, letter Claim: I/O) device 13.Computer 12 includes microprocessor 122, random access memory (random access Memory, is called for short: RAM) 124, system bus 126 and data transmission interface 128.Input/output fills Put 13 and include mouse 21 such as Fig. 2, keyboard 22, display 23 and printer 24.Have to be understood that Being, the unrestricted input/output device of device 13 shown in Fig. 2, input/output device 13 can also include it His device.
In an exemplary embodiment, memory storage apparatus 10 is by data transmission interface 128 and main frame Other elements of system 11 are electrically connected with.By microprocessor 122, random access memory 124 with defeated Enter/running of output device 13 can write data into memory storage apparatus 10 or from memorizer storage dress Put reading data in 10.Such as, memory storage apparatus 10 can be Portable disk 25 as shown in Figure 2, (Solid State Drive is called for short: SSD) duplicative of 27 grades is non-volatile for memory card 26 or solid state hard disc Property memory storage apparatus.
Fig. 3 is host computer system shown by one example of the present invention embodiment and the showing of memory storage apparatus It is intended to.
It is said that in general, host computer system 11 is for coordinating to store number with memory storage apparatus 10 substantially According to any system.Although in this exemplary embodiment, host computer system 11 is to explain with computer system, But, in another exemplary embodiment, host computer system 11 can be digital camera, video camera, communicator, The system such as audio player or video player.Such as, it is digital camera (video camera) 31 in host computer system Time, type nonvolatile storage device is then by its SD card 32 used, mmc card 33, memory stick (memory stick) 34, CF card 35 or embedded storage device 36 (as shown in Figure 3). Embedded storage device 36 includes that (Embedded MMC is called for short: eMMC) embedded multi-media card. It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host computer system.
Fig. 4 is the schematic block diagram illustrating the memory storage apparatus shown in Fig. 1.
Refer to Fig. 4, memory storage apparatus 10 includes connecting interface unit 402, memorizer controls electricity Road unit 404 and reproducible nonvolatile memorizer module 406.
In this exemplary embodiment, connect interface unit 402 and be compatible with Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, is called for short: SATA) standard.However, it is necessary to be appreciated that, The invention is not restricted to this.In another exemplary embodiment, connecting interface unit 402 can also be to meet also (Parallel Advanced Technology Attachment, is called for short row Advanced Technology Attachment: PATA) mark Accurate, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, letter Claim: IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, is called for short: PCI Express) standard, USB (universal serial bus) (Universal Serial Bus, is called for short: USB) (Secure Digital is called for short: SD) interface standard, superelevation for standard, secure digital (Ultra High Speed-I is called for short: UHS-I) interface standard, ultrahigh speed secondary (Ultra High a speed generation Speed-II, is called for short: UHS-II) (Memory Stick is called for short: MS) interface mark for interface standard, memory stick Accurate, multimedia storage card (Multi Media Card, abbreviation: MMC) interface standard, built-in multimedia (Embedded Multimedia Card is called for short: eMMC) interface standard, general flash memory storage card (Universal Flash Storage, is called for short: UFS) interface standard, compact flash (Compact Flash, letter Claim: CF) interface standard, integrated form drive electrical interface (Integrated Device Electronics, be called for short: IDE) standard or other standards being suitable for.Connecting interface unit 402 can be with memorizer control circuit unit 404 It is encapsulated in a chip, or connection interface unit 402 is to be laid in one to comprise memorizer control circuit Outside the chip of unit 404.
Memorizer control circuit unit 404 is in order to perform with hardware pattern or multiple the patrolling of software pattern implementation Volume grid or control instruction and according to the instruction of host computer system 11 at type nonvolatile mould Block 406 carries out the write of data, reads and operate with erasing etc..
Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404 and the data that write in order to host system 11.Reproducible nonvolatile memorizer module 406 can be that (Single Level Cell is called for short: SLC) NAND type flash memory single-order memory element Module (that is, the flash memory module of 1 Bit data can be stored in one memory element), multistage storage (Multi Level Cell is called for short: MLC) NAND type flash memory module (that is, one storage unit Unit can store the flash memory module of 2 Bit datas), Complex Order memory element (Triple Level Cell, is called for short: TLC) NAND type flash memory module (that is, can store 3 in one memory element The flash memory module of Bit data), other flash memory module or other there is depositing of identical characteristics Memory modules.
Fig. 5 is the reproducible nonvolatile memorizer module shown by one example of the present invention embodiment Schematic block diagram.Fig. 6 is the schematic diagram of the memory cell array shown by one example of the present invention embodiment.
Refer to Fig. 5, reproducible nonvolatile memorizer module 406 include memory cell array 502, Word-line control circuit 504, bit line control circuit 506, row decoder (column decoder) 508, Data input/output buffer 510 and control circuit 512.
In this exemplary embodiment, memory cell array 502 can include the multiple storages storing data (select gate drain, is called for short: SGD) transistor 612 and multiple choosings for unit 602, multiple selection grid leak pole (select gate source, is called for short: SGS) transistor 614 and connect this little memory element to select grid source electrode A plurality of bit line 604, a plurality of word-line 606 and common source line 608 (as shown in Figure 6).Storage Unit 602 is to be arranged in bit line 604 and word-line 606 by array way (or in the way of three-dimensional stacking) Cross point on.When receiving write instruction from memorizer control circuit unit 404 or read instruction, Control circuit 512 can control character line control circuit 504, bit line control circuit 506, row decoder 508, data input/output buffer 510 writes data to memory cell array 502 or single from storage Reading data in element array 502, wherein word-line control circuit 504 is bestowed to word-line 606 in order to controlling Voltage, bit line control circuit 506 is in order to control the voltage bestowed to bit line 604, row decoder Column address in 508 foundation instructions is to select corresponding bit line, and data input/output buffer 510 It is configured to temporarily store data.
Each memory element in reproducible nonvolatile memorizer module 406 is with critical voltage Change and store one or more bit.Specifically, the control gate (control gate) of each memory element And there is an electric charge capture layer between passage.By bestowing a write voltage to control gate, thus it is possible to vary Electric charge mends the amount of electrons catching layer, thus changes the critical voltage of memory element.This changes critical voltage Program is also referred to as " writing the data to memory element " or " memory cells ".Along with changing of critical voltage Becoming, each memory element of memory cell array 502 has multiple storage state.And by reading Voltage may determine which storage state is memory element be belonging to, and obtains what memory element was stored whereby One or more bit.
Fig. 7 is the summary square of the memorizer control circuit unit shown by one example of the present invention embodiment Figure.
Refer to Fig. 7, memorizer control circuit unit 404 includes that memory management circuitry 702, main frame connect Mouth 704, memory interface 706 and error checking and correcting circuit 708.
Memory management circuitry 702 is in order to control the overall operation of memorizer control circuit unit 404.Tool For body, memory management circuitry 702 has multiple control instruction, and at memory storage apparatus 10 During running, these a little control instructions can be performed to carry out the write of data, read and operate with erasing etc..With During the operation of lower explanation memory management circuitry 702, it is equal to memorizer control circuit unit 404 is described Operation.
In this exemplary embodiment, the control instruction of memory management circuitry 702 is to come in fact with software pattern Make.Such as, memory management circuitry 702 has microprocessor unit (not shown) with read only memory (not Illustrate), and these a little control instructions are to be programmed so far in read only memory.When memory storage apparatus 10 During running, these a little control instructions can by microprocessor unit perform to carry out data write, read with The runnings such as erasing.
In another exemplary embodiment, the control instruction of memory management circuitry 702 can also program pattern Formula is stored in the specific region of reproducible nonvolatile memorizer module 406 (such as, in memory module It is exclusively used in the system area of storage system data) in.Additionally, memory management circuitry 702 has microprocessor Unit (not shown), read only memory (not shown) and random access memory (not shown).Particularly, this Read only memory has boot code (boot code), and when memorizer control circuit unit 404 is enabled Time, microprocessor unit can first carry out this boot code will be stored in type nonvolatile mould Control instruction in block 406 is loaded in the random access memory of memory management circuitry 702.Afterwards, Microprocessor unit can operate these a little control instructions to carry out the write of data, to read and operate with erasing etc..
Additionally, in another exemplary embodiment, the control instruction of memory management circuitry 702 can also one Hardware pattern carrys out implementation.Such as, memory management circuitry 702 includes microcontroller, Storage Unit Management Circuit, memorizer write circuit, memory reading circuitry, memorizer erasing circuit and data processing circuit. Storage Unit Management circuit, memorizer write circuit, memory reading circuitry, memorizer erasing circuit with Data processing circuit is electrically connected to microcontroller.Wherein, Storage Unit Management circuit can in order to manage The physics erasing unit of manifolding formula non-volatile memory module 406；Memorizer write circuit is in order to can Manifolding formula non-volatile memory module 406 assigns write instruction sequence to write data into duplicative In non-volatile memory module 406；Memory reading circuitry is in order to duplicative non-volatile memories Device module 406 assigns reading job sequence to read from reproducible nonvolatile memorizer module 406 Data；Memorizer erasing circuit refers in order to reproducible nonvolatile memorizer module 406 is assigned erasing Make sequence data to be wiped from reproducible nonvolatile memorizer module 406；And data process electricity Road is intended to write to the data of reproducible nonvolatile memorizer module 406 and from making carbon copies in order to process The data read in formula non-volatile memory module 406.Write instruction sequence, read job sequence and Erasing instruction sequence can distinctly include one or more procedure code or order code and in order to indicate duplicative non- Volatile 406 performs corresponding write, read and the operation such as erasing.
HPI 704 is electrically connected to memory management circuitry 702 and in order to receive and to identify master Instruction that machine system 11 is transmitted and data.It is to say, the instruction that transmitted of host computer system 11 and number According to being sent to memory management circuitry 702 by HPI 704.In this exemplary embodiment, HPI 704 is compatible with SATA standard.However, it is necessary to be appreciated that and the invention is not restricted to this, HPI 704 can also be compatible with PATA standard, IEEE 1394 standard, PCI Express mark Standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, EMMC standard, UFS standard, CF standard, IDE standard or other data transmission standards being suitable for.
Memory interface 706 is electrically connected to memory management circuitry 702 and can make carbon copies in order to access Formula non-volatile memory module 406.It is to say, be intended to write to type nonvolatile The data of module 406 can be converted to reproducible nonvolatile memorizer module by memory interface 706 406 receptible forms.Specifically, if memory management circuitry 702 duplicative to be accessed is non- Volatile 406, memory interface 706 can transmit the job sequence of correspondence.Such as, this A little job sequences can include that the write instruction sequence of instruction write data, instruction read the reading instruction of data Sequence, instruction wipe the erasing instruction sequence of data and in order to indicate various storage operation (such as, Change read voltage level or perform garbage reclamation program etc.) corresponding job sequence, differ at this One repeats.These job sequences are e.g. produced by memory management circuitry 702 and are connect by memorizer Mouth 706 is sent to reproducible nonvolatile memorizer module 406.These job sequences can include one or Multiple signals, or the data in bus.These signals or data can include order code or procedure code. Such as, in reading job sequence, the information such as the identification code of reading, storage address can be included.
Error checking and correcting circuit 708 are electrically connected to memory management circuitry 702 and in order to hold Row error checking and correction program are to guarantee the correctness of data.Specifically, memory management circuitry is worked as 702 when receiving write instruction from host computer system 11, and error checking can be corresponding with correcting circuit 708 The data of this write instruction produce corresponding error correcting code, and (error correcting code is called for short: ECC) And/or error checking code (error detecting code, is called for short: EDC), and memory management circuitry 702 Can the data of this write instruction corresponding be write with corresponding error correcting code and/or error checking code extremely can In manifolding formula non-volatile memory module 406.Afterwards, when memory management circuitry 702 is from making carbon copies Can read, when formula non-volatile memory module 406 reads data, the error correction that these data are corresponding simultaneously Code and/or error checking code, and error checking and correcting circuit 708 can according to this error correcting code and/ Or the data that error checking code is to being read perform error checking and correction program.
In an exemplary embodiment, memorizer control circuit unit 404 also include buffer storage 710 with Electric power management circuit 712.Buffer storage 710 be electrically connected to memory management circuitry 702 and It is configured to temporarily store and comes from data and the instruction of host computer system 11 or come from duplicative non-volatile memories The data of device module 406.Electric power management circuit 712 is electrically connected to memory management circuitry 702 also And in order to control the power supply of memory storage apparatus 10.
Fig. 8 is the management type nonvolatile mould shown by one example of the present invention embodiment The schematic diagram of block.It will be appreciated that be described herein reproducible nonvolatile memorizer module 406 When physics wipes the running of unit, carry out operating physical with the word such as " selection ", " packet ", " division ", " association " Erasing unit is concept in logic.It is to say, the physics of reproducible nonvolatile memorizer module The physical location of erasing unit is not changed, but in logic to reproducible nonvolatile memorizer module Physics erasing unit operate.
It is single that the memory element of reproducible nonvolatile memorizer module 406 can constitute the programming of multiple physics Unit, and these a little physics programming units can constitute multiple physics erasing unit.Specifically, same word Memory element on unit's line can form one or more physics programming unit.If each memory element can store The bit of more than 2, then the physics programming unit on same word-line at least can be classified as lower physics Programming unit and upper physics programming unit.Such as, the minimum effective bit (Least of a memory element Significant Bit, is called for short: LSB) be belonging to lower physics programming unit, and a memory element is the highest (Most Significant Bit is called for short: MSB) be belonging to physics programming unit significant bit.General next Saying, in MLC NAND type flash memory, the writing speed of lower physics programming unit can be more than upper The writing speed of physics programming unit, or the reliability of lower physics programming unit to be above physics programming single The reliability of unit.In this exemplary embodiment, physics programming unit is the minimum unit of programming.That is, thing Reason programming unit is the minimum unit of write data.Such as, physics programming unit is physical page or thing Reason fan (sector).If physics programming unit is physical page, then each physics programming unit generally includes Data bit district and redundancy ratio special zone.Data bit district comprises multiple physics fan, in order to store user Data, and redundancy ratio special zone is in order to store the data (such as, error correcting code) of system.At this example In embodiment, data bit district comprises 32 physics fans, and the size of a physics fan is 512 bit groups (byte is called for short: B).But, in other exemplary embodiment, data bit district also can comprise 8, 16 or number more or less of physics fan, the present invention is not limiting as size and the number of physics fan. On the other hand, physics erasing unit is the least unit of erasing.That is, each physics erasing unit contains The memory element being wiped free of in the lump of minimal amount.Such as, physics erasing unit is physical blocks.
Refer to Fig. 8, memory management circuitry 702 can be by reproducible nonvolatile memorizer module 406 Physics erasing unit 800 (0)～800 (R) be logically divided into multiple region, for example, memory block 802 with System area 806.
The physics erasing unit of memory block 802 is to store the data from host computer system 11.Memory block Valid data and invalid data can be stored in 802.Such as, a valid data are deleted when host computer system Time, deleted data may also be stored in memory block 802, but can be marked as invalid data. Do not store physics erasing unit the most idle (spare) physics erasing unit of valid data.Such as, It is wiped free of later physics erasing unit and will become idle physics erasing unit.If memory block 802 or be When having physics erasing unit to damage in system district 806, the physics erasing unit in memory block 802 can also be used Replace the physics erasing unit of damage.If memory block 802 does not has can physics erasing unit When replacing the physics erasing unit damaged, then whole memorizer may be deposited by memory management circuitry 702 Storage device 10 is declared as write protection (write protect) state, and cannot write data again.Additionally, have The physics erasing unit of storage valid data is also referred to as non-idle (non-spare) physics erasing unit.
The physics erasing unit of system area 806 is to record system data, and wherein this system data includes Manufacturer and model, physics erasing unit number, each physics of memory chip about memory chip The physics programming unit number etc. of erasing unit.
Memory block 802 can be according to different memorizer rule from the quantity of the physics of system area 806 erasing unit Lattice and different.Further, it is necessary to be appreciated that, in the running of memory storage apparatus 10, physics Erasing unit closes and is coupled to the packet relation of memory block 802 and system area 806 and may dynamically change.Example As, wipe unit damage when the physics in system area 806 and wiped unit by the physics of memory block 802 and take Dai Shi, then the script physics erasing unit in memory block 802 can be associated to system area 806.
Memory management circuitry 702 meeting configuration logic unit 810 (0)～810 (D) is to map to memory block 802 In physics erasing unit 800 (0)～800 (A).Such as, in this exemplary embodiment, host computer system 11 It is to access the data in memory block 802, therefore, each logical block by logical address 810 (0)～810 (D) refer to a logical address.Additionally, in an exemplary embodiment, each logic list Unit 810 (0)～810 (D) may also mean that a logic fan, programming in logic unit, a logic erasing Unit or be made up of multiple continuous print logical addresses.Each logical block 810 (0)～810 (D) is to map To one or more physical location.In this exemplary embodiment, a physical location refers to a physics erasing Unit.But, in another exemplary embodiment, physical location can also be a physical address, One physics fan, a physics programming unit or be made up of multiple continuous print physical address, the present invention It is not any limitation as.Memory management circuitry 702 can be by the mapping relations between logical block and physical location It is recorded at least one logical-physical mapping table.When host computer system 11 is intended to read from memory storage apparatus 10 Data or when writing data to memory storage apparatus 10, memory management circuitry 702 can be according to this logic -physical mappings table performs the data access for memory storage apparatus 10.
Fig. 9 is the critical voltage distribution of the multiple memory element shown by one example of the present invention embodiment Schematic diagram.
Refer to Fig. 9, the critical voltage of transverse axis representative memory cell, and longitudinal axis representative memory cell number. Such as, Fig. 9 is to represent the critical voltage of each memory element in a physical location.It is assumed herein that when certain The critical voltage of one memory element is to fall when being distributed 901, and what this memory element was stored is bit " 1 "； If the critical voltage of some memory element is to fall when being distributed 902, what this memory element was stored is ratio Special " 0 ".It is noted that in this exemplary embodiment, each memory element is to store one Bit, thus critical voltage be distributed two kinds may.But, in other exemplary embodiment, if one Memory element is to store multiple bit, then the distribution of corresponding critical voltage then may have four kinds, eight Plant or other are the most individual possible.Additionally, the present invention is also not intended to each bit representated by distribution.Example As, in another exemplary embodiment of Fig. 9, distribution 901 is to represent bit " 0 ", and is distributed 902 and is Represent bit " 1 ".
To read data, memory management circuitry 702 from reproducible nonvolatile memorizer module 406 A reading job sequence can be sent to reproducible nonvolatile memorizer module 406.This reads sequence of instructions Arrange in order to indicate the multiple memory element read in a certain logical block or physical location to obtain multiple ratios Special.Such as, reading job sequence according to this, reproducible nonvolatile memorizer module 406 can basis Read voltage level Vread-0Read multiple memory element and being sent to by the Bit data obtained to deposit Reservoir management circuit 702.Such as, if the critical voltage of some memory element is less than read voltage level Vread-0(such as, belong to the memory element of distribution 901), then memory management circuitry 702 can read bit “1”；If the critical voltage of some memory element is more than read voltage level Vread-0(such as, belong to distribution The memory element of 902), then memory management circuitry 702 can read bit " 0 ".
But, along with the use time of reproducible nonvolatile memorizer module 406 increases and/or operation Environment changes, and distribution 901 and 902 can occur performance degradation (degradation).After there is performance degradation, Distribution 901 may be the most close to each other the most overlapped with 902.Such as, distribution 911 and distribution 912 are respectively intended to the distribution 901 and 902 after representing performance degradation.Distribution 911 comprises one with distribution 912 Individual overlapping region 913 (representing with oblique line).Overlapping region 913 indicates and is stored in some memory element Should be bit " 1 ", but its critical voltage is more than read voltage level Vread-0；Or, have some to store Stored in unit should be bit " 0 ", but its critical voltage is less than read voltage level Vread-0.Send out After raw performance degradation, if persistently using read voltage level Vread-0Read and belong to distribution 911 or distribution The memory element of 912, then the bit read may comprise more mistake.Such as, distribution will be belonged to The memory element of 911 is mistaken for belonging to distribution 912, or the memory element belonging to distribution 912 is mistaken for Belong to distribution 911.Therefore, in this exemplary embodiment, error checking can be to reading with correcting circuit 708 The Bit data got is decoded, thus corrects mistake therein.
In this exemplary embodiment, to data are stored to reproducible nonvolatile memorizer module 406 In, error checking and correcting circuit 708 can encode and be intended to store to reproducible nonvolatile memorizer module The data of 406 also produce a coding unit.Such as, this coding unit is made up of the data after encoding. This coding unit is belonging to block code.Thereafter, memory management circuitry 702 can send a write instruction Sequence is to reproducible nonvolatile memorizer module 406.This is compiled by this write instruction sequence in order to indicate The region that code unit is stored in reproducible nonvolatile memorizer module 406.Such as, this district Territory can be at least one physical location and include multiple memory element (the hereinafter also referred to first storage list Unit).According to this write instruction sequence, reproducible nonvolatile memorizer module 406 can be by single for this coding Unit stores in the most a little first memory element.Thereafter, this district is read when memory management circuitry 702 instruction During data in territory, reproducible nonvolatile memorizer module 406 can be from these a little first memory element Read this coding unit, and error checking can perform corresponding decoding program to solve with correcting circuit 708 This coding unit of code.
Figure 10 is the schematic diagram of the block code shown by one example of the present invention embodiment.
Refer to Figure 10, coding unit 1010 belongs to block code and includes bit b11～bnm.Bit b11～bnmSub-coding unit 1020 (1)～1020 (n) can be grouped into.Each sub-coding unit 1020 (1)～1020 (n) there is m bit.N Yu m can be greater than any positive integer of 1.At this In exemplary embodiment, in coding unit 1010, the bit (hereinafter also referred to predetermined bit) of part is by multiple Encoding procedure is determined.Such as, the volume that direction is row (row) direction (such as, from left to right) can be encoded Coded program is considered as first kind encoding procedure, and by coding that coding direction is column direction (such as, from top to bottom) Program is considered as Equations of The Second Kind encoding procedure.In an exemplary embodiment, first kind encoding procedure also referred to as row (row) Encoding procedure, and Equations of The Second Kind encoding procedure also referred to as row (column) encoding procedure.
In this exemplary embodiment, first kind encoding procedure can first be performed, and encodes journey according to the first kind The coding result of sequence, Equations of The Second Kind encoding procedure can continue and be performed.For example, it is assumed that the user to be stored Packet b Han bit11～b1p、b21～b2p、…、br1～brp(representing with oblique line), then encode journey in the first kind In sequence, bit b11～b1p、b21～b2p、…、br1～brpCan be encoded to respectively obtain bit b11～b1m(i.e., Sub-coding unit 1020 (1)), b21～b2m(that is, sub-coding unit 1020 (2)) ..., br1～brm(that is, son Coding unit 1020 (n)).Bit b1q～b1mFor corresponding to bit b11～b1pError correcting code, bit b2q～b2mFor corresponding to bit b21～b2pError correcting code, bit brq～brmFor corresponding to bit br1～brp Error correcting code, by that analogy, wherein q be equal to p+1.Obtaining sub-coding unit 1020 (1)～1020 (n) Afterwards, Equations of The Second Kind encoding procedure can be performed.Such as, in Equations of The Second Kind encoding procedure, bit b11～br1(i.e., The 1st bit in each sub-coding unit 1020 (1)～1020 (n)), bit b12～br2(that is, each The 2nd bit in individual sub-coding unit 1020 (1)～1020 (n)) ..., bit b1m～brm(that is, each M-th bit in individual sub-coding unit 1020 (1)～1020 (n)) can be encoded to respectively obtain bit b11～bn1、b12～bn2、…、b1m～bnm.Bit bs1～bn1For corresponding to bit b11～br1Error correction Code, bit bs2～bn2For corresponding to bit b12～br2Error correcting code, bit bsm～bnmFor corresponding to Bit b1m～brmError correcting code, by that analogy, wherein s be equal to r+1.
After being read out by coding unit 1010, correspond to used coded sequence, coding unit 1010 can be decoded.Such as, in this exemplary embodiment, decoding direction be the decoding program of column direction (also It is referred to as Equations of The Second Kind decoding program) can first be performed, and according to the decoded result of Equations of The Second Kind decoding program, decoding Direction is that can continue is performed for the decoding program (also referred to as first kind decoding program) of line direction.Such as, In two class decoding programs, bit bs1～bn1、bs2～bn2、…、bsm～bnmCan be respectively used to bit b11～br1、 b12～br2、…、b1m～brmIt is decoded.Obtaining decoded bit b11～br1、b12～br2、…、b1m～brm Afterwards, first kind decoding program can be performed.Such as, in first kind decoding program, by Equations of The Second Kind solution Coded program decoded bit b1q～b1m、b2q～b2m、…、brq～brmCan be used, respectively, to by Equations of The Second Kind Bit b after decoding process11～b1p、b21～b2p、…、br1～brpIt is decoded obtaining decoded User data.
It is noted that the composition of the coding unit mentioned in above-mentioned exemplary embodiment and coding/decoding are suitable Sequence is an example and is not used to limit the present invention.Such as, in another exemplary embodiment, produced Error correcting code can also be aligned in correspondence user data before or be interspersed in correspondence use In person's data.Such as, in an exemplary embodiment, when encoding user data, it is also possible to be first to hold Row Equations of The Second Kind encoding procedure, then the coding result further in accordance with Equations of The Second Kind encoding procedure performs first kind coding Program；Corresponding, when decoding coding unit, it is also possible to be to first carry out first kind decoding program, so After perform Equations of The Second Kind decoding program further according to the decoded result of first kind decoding program.Additionally, at another In exemplary embodiment, if being to first carry out first kind encoding procedure to perform second again when encoding user data Class encoding procedure, then can also be to first carry out first kind decoding program to perform the again when decoding coding unit Two class decoding programs；Or, if being to first carry out Equations of The Second Kind encoding procedure to hold again when encoding user data Row first kind encoding procedure, then can also be to first carry out Equations of The Second Kind decoding program again when decoding coding unit Perform first kind decoding program.
In this exemplary embodiment, first kind encoding procedure (or first kind decoding program) encodes journey with Equations of The Second Kind The coding direction of sequence (or Equations of The Second Kind decoding program) is different, but first kind encoding procedure (or first kind decoding Program) identical or different coding/decoding can be used to calculate with Equations of The Second Kind encoding procedure (or Equations of The Second Kind decoding program) Method.Such as, first kind encoding procedure can be to comprise low-density parity with corresponding first kind decoding program LDPC), BCH code and Reed Solomon code check that (low density parity code, is called for short correcting code: (Reed-solomon code, be called for short: RS code), square turbine code (block turbo code, be called for short: At least one of various coding/decoding algorithm such as BTC)；And Equations of The Second Kind encoding procedure and corresponding Equations of The Second Kind Decoding program can also be at least one comprising above-mentioned coding/decoding algorithm or other kinds of volume/ Decoding algorithm, the present invention is not any limitation as.Additionally, in another exemplary embodiment of Figure 10, in order to produce The direction of multiple coding/decoding programs of raw coding unit 1010 can also be any direction or meet arbitrarily Rule, and it is not limited to above-mentioned line direction and column direction.Such as, in an exemplary embodiment, it is also possible to be Diagonally come bit b11、b22、b33Etc. encoding, then can be along right when decoding Linea angulata direction specific bit is performed decoding.Or, in another exemplary embodiment, during coding/decoding Some row, some row or some bit etc. can also be skipped.
In this exemplary embodiment, memory management circuitry 702 can receive a reading from host computer system 11 and refer to Order.This reads instruction e.g. instruction reading and maps to the physical location at the first memory element place at least One logical block.According to this read instruction, memory management circuitry 702 can send a reading job sequence (with It is also referred to as down hard decision and reads job sequence) to reproducible nonvolatile memorizer module 406.Additionally, In another exemplary embodiment, this hard decision reads job sequence and is also likely to be in execution garbage reclamation Used during the data administrator of the arbitrarily memory inside such as (garbage collection).This hard decision is read Instruction fetch sequence is come with a read voltage level (hereinafter also referred to hard decision read voltage level) in order to indicate Data are read from the first memory element.This hard decision read voltage level may refer to read due to hard decision Instruction is read according to this hard decision in job sequence or by reproducible nonvolatile memorizer module 406 Sequence is tabled look-up voluntarily and is obtained.Job sequence, type nonvolatile is read according to hard decision Module 406 can bestow a read voltage corresponding to this hard decision read voltage level (such as, in Fig. 9 Read voltage level VRead-0) to the first memory element and return multiple Bit data according to this.This compare Special data can form a coding unit (hereinafter also referred to hard decision coding unit).This hard decision coding unit Belong to block code.Introduction about block code has been specified in, therefore does not repeats at this.Then, mistake Check that this hard decision coding unit can be performed a decoding program with correcting circuit 708 (determines the most firmly Plan decoding program).
In this exemplary embodiment, hard decision decoding program is belonging to iteration decoding program.Such as, firmly In decision-making decoding program, error checking and correcting circuit 708 can perform iteration decoding computing at least one times, With reliability information (such as, the decoding by updating at least one bit in hard decision coding unit with iterating Initial value) improve hard decision coding unit be decoded into power.Iteration decoding computing each time can comprise The same or similar decoding operation introduced in the exemplary embodiment of Figure 10.In general, according to hard decision The number of mistake (also referred to as error bit) in coding unit, hard decision decoding program may success or failure. Such as, after iteration decoding computing at least one times, if the success of hard decision decoding program is (such as, wrong Flase drop is looked into and is judged that the mistake in hard decision coding unit is corrected the most with correcting circuit 708), then mistake inspection Look into and can export decoded hard decision coding unit with correcting circuit 708.Such as, this is decoded the most certainly Plan coding unit can be transferred into host computer system 11 or (such as, restore to answer in order to perform other operations Write original in formula non-volatile memory module 406 or other memory element).Otherwise, if because the most certainly In plan coding unit, the number of error bit is too much and/or the distribution of these a little error bits is just at cannot Position being corrected etc., error checking and correcting circuit 708 may be because of performed iteration decodings The number of times of computing reaches a preset times and judges the failure of hard decision decoding program.Although additionally, at this model In example embodiment, hard decision decoding program is belonging to iteration decoding program, but, in another exemplary embodiment In, hard decision decoding program can also be belonging to non-iteration decoding program.
If the failure of hard decision decoding program, memory management circuitry 702 can send another and read job sequence (the hereinafter also referred to first soft decision reads job sequence) is to reproducible nonvolatile memorizer module 406. First soft decision reads job sequence in order to indicate according to another read voltage level (hereinafter also referred to first Soft decision read voltage level) to read data from the first memory element.Such as, this first soft decision reads Voltage level can be specified in the first soft decision reads job sequence, or can also be non-by duplicative Volatile 406 is tabled look-up voluntarily according to the first soft decision reading job sequence and is obtained.
After receiving the first soft decision and reading job sequence, reproducible nonvolatile memorizer module 406 can read the first memory element to obtain another coding list with this first soft decision read voltage level Unit's (the hereinafter also referred to first soft decision coding unit).Such as, read job sequence according to the first soft decision, Reproducible nonvolatile memorizer module 406 can be bestowed corresponding to this first soft decision read voltage level A read voltage to the first memory element and return multiple Bit data according to this.These a little Bit datas This first soft decision coding unit can be formed.This first soft decision coding unit falls within block code.Then, Error checking can perform another decoding program (the most also to the first soft decision coding unit with correcting circuit 708 It is referred to as the first soft decision decoding program).
If the first soft decision decoding program success, error checking can export decoded with correcting circuit 708 First soft decision coding unit.Such as, this decoded first soft decision coding unit can be transferred into master Machine system 11 or in order to perform other operation.But, if the first soft decision decoding program failure, memorizer Management circuit 702 can send another and read job sequence (the hereinafter also referred to second soft decision reads job sequence) To reproducible nonvolatile memorizer module 406.Second soft decision reads job sequence in order to indicate root Come from the first storage single according to another read voltage level (the hereinafter also referred to second soft decision read voltage level) Unit reads data.After receiving the second soft decision and reading job sequence, duplicative is non-volatile to be deposited It is another to obtain that memory modules 406 can read the first memory element with this second soft decision read voltage level One coding unit (the hereinafter also referred to second soft decision coding unit).Such as, refer to according to the second soft decision reading Make sequence, reproducible nonvolatile memorizer module 406 to bestow read corresponding to this second soft decision One read voltage of voltage level to the first memory element and returns multiple Bit data according to this.These are a little Bit data can form this second soft decision coding unit.This second soft decision coding unit falls within block Code.Then, error checking can perform another decoding with correcting circuit 708 to the second soft decision coding unit Program (the hereinafter also referred to second soft decision decoding program).
In an exemplary embodiment, performing the first soft decision decoding program and performing the second soft decision decoding The soft decision decoding program performing other can also be included between program.Such as, in an exemplary embodiment, After the first soft decision decoding program failure, another soft decision read voltage level can be used to read the One memory element is to obtain another soft decision coding unit, and another soft decision decoding program (is also referred to as below It is the 3rd soft decision decoding program) can be performed.After this 3rd soft decision decoding program failure, above-mentioned Obtain the second soft decision coding unit and perform the operation of the second soft decision decoding program and just can be performed.This Outward, more or less of soft decision read voltage level can be determined and use, more or less of soft Decision-making decoding program can also be performed, and does not repeats at this.
It is noted that " hard decision " and " soft decision " mentioned in example embodiments herein is only It is used to read operation corresponding to difference and decoding operation.Such as, in an exemplary embodiment, soft decision Decoding program must be to perform after the failure of hard decision decoding program.But, in another exemplary embodiment In, if performing solution according to channel status (such as, extent of deterioration or the critical voltage of memory element is distributed) The decoding difficulty just identifying a certain coded data before Ma is higher, then can not also perform hard decision Decoding program and directly read soft decision coding unit and perform correspondence soft decision decoding program.
In this exemplary embodiment, the first soft decision read voltage level and the second soft decision read voltage electricity Difference between Ping is relevant with the extent of deterioration of the first memory element.Such as, the loss of the first memory element Degree is relevant with the behaviour in service of the first memory element or current operation environment.Such as, if the first storage is single The erasing times of the reading times of unit, the write number of times of the first memory element and/or the first memory element increases Add, then the extent of deterioration of the first memory element may corresponding increase.Such as, if certain data leaves in Time interval in one memory element increases, then the extent of deterioration of the first memory element may corresponding increase. Such as, if the temperature of the operating environment of current reproducible nonvolatile memorizer module 106 or humidity too High or the lowest, then the extent of deterioration of the first memory element is likely to correspondence to increase.Additionally, the first storage The extent of deterioration of unit is likely to can be with the correctness/error rate of the data being stored in the first memory element Relevant.Such as, if the extent of deterioration of the first memory element is the highest, then it is stored in the first memory element The correctness of the data error rate of data that is the lowest or that be stored in the first memory element is the highest.At a model In example embodiment, the extent of deterioration of the first memory element can represent by an extent of deterioration value.This damages The size of consumption degree value can be that the extent of deterioration with the first memory element becomes positive correlation or negative correlation.Such as, If extent of deterioration value is the biggest, represent that the extent of deterioration of the first memory element is the highest, then this extent of deterioration value Size is to be positively correlated with the extent of deterioration of the first memory element；If extent of deterioration value is the biggest, represent that first deposits The extent of deterioration of storage unit is the lowest, then the size of this extent of deterioration value is that negative is about the first memory element Extent of deterioration.Extent of deterioration (such as, extent of deterioration value) according to the first memory element, memorizer management electricity Road 702 may decide that the first soft decision read voltage level and the second soft decision read voltage level.At this In exemplary embodiment, between the first soft decision read voltage level and the second soft decision read voltage level Difference becomes negative correlation with the extent of deterioration of the first memory element.If it is to say, the damage of the first memory element Consumption degree is the highest, then between the first soft decision read voltage level and the second soft decision read voltage level Difference can be the least；If the extent of deterioration of the first memory element is the lowest, then the first soft decision read voltage level And the difference between the second soft decision read voltage level can be the biggest.
In general, the extent of deterioration of memory element often has influence on the critical voltage distribution of memory element, Therefore, in an exemplary embodiment, memory management circuitry 702 can also be according to the first memory element Voltage's distribiuting state (that is, critical voltage distribution) determines the first soft decision read voltage level and second Soft decision read voltage level.The voltage's distribiuting state of the first memory element can be by scanning at least portion Point the first memory element, table look-up according to the extent of deterioration value of memory element or by analyze a certain The number etc. of the mistake (that is, error bit) of statistics in secondary decoding program (such as, hard decision decoding program) Mode obtains, and the present invention is not limiting as obtaining the practice of the voltage's distribiuting state of the first memory element.Additionally, In an exemplary embodiment, memory management circuitry 702 is the electricity complete by analyzing the first memory element Pressure distribution determines the first soft decision read voltage level and the second soft decision read voltage level.So And, in another exemplary embodiment, memory management circuitry 702 can also only analyze the first memory element Voltage's distribiuting state in the higher region of error rate (such as, the overlapping region 913 in Fig. 9 and near) The first soft decision read voltage level and the second soft decision read voltage level can be determined, without going Obtain the voltage's distribiuting state that the first memory element is complete, to save the operating time.
In an exemplary embodiment, memory management circuitry 702 can be according to the voltage of the first memory element The gap width between two states (the also referred to as first state and the second state) adjacent in distribution and/ Or the overlapping degree of these two states determines that the first soft decision read voltage level and the second soft decision read Voltage level.Such as, in an exemplary embodiment, adjacent in the voltage's distribiuting state of the first memory element Two states between gap width can read with the first soft decision read voltage level and the second soft decision Difference between voltage level becomes positive correlation.Such as, if the relief width between the first state and the second state Spend the biggest, then the difference between the first soft decision read voltage level and the second soft decision read voltage level The biggest.This gap width may refer to the distance between the summit of adjacent two state, or also Adjacent two end points that may refer to adjacent two state (such as, in Fig. 9, is distributed the right-hand member of 901 Point be distributed 902 left end point) between distance.Additionally, in an exemplary embodiment, the first storage is single The overlapping degree of two states adjacent in the voltage's distribiuting state of unit can be with the first soft decision read voltage electricity Put down and become negative correlation with the difference between the second soft decision read voltage level.Such as, if the first state and the The overlapping degree of two-state is the highest (such as, in Fig. 9, in overlapping region 913, the number of memory element is the most), Then the difference between the first soft decision read voltage level and the second soft decision read voltage level is the biggest.
Figure 11 is that the soft decision read voltage level shown by one example of the present invention embodiment is single with storage The schematic diagram of the critical voltage distribution of unit.
Refer to Figure 11, it is assumed that each first memory element is in order to store a Bit data and 4 Individual time point (that is, first time point, the second time point, the 3rd time point and the 4th time point), first deposits The voltage's distribiuting state of storage unit is respectively voltage's distribiuting state 1110,1120,1130 and 1140.
In this exemplary embodiment, between the state 1121 and 1122 in voltage's distribiuting state 1120 between Gap length degree is less than the gap width between the state 1111 and 1112 in voltage's distribiuting state 1110, therefore, The soft decision read voltage level V that can be used corresponding to voltage's distribiuting state 1120Read-4～VRead-6 In difference between any two adjacent soft decision read voltage level can be less than corresponding to voltage's distribiuting state 1110 and the soft decision read voltage level V that can be usedRead-1～VRead-3In any two adjacent soft certainly Difference between plan read voltage level.
In this exemplary embodiment, the state 1131 in voltage's distribiuting state 1130 is overlapped with 1132, Therefore not there is between state 1131 and 1132 gap (that is, gap width is zero).Therefore, corresponding to voltage Distribution 1130 and the soft decision read voltage level V that can be usedRead-7～VRead-11In any two The adjacent difference between soft decision read voltage level can be less than corresponding to voltage's distribiuting state 1120 The soft decision read voltage level V that can be usedRead-4～VRead-6In any two adjacent soft decisions read Difference between voltage level.
In this exemplary embodiment, the state 1141 in voltage's distribiuting state 1140 with 1142 overlapping journey Degree is more than the overlapping degree of the state 1131 and 1132 in voltage's distribiuting state 1130, therefore, soft decision Read voltage level VRead-12～VRead-18In difference between any two adjacent soft decision read voltage level Value can be less than soft decision read voltage level VRead-7～VRead-11In any two adjacent soft decisions read electricity Difference between voltage level.
In general, if the gap width between state adjacent in the voltage's distribiuting state of memory element is got over The overlapping degree of little or adjacent state is the highest, then the data read out from these a little memory element are comprised The number of error bit the most, and may need to perform more soft decision decoding program The data decoding that can successfully will read out.Therefore, in an exemplary embodiment, made except reducing Soft decision read voltage level between difference outside, it is also possible to increase the soft decision that can use and read The number of power taking voltage level, promotes and is decoded into power.Such as, in the exemplary embodiment of Figure 11, electricity The overlapping degree of the state 1141 and 1142 in pressure distribution 1140 is more than voltage's distribiuting state 1130 In the overlapping degree of state 1131 and 1132, therefore, permissible corresponding to voltage's distribiuting state 1140 The soft decision read voltage level V usedRead-12～VRead-18Number can be set to more than corresponding to Voltage's distribiuting state 1130 and the soft decision read voltage level V that can be usedRead-7～VRead-11Number Mesh.The rest may be inferred, in another exemplary embodiment, along with the gap width between adjacent state changes, The number of the corresponding soft decision read voltage level that can be used can also be increased or decreased.
In an exemplary embodiment, the voltage's distribiuting state current corresponding to the first memory element or loss journey The multiple soft decision read voltage level spent and determine can be considered as belonging to same soft decision read voltage Level group.Belong in multiple soft decision read voltage level of same soft decision read voltage level group and appoint Difference between two adjacent soft decision read voltage level can be identical or different.If hard decision decodes Procedure failure, then the corresponding multiple soft decision read voltage level in soft decision read voltage level group can To be used to one by one read corresponding soft decision coding unit.Such as, electricity is read with the soft decision in Figure 11 Voltage level VRead-12～VRead-18As a example by, if the failure of hard decision decoding program, then soft decision read voltage electricity Flat VRead-12Can first be used to read the first memory element and a soft decision decoding program can be performed； If this soft decision decoding program failure, then soft decision read voltage level VRead-13Can continue and be used to read First memory element and a corresponding soft decision decoding program can be performed；If this soft decision decoding journey Sequence is still failed, then soft decision read voltage level VRead-14Can continue and be used to read the first memory element also And a corresponding soft decision decoding program can be performed；If this soft decision decoding program is still failed, the softest Decision-making read voltage level VRead-15Can continue be used to read the first memory element and one corresponding soft Decision-making decoding program can be performed；If this soft decision decoding program is still failed, then soft decision read voltage electricity Flat VRead-16Can continue and be used to read the first memory element and a corresponding soft decision decoding program meeting It is performed, by that analogy, until some soft decision decoding program success or soft decision read voltage level Till in group, all of soft decision read voltage level is all previously used.Additionally, the present invention is not limiting as belonging to The use order of each soft decision read voltage level in same soft decision read voltage level group. Such as, in another exemplary embodiment, soft decision read voltage level VRead-12～VRead-18It is according to electricity The size of pressure value or any regular to be used successively.
In an exemplary embodiment, each soft decision belonging to same soft decision read voltage level group is read Power taking voltage level can disposably be determined.Such as, according to the extent of deterioration of the first memory element, note Record has the look-up table of the soft decision read voltage level group of correspondence can be chosen or produce and this soft decision In read voltage level group, all of soft decision read voltage level can be obtained.But, at another example In embodiment, belong to each soft decision read voltage level of same soft decision read voltage level group then It is to use at needs the most just can immediately determine.Such as, in an exemplary embodiment, if hard decision solution Coded program failure, the most only soft decision read voltage level VRead-12Can first be determined and used；You After, if corresponding to soft decision read voltage level VRead-12Soft decision decoding program also failure, then belong to The next soft decision read voltage level of same soft decision read voltage level group just can continue and be determined And used.
In an exemplary embodiment, if the failure of hard decision decoding program, memory management circuitry 702 can be held Row one optimal read voltage level tracing program (optimal read voltage level tracking process) To determine the optimal read voltage level corresponding to the first memory element.Such as, the example at Figure 11 is implemented In example, in voltage's distribiuting state 1110, the optimal read voltage level corresponding to the first memory element can Can be soft decision read voltage level VRead-1；In voltage's distribiuting state 1120, corresponding to the first storage The optimal read voltage level of unit is probably soft decision read voltage level VRead-4；At voltage's distribiuting shape In state 1130, the optimal read voltage level corresponding to the first memory element is probably soft decision read voltage Level VRead-7；In voltage's distribiuting state 1140, corresponding to the optimal read voltage of the first memory element Level is probably soft decision read voltage level VRead-12.Belong to same soft decision read voltage level group Other soft decision read voltage level can be to set according to this optimal read voltage level.Such as, In an exemplary embodiment, memory management circuitry 702 can be according to the extent of deterioration of the first memory element Or voltage's distribiuting state determines the difference between any two adjacent soft decision read voltage level.About How to determine two adjacent soft decisions according to extent of deterioration or the voltage's distribiuting state of the first memory element Difference between read voltage level is specified in, does not repeats at this to repeat.Obtaining optimal reading After voltage level, memory management circuitry 702 can be according to this optimal read voltage level and determined Fixed difference determines other soft decision read voltage level one by one.Such as, the example at Figure 11 is implemented In example, in voltage's distribiuting state 1140, the optimal read voltage level corresponding to the first memory element is Soft decision read voltage level VRead-12, then after determining a difference, soft decision read voltage level VRead-13Can be by by soft decision read voltage level VRead-12Deduct this difference and obtain, and soft certainly Plan read voltage level VRead-14Then can be by by soft decision read voltage level VRead-12Poor plus this Value and obtain.In another exemplary embodiment, the difference determined can also be that same soft decision reads Difference between the soft decision read voltage level that in voltage level group, magnitude of voltage is maximum and minimum.Such as, In an exemplary embodiment of Figure 11, memory management circuitry 702 can be according to the damage of the first memory element Consumption degree or voltage's distribiuting state determine soft decision read voltage level VRead-17With VRead-18Between Difference.Then, memory management circuitry 702 can be according to soft decision read voltage level VRead-12And Soft decision read voltage level VRead-17With VRead-18Between difference set soft decision read voltage electricity Flat VRead-12～VRead-18.Additionally, in another exemplary embodiment, the difference determined can also be any Difference between two non-conterminous soft decision read voltage level.
In an exemplary embodiment, described first soft decision read voltage level is read with described second soft decision One of them of power taking voltage level can correspond to the optimal read voltage level of the first memory element.More For body, its of described first soft decision read voltage level and described second soft decision read voltage level One of correspond to the optimal read voltage level of the current voltage's distribiuting state of the first memory element, and And described first soft decision read voltage level and described second soft decision read voltage level is the most another It is the soft decision read voltage level adjacent with this optimal read voltage level first.But, at another model In example embodiment, described first soft decision read voltage level and described second soft decision read voltage level Then may refer to the soft decision read voltage level of the voltage's distribiuting state current corresponding to the first memory element Soft decision read voltage level (such as, the soft decision read voltage in Figure 11 that in group, any two is adjacent Level VRead-1With VRead-2).Or, in another exemplary embodiment, described first soft decision reads electricity Voltage level may also mean that corresponding to the first memory element current with described second soft decision read voltage level Voltage's distribiuting state soft decision read voltage level group in arbitrary two non-conterminous soft decisions read Voltage level (such as, the soft decision read voltage level V in Figure 11Read-2With VRead-3)。
Refer to back Figure 10, knowable to the exemplary embodiment of Figure 10, corresponding to the first kind solution of certain a line Coded program or the Equations of The Second Kind decoding program corresponding to certain string all may success or failures.Perform each time First kind decoding program is the most independent, and the Equations of The Second Kind decoding program performed each time is also respective Independent.Such as, for the possible success or failure of first kind decoding program of sub-coding unit 1020 (1), And the first kind decoding program for sub-coding unit 1020 (2) is likely to success or failure, both may Unrelated.Therefore, even for the decoding program failure of some coding unit, but the most still may deposit At the row, column being successfully decoded or bit.
In an exemplary embodiment, during performing decoding program, be partly successfully decoded (or, more The bit value on position just) can be considered to be correct bit value and be recorded.Such as, exist In first soft decision decoding program, if some row or column is decoded successfully, then in this row or column each The bit value of position can be recorded.Thereafter, if the first soft decision decoding program failure, then holding Before row the second soft decision decoding program, the second soft decision that memory management circuitry 702 can will be obtained At least one bit in coding unit be set as the first soft decision decoding program previously (or, hard decision Decoding program) in determine at least one bit value of (or, corrigendum).Such as, in the exemplary embodiment of Figure 10, The decoding assuming the coding unit 1010 for being obtained is failed but decoded result presentation code unit Bit b in 101011Correct, then bit b11Bit value can be recorded.In follow-up adjustment Read voltage level reads in same pen data and the decoding next time that performs the data that read out, Bit b on same position in the coding unit read out11Can be directly corrected as previously being remembered The bit value of record.In other words, in the mistake performing corresponding decoding program according to different read voltage level Cheng Zhong, is successfully decoded in part decoding program the most previously in the coding unit obtained each time Bit can little by little be determined (such as, being corrected).Such as, in the exemplary embodiment of Figure 11, Use soft decision read voltage level V one by oneRead-12～VRead-18In a part of soft decision read voltage electricity Put down after reading soft decision coding unit and performing corresponding soft decision decoding program, though performed Soft decision decoding program or failure, but real in soft decision decoding program next time need to be decoded The number of bit (bit i.e., not also being successfully decoded) can gradually decrease.Whereby, ensuing soft Being decoded into power and can gradually promote of decision-making decoding program.Additionally, the present invention is not limiting as transmitting The kind of the extra decoded information gone down, any can pass to the solution that decoding program next time uses Code information can be recorded and be used in upper decoding program once.
In an exemplary embodiment, at least part of bit being successfully decoded out in hard decision decoding program Can also be used in subsequent execution soft decision decoding program (such as, the first soft decision decoding program and/ Or the second soft decision decoding program) in.Relevant application mode is specified in, does not repeats at this.Borrow This, even if the front hard decision decoding program performed several times and soft decision decoding program are all failed, but this loses Follow-up decoding program still can be made help by the decoding program lost.
It is noted that in an exemplary embodiment, use hard decision read voltage level to be obtained The size of data of hard decision coding unit is to be obtained with the follow-up soft decision read voltage level of use each time The size of data of the soft decision coding unit obtained is equal.Therefore, in above-mentioned exemplary embodiment, in order to temporarily Deposit hard decision coding unit to be not required to because of hard from performing with the size in the working area of soft decision coding unit Decision-making decoding program switches to execution soft decision decoding program to strengthen.Additionally, in above-mentioned exemplary embodiment In, the algorithm that soft decision decoding program is used/decoding rule is same or similar in hard decision decoding program The algorithm used/decoding rule, do not repeat at this to repeat.
Figure 12 is the flow chart of the coding/decoding method shown by one example of the present invention embodiment.
Refer to Figure 12, in step S1201, receive a reading instruction.In step S1202, root Multiple deposit according to what a hard decision read voltage level read in reproducible nonvolatile memorizer module Storage unit (such as, the first memory element) is to obtain hard decision coding unit.This hard decision coding unit belongs to Block code.In step S1203, described hard decision coding unit is performed hard decision decoding program.In step In rapid S1204, it is judged that hard decision decoding program is the most successful.If the success of hard decision decoding program, in step In S1205, the data (that is, the hard decision coding unit of successfully decoded) of output successfully decoded.If hard decision Decoding program unsuccessful (that is, failure), in step S1206, comes with a soft decision read voltage level Read described memory element (such as, the first memory element) to obtain a soft decision coding unit.This soft decision Coding unit falls within block code.In step S1207, described soft decision coding unit is performed soft decision Decoding program.In step S1208, it is judged that performed soft decision decoding program is the most successful.If being held The soft decision decoding program success of row, performs step S1205.If performed soft decision decoding program does not becomes Merit (that is, failure), in step S1209, it is judged that whether decode the number of times of failed soft decision decoding program More than a preset times.If the number of times decoding failed soft decision decoding program is not above this preset times (the soft decision read voltage level that i.e., also can use), in step S1210, changes soft decision and reads Power taking voltage level, and step S1206 can according to change after soft decision read voltage level and be repeated to hold OK.Such as, in step S1210, if soft decision read voltage level is by from previously in step S1206 The second soft decision that first soft decision read voltage level of middle use is adjusted to magnitude of voltage greater or lesser is read Power taking voltage level, then in step S1206 of subsequent execution, the second soft decision read voltage level can by with Again read off described memory element (such as, the first memory element).If additionally, the soft decision that decoding is failed The number of times of decoding program has exceeded this preset times (that is, all soft decision read voltage level be used), Then in step S1211, perform a predetermined registration operation.Such as, this predetermined registration operation can include that transmitting a reading loses The information that loses is to host computer system and/or the error handler performing other etc..
It is noted that in the exemplary embodiment of Figure 12, all soft decisions that can use read electricity Voltage level is that the extent of deterioration according to the memory element (such as, the first memory element) to be read determines (example As, by tabling look-up or algorithm computing).The soft decision read voltage level that each can use can be one Rise and determine or need not determine by then inborn ability.
But, in Figure 12, each step has described in detail as above, just repeats no more at this.It should be noted that In Figure 12, each step can be implemented as multiple procedure code or circuit, and the present invention is not any limitation as.Additionally, The method of Figure 12 example above embodiment of can arranging in pairs or groups uses, it is also possible to being used alone, the present invention is the most in addition Limit.
In sum, the present invention can use the first soft decision to read according to the extent of deterioration of memory element Voltage level and the second soft decision read voltage level read the first soft decision coding belonging to block code respectively Unit and the second soft decision coding unit, and perform the soft decision decoding program of correspondence respectively.Whereby, The decoding efficiency for block code can be improved.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it, Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.

Claims (25)

1. a coding/decoding method, for a reproducible nonvolatile memorizer module, described duplicative Non-volatile memory module includes multiple memory element, it is characterised in that described coding/decoding method includes:
An extent of deterioration according to the first memory element multiple in those memory element determine one first soft certainly Plan read voltage level and one second soft decision read voltage level, wherein said first soft decision reads electricity Between voltage level and described second soft decision read voltage level, there is a difference；
Those first memory element are read to obtain one first with described first soft decision read voltage level Soft decision coding unit, wherein said first soft decision coding unit belongs to a block code；
Described first soft decision coding unit is performed one first soft decision decoding program；
If described first soft decision decoding program failure, read with described second soft decision read voltage level Taking those first memory element to obtain one second soft decision coding unit, wherein said second soft decision is compiled Code unit belongs to described block code；And
Described second soft decision coding unit is performed one second soft decision decoding program.
Coding/decoding method the most according to claim 1, it is characterised in that also include:
Receive a reading instruction and read those the first memory element with a hard decision read voltage level To obtain a hard decision coding unit, wherein said hard decision coding unit belongs to described block code；And
Described hard decision coding unit is performed a hard decision decoding program,
The step wherein reading those the first memory element with described first soft decision read voltage level is Perform after the failure of described hard decision decoding program.
Coding/decoding method the most according to claim 1, it is characterised in that also include:
Before performing described second soft decision decoding program, by described second soft decision coding unit At least one bit is set as in described first soft decision decoding program the bit value of corrigendum.
Coding/decoding method the most according to claim 1, it is characterised in that single according to those first storages The described extent of deterioration of unit determines that described first soft decision read voltage level is read with described second soft decision The step of power taking voltage level includes:
Obtaining a voltage's distribiuting state of those the first memory element, wherein said voltage's distribiuting state is at least Including one first state and one second state；And
According to the gap width between described first state and described second state or described first state with One overlapping degree of described second state determines described first soft decision read voltage level and described second Soft decision read voltage level.
Coding/decoding method the most according to claim 4, it is characterised in that described first soft decision reads Described difference between voltage level and described second soft decision read voltage level is that negative is about described Described overlapping degree between one state and described second state.
Coding/decoding method the most according to claim 4, it is characterised in that described first soft decision reads Described difference between voltage level and described second soft decision read voltage level is to be positively correlated with described Described gap width between first state and described second state.
Coding/decoding method the most according to claim 1, it is characterised in that described first soft decision reads Described difference between voltage level and described second soft decision read voltage level be negative about those The described extent of deterioration of one memory element,
Wherein determine that described first soft decision reads according to the described extent of deterioration of those the first memory element Voltage level includes with the step of described second soft decision read voltage level:
A reading times according to those the first memory element, a write number of times of those the first memory element, One erasing times of those the first memory element and a bit error rate of those the first memory element are at least One of them, determine described first soft decision read voltage level and described second soft decision read voltage Level.
Coding/decoding method the most according to claim 1, it is characterised in that described first soft decision reads Voltage level is corresponding to those the first storages with one of them of described second soft decision read voltage level The optimal read voltage level of the one of unit,
Wherein determine that described first soft decision reads according to the described extent of deterioration of those the first memory element Voltage level includes with the step of described second soft decision read voltage level:
Perform an optimal read voltage level tracing program to determine described optimal read voltage level.
Coding/decoding method the most according to claim 1, it is characterised in that described block code is by many height Coding unit forms, and the predetermined bit in this little coding unit is to be determined by multiple encoding procedures.
Coding/decoding method the most according to claim 9, it is characterised in that wherein those encoding procedures tool There is different coding directions.
11. 1 kinds of memory storage apparatus, it is characterised in that including:
One connects interface unit, is electrically connected to a host computer system；
One reproducible nonvolatile memorizer module, including multiple memory element；And
One memorizer control circuit unit, is electrically connected to described connection interface unit and described duplicative Non-volatile memory module,
Wherein said memorizer control circuit unit is in order to single according to the first storages multiple in those memory element One extent of deterioration of unit determines one first soft decision read voltage level and one second soft decision read voltage Level, wherein said first soft decision read voltage level and described second soft decision read voltage level it Between there is a difference,
Wherein said memorizer control circuit unit also in order to send one first soft decision read job sequence, Wherein said first soft decision reads job sequence in order to indicate with described first soft decision read voltage level Read those first memory element to obtain one first soft decision coding unit, wherein said first soft certainly Plan coding unit belongs to a block code,
Wherein said memorizer control circuit unit is also in order to perform one to described first soft decision coding unit First soft decision decoding program,
If the most described first soft decision decoding program failure, described memorizer control circuit unit also in order to Sending one second soft decision and read job sequence, wherein said second soft decision reads job sequence in order to refer to Show with described second soft decision read voltage level soft to obtain one second to read those first memory element Decision-making coding unit,
Wherein said memorizer control circuit unit is also in order to perform one to described second soft decision coding unit Second soft decision decoding program.
12. memory storage apparatus according to claim 11, it is characterised in that described memorizer Control circuit unit is also in order to receive a reading instruction and to send a hard decision reading job sequence, wherein Described hard decision read job sequence in order to indicate with a hard decision read voltage level to read those first Memory element is to obtain a hard decision coding unit, and wherein said hard decision coding unit belongs to described block Code,
Wherein said memorizer control circuit unit is also in order to firmly to determine to described hard decision coding unit execution one Plan decoding program,
Wherein said memorizer control circuit unit sends described first soft decision and reads the operation of job sequence It is to perform after the failure of described hard decision decoding program.
13. memory storage apparatus according to claim 11, it is characterised in that described in performing Before second soft decision decoding program, described memorizer control circuit unit also in order to by described second soft certainly At least one bit in plan coding unit is set as in described first soft decision decoding program the bit of corrigendum Value.
14. memory storage apparatus according to claim 11, it is characterised in that described memorizer Control circuit unit determines described first soft decision according to the described extent of deterioration of those the first memory element Read voltage level includes with the operation of described second soft decision read voltage level:
Obtaining a voltage's distribiuting state of those the first memory element, wherein said voltage's distribiuting state includes One first state and one second state；And
According to the gap width between described first state and described second state or described first state with One overlapping degree of described second state determines described first soft decision read voltage level and described second Soft decision read voltage level.
15. memory storage apparatus according to claim 14, it is characterised in that described first soft Described difference between decision-making read voltage level and described second soft decision read voltage level is negative correlation Described overlapping degree between described first state and described second state.
16. memory storage apparatus according to claim 14, it is characterised in that described first soft Described difference between decision-making read voltage level and described second soft decision read voltage level is positive correlation Described gap width between described first state and described second state.
17. memory storage apparatus according to claim 11, it is characterised in that described first soft Described difference between decision-making read voltage level and described second soft decision read voltage level is negative correlation In the described extent of deterioration of those the first memory element,
Wherein said memorizer control circuit unit comes according to the described extent of deterioration of those the first memory element Determine the operation bag of described first soft decision read voltage level and described second soft decision read voltage level Include:
A reading times according to those the first memory element, a write number of times of those the first memory element, One erasing times of those the first memory element and a bit error rate of those the first memory element are at least One of them, determine described first soft decision read voltage level and described second soft decision read voltage Level.
18. memory storage apparatus according to claim 11, it is characterised in that described first soft Decision-making read voltage level is corresponding to those with one of them of described second soft decision read voltage level The optimal read voltage level of the one of first memory element,
Wherein said memorizer control circuit unit comes according to the described extent of deterioration of those the first memory element Determine the operation bag of described first soft decision read voltage level and described second soft decision read voltage level Include:
Perform an optimal read voltage level tracing program to determine described optimal read voltage level.
19. memory storage apparatus according to claim 11, it is characterised in that described block code Being made up of many sub-coding units, the predetermined bit in this little coding unit is by multiple encoding procedures Determine.
20. memory storage apparatus according to claim 19, it is characterised in that wherein those are compiled Coded program has different coding directions.
21. 1 kinds of memorizer control circuit unit, for controlling a type nonvolatile mould Block, wherein said reproducible nonvolatile memorizer module includes multiple memory element, it is characterised in that Described memorizer control circuit unit includes:
One HPI, is electrically connected to a host computer system；
One memory interface, is electrically connected to described reproducible nonvolatile memorizer module；
One error checking and correcting circuit；And
One memory management circuitry, is electrically connected to described HPI, described memory interface and described Error checking and correcting circuit,
Wherein said memory management circuitry is in order to according to the first memory element multiple in those memory element One extent of deterioration determines one first soft decision read voltage level and one second soft decision read voltage electricity Flat, between wherein said first soft decision read voltage level and described second soft decision read voltage level There is a difference,
Wherein said memory management circuitry is also in order to send one first soft decision reading job sequence, wherein Described first soft decision reads job sequence and reads with described first soft decision read voltage level in order to indicate Taking those first memory element to obtain one first soft decision coding unit, wherein said first soft decision is compiled Code unit belongs to a block code,
Wherein said error checking and correcting circuit in order to perform one the to described first soft decision coding unit One soft decision decoding program,
If the most described first soft decision decoding program failure, described memory management circuitry is also in order to send One second soft decision read job sequence, wherein said second soft decision read job sequence in order to indicate with Described second soft decision read voltage level reads those first memory element to obtain one second soft decision Coding unit, wherein said second soft decision coding unit belongs to described block code,
Wherein said error checking and correcting circuit are also in order to perform one to described second soft decision coding unit Second soft decision decoding program.
22. memorizer control circuit unit according to claim 21, it is characterised in that described in deposit Reservoir management circuit determines described first soft decision according to the described extent of deterioration of those the first memory element Read voltage level includes with the operation of described second soft decision read voltage level:
Obtaining a voltage's distribiuting state of those the first memory element, wherein said voltage's distribiuting state includes One first state and one second state；And
According to the gap width between described first state and described second state or described first state with One overlapping degree of described second state determines described first soft decision read voltage level and described second Soft decision read voltage level.
23. memorizer control circuit unit according to claim 22, it is characterised in that described Described difference between one soft decision read voltage level and described second soft decision read voltage level is negative It is relevant to the described overlapping degree between described first state and described second state.
24. memorizer control circuit unit according to claim 22, it is characterised in that described Described difference between one soft decision read voltage level and described second soft decision read voltage level is just It is relevant to the described gap width between described first state and described second state.
25. memorizer control circuit unit according to claim 21, it is characterised in that described One of them of one soft decision read voltage level and described second soft decision read voltage level be corresponding to The optimal read voltage level of the one of those the first memory element,
Wherein said memory management circuitry determines according to the described extent of deterioration of those the first memory element Described first soft decision read voltage level includes with the operation of described second soft decision read voltage level:
Perform an optimal read voltage level tracing program to determine described optimal read voltage level.
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