CN106681856A - Decoding method, storage storing device and storage control circuit unit - Google Patents

Decoding method, storage storing device and storage control circuit unit Download PDF

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Publication number
CN106681856A
CN106681856A CN201610711090.4A CN201610711090A CN106681856A CN 106681856 A CN106681856 A CN 106681856A CN 201610711090 A CN201610711090 A CN 201610711090A CN 106681856 A CN106681856 A CN 106681856A
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China
Prior art keywords
decoding
data
condition
bit
error
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Granted
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CN201610711090.4A
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Chinese (zh)
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CN106681856B (en
Inventor
林玉祥
严绍维
杨政哲
赖国欣
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Hefei Core Electronics Co Ltd
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Hefei Core Electronics Co Ltd
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Priority to CN201610711090.4A priority Critical patent/CN106681856B/en
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Abstract

The invention provides a decoding method, a storage storing device and a storage control circuit unit. The decoding method comprises the steps that first data is read from multiple first storing units of a rewritable nonvolatile storage module; a first decoding operation is executed on the first data on the basis of first decoding conditions; if the first decoding operation accords with a first preset state, a second decoding operation is executed on the first data on the basis of second decoding conditions, wherein the preciseness obtained when error bits in the first data are positioned on the basis of the second decoding conditions is higher than that obtained when the error bits in the first data are positioned on the basis of the first decoding conditions. Accordingly, the decoding efficiency of the storage storing device can be improved.

Description

Coding/decoding method, memory storage apparatus and memorizer control circuit unit
Technical field
The invention relates to a kind of decoding technique, and in particular to a kind of coding/decoding method, memory storage apparatus And memorizer control circuit unit.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that consumer is to storage The demand of medium also rapidly increases.Because rewritable nonvolatile memory module (for example, fast storage) has data non- Volatibility, power saving, small volume, and the characteristic such as mechanical structure, thus be especially suitable for being built into it is above-mentioned it is illustrated it is various just In taking formula multimedia device.
In general, one or more decoding mechanism are had in storage arrangement meeting, it reads to correct from storage arrangement The mistake that may have in the data for taking.For example, this decodes mechanism and potentially includes bit reversal (Bit-Flipping) calculation The decoding algorithms such as method, minimum-sum total (Min-Sum) algorithm and summation-product (Sum-Product) algorithm.In storage When device device dispatches from the factory, the built-in decoding algorithm of storage arrangement can be configured with optimized operating parameter.But, with The use time and/or usage frequency of storage arrangement increases, and the channel status of storage arrangement also can change.If depositing The channel status of reservoir device changes too greatly, also tends to cause the decoding of storage arrangement even with optimized operating parameter Efficiency is low.
The content of the invention
The present invention provides a kind of coding/decoding method, memory storage apparatus and memorizer control circuit unit, can lift storage The decoding efficiency of device storage device.
One example of the present invention embodiment provides a kind of coding/decoding method, and it is used to include the rewritable non-of multiple memory cell Volatile, the coding/decoding method includes：Multiple first memory cell from the plurality of memory cell read First data；First decoding operate is performed to first data based on the first decoding condition；And if the first decoding behaviour Work meets the first preset state, the second decoding operate is performed to first data based on the second decoding condition, wherein based on institute The rigor for stating the error bit in the second decoding condition positioning first data is higher than fixed based on the first decoding condition The rigor of the error bit in first data of position.
In one example of the present invention embodiment, the coding/decoding method also includes：If first decoding operate meets First data are performed the 3rd decoding operate by two preset states based on the 3rd decoding condition, wherein based on the described 3rd solution Code-bar part positions the rigor of the error bit in first data less than based on the described first decoding condition positioning institute State the rigor of the error bit in the first data.
In one example of the present invention embodiment, described coding/decoding method also includes：If the first decoding condition meets Stage conditions, count the iteration count value of first decoding operate；And if the iteration count value coincidence counting condition, sentence Fixed first decoding operate meets first preset state.
In one example of the present invention embodiment, described coding/decoding method also includes：If the first decoding condition is not inconsistent The sum for closing the bit that the stage conditions and first decoding operate are overturn meets number condition, judges first solution Code operation meets second preset state.
In one example of the present invention embodiment, described coding/decoding method also includes：From first candidate's count condition and The count condition is selected in two candidate's count conditions, wherein the first candidate count condition corresponds to the first count value, institute Second candidate's count condition is stated corresponding to the second count value, and first count value is different from second count value.
In one example of the present invention embodiment, described coding/decoding method also includes：From the first candidate solution code-bar part and The second decoding condition is selected in two candidate solution code-bar parts, wherein based in the first candidate solution code-bar part location data The rigor of error bit is tight higher than the error bit positioned based on the second candidate solution code-bar part in the data Careful degree.
In one example of the present invention embodiment, described coding/decoding method also includes：Odd even is performed to first data Inspection operation is summed up with the syndrome for obtaining first data；If the syndrome sum total is less than preset value, by described first The error weight value of the bit in data is reduced to the second error weight value from the first error weight value；And if described second wrong By mistake weighted value overturns the ratio more than the upset threshold value corresponding to the described first decoding condition in first decoding operate It is special.
Another example of the present invention embodiment provides a kind of memory storage apparatus, and it includes connecting interface unit, can weigh Write non-volatile memory module and memorizer control circuit unit.The connecting interface unit is to be connected to host computer system. The rewritable nonvolatile memory module includes multiple memory cell.The memorizer control circuit unit is connected to described Connecting interface unit and the rewritable nonvolatile memory module, the memorizer control circuit unit is to send reading Command sequence, wherein the command sequence that reads indicates that multiple first memory cell from the plurality of memory cell read the One data, the memorizer control circuit unit is also decoded to perform first to first data based on the first decoding condition Operation, if first decoding operate meets the first preset state, the memorizer control circuit unit is also to based on second Decoding condition performs the second decoding operate to first data, wherein based on the described second decoding condition positioning first number The rigor of the error bit according in is higher than the mistake ratio positioned based on the described first decoding condition in first data Special rigor.
In one example of the present invention embodiment, if first decoding operate meets the second preset state, the storage Device control circuit unit also performs the 3rd decoding operate to decode condition based on the 3rd to first data, wherein based on institute The rigor for stating the error bit in the 3rd decoding condition positioning first data solves code-bar less than based on described first Part positions the rigor of the error bit in first data.
In one example of the present invention embodiment, if the first decoding condition meets stage conditions, the memory control Circuit unit processed also to count the iteration count value of first decoding operate, if the iteration count value coincidence counting bar Part, the memorizer control circuit unit judges that first decoding operate meets first preset state.
In one example of the present invention embodiment, if the first decoding condition does not meet the stage conditions and described The sum of the bit that one decoding operate is overturn meets number condition, and the memorizer control circuit unit judges first solution Code operation meets second preset state.
In one example of the present invention embodiment, the memorizer control circuit unit from the first candidate also to count bar The count condition is selected in part and second candidate's count condition, wherein the first candidate count condition is counted corresponding to first Value, the second candidate count condition corresponds to the second count value, and first count value is counted different from described second Value.
In one example of the present invention embodiment, the memorizer control circuit unit is also to from the first candidate solution code-bar The second decoding condition is selected in part and the second candidate solution code-bar part, wherein positioning number based on the first candidate solution code-bar part The rigor of the error bit according in is higher than the mistake ratio positioned based on the second candidate solution code-bar part in the data Special rigor.
In one example of the present invention embodiment, the memorizer control circuit unit to first data also to hold Row odd-even check operates the syndrome to obtain first data to sum up, described if syndrome sum total is less than preset value Memorizer control circuit unit is also the error weight value of the bit in first data to be subtracted from the first error weight value It is less the second error weight value, if the second error weight value is more than the upset threshold corresponding to the described first decoding condition Value, the memorizer control circuit unit in first decoding operate also to overturn the bit.
Another example of the present invention embodiment provides a kind of memorizer control circuit unit, and it includes multiple depositing to control The rewritable nonvolatile memory module of storage unit, the memorizer control circuit unit includes that HPI, memory connect Mouth, error checking and correcting circuit and memory management circuitry.The HPI is to be connected to host computer system.The storage Device interface is to be connected to the rewritable nonvolatile memory module.The memory management circuitry is connected to the main frame Interface, the memory interface and the error checking and correcting circuit, the memory management circuitry refers to send reading Sequence is made, wherein described read multiple first memory cell reading first that command sequence is indicated from the plurality of memory cell Data, the error checking is with correcting circuit first data are performed with the first decoding behaviour based on the first decoding condition Make, if first decoding operate meets the first preset state, the error checking is with correcting circuit also to based on the second solution Code-bar part performs the second decoding operate to first data, wherein the error checking is solved with correcting circuit based on described second The rigor of the error bit in code-bar part positioning first data is higher than the error checking and correcting circuit based on described First decoding condition positions the rigor of the error bit in first data.
In one example of the present invention embodiment, if first decoding operate meets the second preset state, the mistake Check with correcting circuit also to perform the 3rd decoding operate to first data based on the 3rd decoding condition, wherein the mistake Flase drop looks into the rigor of the error bit positioned based on the 3rd decoding condition with correcting circuit in first data The mistake ratio in first data is positioned based on the described first decoding condition less than the error checking and correcting circuit The special rigor.
In one example of the present invention embodiment, if the first decoding condition meets stage conditions, the memory pipe Reason circuit also to count the iteration count value of first decoding operate, if the iteration count value coincidence counting condition, institute State memory management circuitry and judge that first decoding operate meets first preset state.
In one example of the present invention embodiment, if the first decoding condition does not meet the stage conditions and described The sum of the bit that one decoding operate is overturn meets number condition, and the memory management circuitry judges the first decoding behaviour Work meets second preset state.
In one example of the present invention embodiment, the memory management circuitry also to from first candidate's count condition with The count condition is selected in second candidate's count condition, wherein the first candidate count condition corresponds to the first count value, The second candidate count condition corresponds to the second count value, and first count value is different from second count value.
In one example of the present invention embodiment, the memory management circuitry also to from the first candidate solution code-bar part with The second decoding condition is selected in second candidate solution code-bar part, wherein the error checking is based on described first with correcting circuit The rigor of the error bit in candidate solution code-bar part location data is higher than the error checking and correcting circuit based on described the Two candidate solution code-bar parts position the rigor of the error bit in the data.
In one example of the present invention embodiment, the error checking is with correcting circuit also to hold to first data Row odd-even check operates the syndrome to obtain first data to sum up, described if syndrome sum total is less than preset value Error checking is with correcting circuit also the error weight value of the bit in first data to be subtracted from the first error weight value It is less the second error weight value, if the second error weight value is more than the upset threshold corresponding to the described first decoding condition Value, the error checking is with correcting circuit also to overturn the bit in first decoding operate.
Based on above-mentioned, after the first decoding operate meets the first preset state, the solution code-bar that decoding algorithm is adopted Part can be updated to more scrupulously position the error bit in data to be decoded, cannot so as to lift decoding operate experience mistake The treatment effeciency of convergence situation.
It is that the features described above and advantage of the present invention can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make Carefully it is described as follows.
Description of the drawings
Fig. 1 is host computer system shown by an exemplary embodiment of the invention, memory storage apparatus and input/defeated Go out the schematic diagram of (I/O) device.
Fig. 2 is host computer system shown by another exemplary embodiment of the invention, memory storage apparatus and I/O dress The schematic diagram put.
Fig. 3 is the signal of the host computer system shown by another exemplary embodiment of the invention and memory storage apparatus Figure.
Fig. 4 is the schematic block diagram of the memory storage apparatus shown by an exemplary embodiment of the invention.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment of the invention.
Fig. 6 is the schematic diagram of the parity check matrix shown by an exemplary embodiment of the invention.
Fig. 7 is the schematic diagram of the critical voltage distribution of the memory cell shown by an exemplary embodiment of the invention.
Fig. 8 is that the switch step in an iterative decoding operation shown by an exemplary embodiment of the invention is shown It is intended to.
Fig. 9 A are the schematic diagrames of the switch step shown by an exemplary embodiment of the invention.
Fig. 9 B are the schematic diagrames of the switch step shown by another exemplary embodiment of the invention.
Fig. 9 C are the schematic diagrames of the switch step shown by another exemplary embodiment of the invention.
Figure 10 is the schematic diagram of the odd-even check operation shown by an exemplary embodiment of the invention.
Figure 11 is the flow chart of the coding/decoding method shown by an exemplary embodiment of the invention.
Figure 12 is the flow chart of the coding/decoding method shown by another exemplary embodiment of the invention.
Drawing reference numeral explanation：
10、30：Memory storage apparatus；
11、31：Host computer system；
110：System bus；
111：Processor；
112：Random access memory；
113：Read-only storage；
114：Data transmission interface；
12：Input/output (I/O) device；
20：Motherboard；
201：USB flash disk；
202：RAM card；
203：Solid state hard disc；
204：Radio memory storage device；
205：GPS module；
206：NIC；
207：Radio transmitting device；
208：Keyboard；
209：Screen；
210：Loudspeaker；
32：SD card；
33：CF cards；
34：Embedded storage device；
341：Embedded multi-media card；
342：Embedded type multi-core piece sealed storage device；
402：Connecting interface unit；
404：Memorizer control circuit unit；
406：Rewritable nonvolatile memory module；
502：Memory management circuitry；
504：HPI；
506：Memory interface；
508：Error checking and correcting circuit；
510：Buffer storage；
512：Electric power management circuit；
600、1000：Parity check matrix；
710、720：State；
701：Read voltage；
730：Overlapping region；
1001：Code word；
1002：Verification vector；
S1101：Step (reads the first data) from multiple first memory cell of rewritable nonvolatile memory module；
S1102：Step (performs the first decoding operate) based on the first decoding condition to the first data；
S1103：Step (judges whether the first decoding operate meets the first preset state)；
S1104：Step (performs the second decoding operate) based on the second decoding condition to the first data；
S1105：Step (judges whether the first decoding operate meets the second preset state)；
S1106：Step (performs the 3rd decoding operate) based on the 3rd decoding condition to the first data；
S1201：Step (reads the first data) from multiple first memory cell of rewritable nonvolatile memory module；
S1202：Step (the first data are performed with odd-even check operates the syndrome to obtain the first data to sum up)；
S1203：Whether step (judges syndrome sum total less than preset value)；
S1204：The error weight value of each bit in the first data (is reduced to second wrong by step from the first error weight value Miss weighted value)；
S1205：Step (is operated) based on a decoding condition to the first data perform decoding；
S1206：Step (judges whether decoding operate meets the first preset state)；
S1207：Decoding condition (is updated to the second decoding condition) by step；
S1208：Step (judges whether decoding operate meets the second preset state)；
S1209：Decoding condition (is updated to the 3rd decoding condition) by step.
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) include rewritable nonvolatile memory Module (rewritable non-volatile memory module) and controller (also referred to as, control circuit).It is commonly stored device Storage device is used together with host computer system, so that host computer system can be write data into memory storage apparatus or from storage Data are read in device storage device.
Fig. 1 is host computer system shown by an exemplary embodiment of the invention, memory storage apparatus and input/defeated Go out the schematic diagram of (I/O) device.Fig. 2 is that host computer system shown by another exemplary embodiment of the invention, memory are deposited The schematic diagram of storage device and I/O devices.Fig. 1 and Fig. 2 is refer to, host computer system 11 generally comprises processor 111, arbitrary access and deposits Reservoir (random access memory, RAM) 112, read-only storage (read only memory, ROM) 113 and data are passed Defeated interface 114.Processor 111, random access memory 112, read-only storage 113 and data transmission interface 114 are all connected to System bus (system bus) 110.
In this exemplary embodiment, host computer system 11 is connected with memory storage apparatus 10 by data transmission interface 114 Connect.For example, host computer system 11 can pass through data transmission interface 114 by data storage to memory storage apparatus 10 or from memory Data are read in storage device 10.Additionally, host computer system 11 is connected with I/O devices 12 by system bus 110.For example, it is main Output signal can be sent to I/O devices 12 or from the receives input signal of I/O devices 12 by machine system 11 by system bus 110.
In this exemplary embodiment, processor 111, random access memory 112, read-only storage 113 and data transfer Interface 114 may be provided on the motherboard 20 of host computer system 11.The number of data transmission interface 114 can be one or more.It is logical Data transmission interface 114 is crossed, motherboard 20 can be connected to memory storage apparatus 10 by wired or wireless way.Memory Storage device 10 can be for example USB flash disk 201, RAM card 202, solid state hard disc (Solid State Drive, SSD) 203 or wirelessly deposit Reservoir storage device 204.Radio memory storage device 204 can be for example close range wireless communication (Near Field Communication, NFC) memory storage apparatus, Wireless Fidelity (WiFi) memory storage apparatus, bluetooth (Bluetooth) Memory storage apparatus or low-power consumption bluetooth memory storage apparatus (for example, iBeacon) etc. are with various wireless communication technique The memory storage apparatus on basis.Additionally, motherboard 20 can also be connected to global positioning system by system bus 110 (Global Positioning System, GPS) module 205, NIC 206, radio transmitting device 207, keyboard 208, The various I/O devices such as screen 209, loudspeaker 210.For example, in an exemplary embodiment, motherboard 20 can pass through radio transmitting device 207 access wireless memory storage apparatus 204.
In an exemplary embodiment, mentioned host computer system is substantially to coordinate to store with memory storage apparatus Any system of data.Although in above-mentioned exemplary embodiment, host computer system is explained with computer system, however, Fig. 3 is The schematic diagram of host computer system and memory storage apparatus shown by another exemplary embodiment of the invention.Refer to Fig. 3, In another exemplary embodiment, host computer system 31 can also be digital camera, video camera, communication device, audio player, video The system such as player or panel computer, and the secure digital (Secure that memory storage apparatus 30 can be used for it Digital, SD) card 32, that small-sized quick (Compact Flash, CF) blocks 33 or embedded storage devices 34 etc. is various non-volatile Property memory storage apparatus.Embedded storage device 34 includes embedded multi-media card (embedded Multi Media Card, eMMC) 341 and/or embedded type multi-core piece encapsulation (embedded Multi Chip Package, eMCP) storage device The all types of embedded storage devices being directly connected in memory module on the substrate of host computer system such as 342.
Fig. 4 is the schematic block diagram of the memory storage apparatus shown by an exemplary embodiment of the invention.Please join According to Fig. 4, memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 and rewritable non-volatile Property memory module 406.
In this exemplary embodiment, connecting interface unit 402 is to be compatible to sequence advanced annex (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not restricted to this, connecting interface unit 402 can also meet advanced annex (Parallel Advanced Technology Attachment, PATA) mark side by side Accurate, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, USB (Universal Serial Bus, USB) standard, SD interface standard, ultrahigh speed A generation (Ultra High Speed-I, UHS-I) interface standard, the generation of ultrahigh speed two (Ultra High Speed-II, UHS-II) Interface standard, memory stick (Memory Stick, MS) interface standard, MCP interface standards, MMC interface standards, eMMC interface marks Accurate, general fast storage (Universal Flash Storage, UFS) interface standard, eMCP interface standards, CF interface marks Accurate, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards. Connecting interface unit 402 can be encapsulated in a chip with memorizer control circuit unit 404, or connecting interface unit 402 It is to be laid in outside a chip comprising memorizer control circuit unit 404.
Memorizer control circuit unit 404 is to perform with multiple gates or control instruction of hardware or software implementation simultaneously And the write of data is carried out in rewritable nonvolatile memory module 406 according to the instruction of host computer system 11, is read and is smeared Operate except waiting.
Rewritable nonvolatile memory module 406 is to be connected to memorizer control circuit unit 404 and to store The data that host computer system 11 is write.Rewritable nonvolatile memory module 406 can be single-order memory cell (Single Level Cell, SLC) NAND flash memory module (that is, can store the quick storage of 1 bit in one memory cell Device module), (that is, one storage is single for multi-level cell memory (Multi Level Cell, MLC) NAND flash memory module The flash memory module of 2 bits can be stored in unit), Complex Order memory cell (Triple Level Cell, TLC) NAND Type flash memory module (that is, the flash memory module of 3 bits can be stored in one memory cell), other quick storages Device module or other there is the memory module of identical characteristics.
In this exemplary embodiment, the memory cell of rewritable nonvolatile memory module 406 can constitute multiple entities Programmed cell, and this little entity program unit can constitute multiple entity erased cells.For example, in same byte line Memory cell can constitute one or more entity program units.If each memory cell can store the bit of more than 2, together Entity program unit in one byte line can at least be classified as lower entity program unit with upper entity program unit. For example, the minimum effective bit (Least Significant Bit, LSB) of a memory cell is belonging to lower entity program list Unit, and the highest significant bit (Most Significant Bit, MSB) of a memory cell is belonging to entity program list Unit.In general, in MLC NAND fast storages, the writing speed of lower entity program unit can be more than upper entity journey The writing speed of sequence unit, and/or the reliability of lower entity program unit is above the reliability of entity program unit Degree.
In this exemplary embodiment, entity program unit is the minimum unit of sequencing.That is, entity program unit is The minimum unit of write data.For example, entity program unit is physical page (page) or entity fan (sector).If real Body programmed cell is physical page, then this little entity program unit generally includes data bit area and redundancy (redundancy) bit area.Data bit area fans comprising multiple entities, and to store user's data, and redundancy ratio special zone is used With memory system data (for example, error correcting code).In this exemplary embodiment, data bit area includes 32 entity fans, and The size of one entity fan is 512 bit groups (byte, B).However, in other exemplary embodiments, data bit also may be used in area Comprising 8,16 or number more or less of entity fan, and the size of each entity fan can also be more greatly or more It is little.On the other hand, entity erased cell is the least unit erased.That is, each entity erased cell contain minimal amount it The memory cell being erased in the lump.For example, entity erased cell is physical blocks (block).
In this exemplary embodiment, each memory cell in rewritable nonvolatile memory module 406 is with electricity The change of pressure (hereinafter also referred to critical voltage) is storing one or more bits.Specifically, the control of each memory cell Grid (control gate) has an electric charge capture layer and passage between.By bestowing a write voltage to control gate, can The amount of electrons for catching layer is mended to change electric charge, and then changes the critical voltage of memory cell.This operation for changing critical voltage is also referred to as For " writing the data to memory cell " or " sequencing memory cell ".With the change of critical voltage, rewritable nonvolatile Each memory cell in memory module 406 has multiple storage states.One is may determine that by bestowing read voltage Which storage state is memory cell be belonging to, and one or more bits that this memory cell is stored are obtained whereby.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment of the invention.
Fig. 5 is refer to, memorizer control circuit unit 404 includes memory management circuitry 502, HPI 504, storage Device interface 506 and error checking and correcting circuit 508.
Memory management circuitry 502 to control memory control circuit unit 404 overall operation.Specifically, deposit Reservoir management circuit 502 has multiple control instructions, and when memory storage apparatus 10 are operated, this little control instruction can quilt The running such as perform carrying out the write of data, read and erase.When below illustrating the operation of memory management circuitry 502, equivalent In the operation of explanation memorizer control circuit unit 404.
In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with software.For example, store Device management circuit 502 has microprocessor unit (not shown) and read-only storage (not shown), and this little control instruction is In being programmed so far read-only storage.When memory storage apparatus 10 are operated, this little control instruction can be by microprocessor unit To perform carrying out the write of data, running of reading and erase etc..
In another exemplary embodiment, the control instruction of memory management circuitry 502 can also procedure code pattern be stored in (storage system data for example, are exclusively used in memory module is for the specific region of rewritable nonvolatile memory module 406 System area) in.Additionally, memory management circuitry 502 have microprocessor unit (not shown), read-only storage (not shown) and with Machine accesses memory (not shown).Particularly, this read-only storage has boot code (boot code), and when memory control When circuit unit processed 404 is enabled, microprocessor unit can first carry out this boot code and deposit will be stored in rewritable nonvolatile Control instruction in memory modules 406 is loaded into the random access memory of memory management circuitry 502.Afterwards, microprocessor Device unit can operate this little control instruction carrying out the write of data, running of reading and erase etc..
Additionally, in another exemplary embodiment, the control instruction of memory management circuitry 502 can also hardware reality Make.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write circuit, memory Reading circuit, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write circuit, memory Reading circuit, memory erase circuit and data processing circuit is to be connected to microcontroller.Storage Unit Management circuit is to manage The memory cell of reason rewritable nonvolatile memory module 406 or its group.Memory write circuit is to rewritable non- Volatile 406 assigns write instruction sequence to write data into rewritable nonvolatile memory module 406 In.Memory reading circuitry is to assign reading command sequence to rewritable nonvolatile memory module 406 with from rewritable Data are read in non-volatile memory module 406.Memory erases circuit to rewritable nonvolatile memory module 406 assign and erase command sequence data are erased from rewritable nonvolatile memory module 406.Data processing circuit is used It is intended to write to the data of rewritable nonvolatile memory module 406 and from rewritable nonvolatile memory module to process The data read in 406.Write instruction sequence, read command sequence and command sequence of erasing can distinctly include one or more programs Code or instruction code and to indicate that rewritable nonvolatile memory module 406 performs corresponding write, reads and erase Deng operation.In an exemplary embodiment, memory management circuitry 502 can also assign other kinds of command sequence to rewritable The operation corresponding to indicate execution of non-volatile memory module 406.
In this exemplary embodiment, it is rewritable non-easy to map that memory management circuitry 502 can configure multiple logical blocks Entity erased cell in the property lost memory module 406.One of logical block may refer to a logical address, one patrol Collect programmed cell, a logic erased cell or be made up of multiple continuous or discrete logical addresses.Additionally, one is patrolled Collecting unit can be mapped to one or more entity erased cells.
In this exemplary embodiment, memory management circuitry 502 can be by reflecting between logical block and entity erased cell Penetrate relation (also referred to as logic-entity mapping relations) and be recorded at least one logic-entity mapping.When host computer system 11 is intended to from depositing When reservoir storage device 10 reads data or writes data to memory storage apparatus 10, memory management circuitry 502 can basis This logic-entity mapping is performing for the data access of memory storage apparatus 10.
HPI 504 is to be connected to memory management circuitry 502 and passed with identification host computer system 11 to receive The instruction sent and data.That is, the instruction that host computer system 11 is transmitted can be sent to data by HPI 504 Memory management circuitry 502.In this exemplary embodiment, HPI 504 is to be compatible to SATA standard.However, it is necessary to understand Be to the invention is not restricted to this, HPI 504 can also be compatible to PATA standards, the standards of IEEE 1394, PCI Express standards, USB standard, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS marks Standard, CF standards, IDE standards or other suitable data transmission standards.
Memory interface 506 is to be connected to memory management circuitry 502 and to access rewritable nonvolatile storage Device module 406.That is, being intended to write to the data of rewritable nonvolatile memory module 406, memory interface can be passed through 506 are converted to the receptible form of the institute of rewritable nonvolatile memory module 406.Specifically, if memory management circuitry 502 will access rewritable nonvolatile memory module 406, and memory interface 506 can transmit corresponding command sequence.For example, These command sequences may include to indicate the write instruction sequence of write data, indicate to read the reading command sequence of data, indicate The command sequence and to indicate that, various storage operations (for example change read voltage level or execution of erasing of data of erasing Garbage collection operation etc.) command sequence.These command sequences are, for example, to be produced and passed through by memory management circuitry 502 Memory interface 506 is sent to rewritable nonvolatile memory module 406.These command sequences may include one or more letters Number, or the data in bus.Additionally, these signals or data may include instruction code or procedure code.For example, instruction is being read In sequence, the information such as identification code, the storage address of reading can be included.
Error checking and correcting circuit 508 be connected to memory management circuitry 502 and to perform error checking with Correct operation is guaranteeing the correctness of data.Specifically, write when memory management circuitry 502 is received from host computer system 11 When entering to instruct, error checking produces corresponding error correcting code with the data that correcting circuit 508 can be corresponding this write instruction (error correcting code, ECC) and/or error checking code (error detecting code, EDC), and store Device management circuit 502 can by correspondence this write instruction data and corresponding error correcting code and/or error checking code write to In rewritable nonvolatile memory module 406.Afterwards, when memory management circuitry 502 is from rewritable nonvolatile memory The corresponding error correcting code of this data and/or error checking code, and mistake inspection can be simultaneously read when data are read in module 406 Look into can be according to this error correcting code and/or error checking code to being read with correcting circuit 508 data perform error checking with Correct operation.
In an exemplary embodiment, memorizer control circuit unit 404 also includes buffer storage 510 with power management electricity Road 512.
Buffer storage 510 is connected to memory management circuitry 502 and is configured to temporarily store and comes from host computer system 11 Data and the data for instructing or coming from rewritable nonvolatile memory module 406.Electric power management circuit 512 is to be connected to deposit Reservoir manages circuit 502 and to the power supply of control memory storage device 10.
In this exemplary embodiment, error checking supports low-density parity inspection (low-density with correcting circuit 508 Parity-check, LDPC) code.For example, error checking and correcting circuit 508 can be encoded using low-density parity check code with Decoding.It is to check matrix (also referred to as parity check matrix) to define effective code with one in low-density parity check code Word.Hereinafter parity check matrix is labeled as into matrix H, and a code word is labeled as V.According to below equation (1), if odd even inspection It is null vector that matrix H is looked into being multiplied for code word V, and expression code word V is effective code word (valid codeword).Wherein computing sublist Show the matrix multiple of mould 2 (mod 2).In other words, the kernel (null space) of matrix H just contains all of effective code Word.However, the present invention is not intended to limit the content of code word V.For example, code word V can also be included with the mistake produced by any algorithm Miss more code or error checking code.
The dimension of wherein matrix H is that k- takes advantage of-n (k-by-n), and the dimension of code word V is that 1- takes advantage of-n.K and n is positive integer.Code word Information bit and parity bits, i.e. code word V are included in V can be expressed as [U P], wherein vector U is by information bit institute group Into, and vector P is made up of parity bits.The dimension of vectorial U is that 1- takes advantage of-(n-k), and the dimension of vector P is that 1- takes advantage of-k. In one code word, parity bits be for protection information bit and be considered as corresponding to information bit produce mistake more Code or error checking code.Wherein, protection information bit for example refers to the correctness for maintaining information bit.For example, when from can again Write when reading a pen data in non-volatile memory module 406, the parity bits in this data can be used to correct corresponding Mistake that may be present in data.
In an exemplary embodiment, the information bit in a code word is referred to as data bit with parity bits.For example, code There is n data bit, wherein the length of information bit is (n-k) bit, and the length of parity bits is k bits in word V. Therefore, the code check (code rate) of code word V is (n-k)/n.
In general, matrix can be produced using one when using low-density parity check code to encode (to be labeled as below G) so that for arbitrary vectorial U can meet below equation (2).The dimension for wherein producing matrix G is (n-k)-take advantage of-n.
Code word V by produced by equation (2) is effective code word.Therefore equation (2) can be substituted into equation (1), is borrowed This obtains below equation (3).
Because vectorial U can be arbitrary vector, therefore below equation (4) inherently meets.That is, determining After parity check matrix H, corresponding generation matrix G also can be determined.
When code word V is decoded, an odd-even check operation first can be performed to the data bit in code word V, for example will Parity check matrix H is multiplied to produce a vector (S being labeled as below, such as shown in below equation (5)) with code word V.If to Amount S is null vector (that is, each element in vectorial S is zero), then it represents that successfully decoded and can direct output codons V. If vector S is not null vector (that is, at least one of vectorial S elements are not zero), then it represents that have at least one in code word V wrong Miss and code word V is not effective code word.
The dimension of vectorial S is that k- takes advantage of -1.Each element in vectorial S is also referred to as syndrome (syndrome).If code word V It is not effective code word, error checking can perform a decoding operate with correcting circuit 508, to attempt correcting the mistake in code word V By mistake.
Fig. 6 is the schematic diagram of the parity check matrix shown by an exemplary embodiment of the invention.
Fig. 6 is refer to, the dimension of parity check matrix 600 is that k- takes advantage of-n.For example, k is 8, and n is 9.However, this The bright positive integer k and n of being not intended to limit is how many.Each row (row) of parity check matrix 600 also represent a restriction (constraint).By taking the first row of parity check matrix 600 as an example, if some code word is effective code word, by this code word In the 3rd, 5,8 and the 9th bits do after the addition of mould 2, bit " 0 " can be obtained.In this field, usually intellectual should be able to manage How solution is encoded with parity check matrix 600, and here is just repeated no more.Additionally, parity check matrix 600 is only an example Matrix, and be not used to limit the present invention.
When memory management circuitry 502 by multiple bit storages to rewritable nonvolatile memory module 406 when, it is wrong Flase drop is looked into can be corresponding to the k parity bits of generation per (n-k) individual bit to be stored (that is, information bit) with correcting circuit 508. Next, memory management circuitry 502 can be write to rewritable non-using this n bit (that is, data bit) as code word Volatile 406.
Fig. 7 is the schematic diagram of the critical voltage distribution of the memory cell shown by an exemplary embodiment of the invention.
Refer to Fig. 7, the critical voltage of transverse axis representative memory cell, and longitudinal axis representative memory cell number.For example, Fig. 7 It is the critical voltage distribution situation for representing each memory cell in an entity program unit.Hypothesis state 710 correspond to than Special " 1 " and state 720 corresponds to bit " 0 ", if the critical voltage of some memory cell belongs to state 710, this storage is single What unit was stored is bit " 1 "；On the contrary, when if the critical voltage of some memory cell belongs to state 720, this memory cell What is stored is bit " 0 ".It is noted that in this exemplary embodiment, the state correspondence in critical voltage distribution is extremely One bit value (that is, " 0 " or " 1 "), and the critical voltage of memory cell is distributed with two kinds of possible states.However, at it In his exemplary embodiment, each state in critical voltage distribution can also be corresponded to multiple bit values and memory cell The distribution of critical voltage has been likely to four kinds, eight kinds or other arbitrarily individual states.Additionally, the present invention does not limit each state yet Representative bit.For example, in another exemplary embodiment of Fig. 7, state 710 may correspond to bit " 0 ", and state 720 correspond to bit " 1 ".
In this exemplary embodiment, when to read data from rewritable nonvolatile memory module 406, memory pipe Reason circuit 502 can send a reading command sequence to rewritable nonvolatile memory module 406.This read command sequence to Indicate that rewritable nonvolatile memory module 406 reads data from multiple memory cell (hereinafter also referred to the first memory cell) (hereinafter also referred to the first data).In this exemplary embodiment, the first memory cell is belonging to same entity program unit. However, in another exemplary embodiment, the first memory cell can also be belonging to different entity program units.According to this reading Instruction fetch sequence, rewritable nonvolatile memory module 406 can read the first storage using the read voltage 701 in Fig. 7 Unit.If the critical voltage of certain one in the first memory cell is less than read voltage 701, this memory cell can be switched on simultaneously And memory management circuitry 502 can read bit " 1 ".If on the contrary, the critical voltage of certain one in the first memory cell is big In read voltage 701, then this memory cell will not be switched on and memory management circuitry 502 can read bit " 0 ".
In this exemplary embodiment, an overlapping region 730 is included between state 710 and state 720.Overlapping region 730 Area be positively correlated with the sum that critical voltage in the first memory cell falls within the memory cell in overlapping region 730.Overlay region Domain 730 represents that have some memory cell to be stored in the first memory cell should be bit " 1 " (belonging to state 710), but Its critical voltage is more than applied read voltage 701；Or, have what some memory cell were stored in the first memory cell Should be bit " 0 " (belonging to state 720), but its critical voltage is less than applied read voltage 701.In other words, by applying Plus in the data that read of read voltage 701, have the bit of part can be wrong.
In general, if the use time of the first memory cell is very short (for example when, data are deposited in the first memory cell Between do not grow) and/or the usage degree of the first memory cell it is very low (for example, the first memory cell reading count, write count And/or counting of erasing is not high), the usual very little of area of overlapping region 730, in some instances it may even be possible to there is no (that is, the shape of overlapping region 730 State 710 is not overlap with 720).Or, if memory storage apparatus 10 have just just dispatched from the factory, overlapping region 730 there is usually no.If The area very little of overlapping region 730, the mistake in the data read from the first memory cell by applying read voltage 701 Bit is often less.
However, with rewritable nonvolatile memory module 406 (or first memory cell) use time and/or make Increased with degree, the area of overlapping region 730 can be gradually increased.For example, if the very long (example of the use time of the first memory cell Such as, data resting period in the first memory cell is very long) and/or the usage degree of the first memory cell it is very high by (for example, first The reading of memory cell is counted, write is counted and/or counting of erasing is very high), then greatly (for example, the area of overlapping region 730 can become It is closer that state 710 and 720 can change flat and/or state 710 and 720).If the area of overlapping region 730 is very big, Error bit in the data read from the first memory cell by applying read voltage 701 is often more.In other words, weight The area in folded region 730 can be positively correlated with the Probability of error bit in the data read out from the first memory cell.
In this exemplary embodiment, from rewritable nonvolatile memory module 406 the first read data are being received Afterwards, with the presence or absence of mistake during error checking can perform odd-even check operation to verify the first data with correcting circuit 508.If Judge there is mistake in the first data, then error checking attempts the number of corrigendum first with the meeting perform decoding operation of correcting circuit 508 Mistake according in.
In this exemplary embodiment, error checking is carried out iteration (iteration) decoding operate with correcting circuit 508. One iterative decoding operation is for decoding a decoding unit for coming from rewritable nonvolatile memory module 406.Example Such as, a decoding unit is a code word.In an iterative decoding operation, for checking the odd-even check of the correctness of data Operate and can repeat for the wrong decoding operate in more correction data, until successfully decoding or total iterations are reached Till one pre-determined number.If total iterations reaches this pre-determined number, represent for the whole iterative decoding operation of this data loses Lose, and error checking can stop decoding with correcting circuit 508.If additionally, being judged in a certain data by odd-even check operation There is no mistake, then error checking can export this data with correcting circuit 508.
In this exemplary embodiment, error checking can be counted based on different decoding conditions from correcting circuit 508 to first According to the multiple decoding operates of execution.It is noted that based on different decoding conditions, error checking and the positioning of correcting circuit 508 the The rigor (strict level) that error bit is used in one data also can be different.For example, in some cases, mistake inspection Looking into can perform one and change with correcting circuit 508 based on the decoding condition of the rigor of Wrong localization bit higher (i.e., more strictly) An at least decoding operate in for decoding operate.Additionally, in some cases, error checking can be changed to base with correcting circuit 508 In Wrong localization bit rigor relatively low (i.e., more loosely) decoding condition to perform same iterative decoding operation in extremely A few decoding operate.
In this exemplary embodiment, the rigor of Wrong localization bit is higher to be referred to for the error bit in the first data Judgement it is more strict with screening, so as to one or more bits in the first data are less easily determined to be error bit. Contrary, the rigor of Wrong localization bit is relatively low, refer to for the error bit in the first data judgement with screening more Loosely, so as to one or more bits in the first data are easier to be determined to be error bit.In other words, based on Wrong localization The decoding condition that the rigor of bit is relatively low has higher probability to overturn more bits to operate to a certain code word perform decoding, But also increase the probability for being turned to the bit (that is, turning over by mistake) that need not be overturn；Conversely, the rigor based on Wrong localization bit Higher decoding condition then has higher probability to be the less bit of upset to operate to this code word perform decoding, but also reduces It is turned to the probability of the bit that need not be overturn.It is noted that overturn some bit referred in this and refer to changing this ratio Special bit value, such as from " 1 " change into " 0 " or change into " 1 " from " 0 " by the bit value of a certain bit.
In this exemplary embodiment, error checking is configured with multiple stages (stage), each of which with correcting circuit 508 The individual stage is corresponding to a decoding condition.In the same iterative decoding operation for the first data, error checking with correction Circuit 508 can switch in here a little stages.Additionally, in each stage, error checking and correcting circuit 508 executable one or Multiple decoding operates.
Fig. 8 is that the switch step in an iterative decoding operation shown by an exemplary embodiment of the invention is shown It is intended to.Refer to Fig. 8, it is assumed that have used with correcting circuit 508 for error checking 0~stage of stage 15, the wherein stage 0 is positioning The stage of the rigor highest (that is, most rigorous) of error bit, and the stage 15 be Wrong localization bit rigor it is minimum (i.e., It is most loose) stage.In 0~stage of stage 15, the rigor of Wrong localization bit is gradually reduced.For example, the stage 0 is rigorous Higher than the rigor in stage 1, the rigor in stage 1 is higher than the rigor in stage 2 to degree, and the rigor in stage 14 is higher than the stage 15 rigor.
In this exemplary embodiment, if error checking and correcting circuit 508 are currently operate within the stage 0 (namely be based on the stage 0 decoding condition carrys out perform decoding operation) and judge to need switching encoding/decoding condition, error checking to switch with correcting circuit 508 To the stage 1.If error checking and correcting circuit 508 are currently operate within the stage 1 and (namely be based on the decoding condition in stage 1 to perform Decoding operate) and judge to need switching encoding/decoding condition, error checking to switch to the stage 2 with correcting circuit 508.The rest may be inferred, Error checking can one by one be switched in the same iterative decoding operation for the first data with correcting circuit 508 from the stage 0 Stage 15, till some decoding operate success or total iterations reach pre-determined number.It is noted that from the stage During 0 switches to one by one the stage 15, error checking is with correcting circuit 508 for the positioning of error bit in data to be decoded It is increasingly looser, so as to the sum of the error bit being reversed in each decoding operate may gradually increase.But, this Also the sum that represent the bit " turned over by mistake " in each decoding operate is likely to gradually increase.
In some cases, if the bit that " turned over " in decoding operate is excessive by mistake, continuously perform many be may result in Individual decoding operate maintains the state of mistake diverging.In the state of mistake diverging, even if performing more decoding operates, data The sum of middle error bit may not be reduced or can be in the situation shaken up and down, so as to ultimately result in whole iterative decoding Operation failure (for example, total iterations reaches pre-determined number).Therefore, in this exemplary embodiment, error checking is electric with correction Road 508 can return to some stage in 0~stage of stage 14 from the stage 15.By improving Wrong localization in decoding operate again The rigor of bit, performed decoding operate has very high probability to depart from the state of mistake diverging, improves follow-up decoding Success rate.Additionally, compared to generally use noise jamming (noising) (that is, randomly change data to be decoded one or more Bit value) or similar fashion to attempt departing from the state of mistake diverging, by improving Wrong localization bit in decoding operate again Rigor also have higher probability to be turned to real error bit.
Fig. 8 is returned to, if error checking and correcting circuit 508 are currently operate within the stage 15 (namely be based on the decoding in stage 15 Condition carrys out perform decoding operation) and judge to need switching encoding/decoding condition, error checking to switch back to the stage with correcting circuit 508 Some stage in 0~stage 14, so as to the rigor for improving Wrong localization bit in the decoding operate for performing next time. After the rigor higher stage is switched back into from the stage 15, error checking can continue to switch to the stage 15 with correcting circuit 508, Unless till some the decoding operate success for performing therebetween or total iterations reach pre-determined number.Additionally, changing same In for decoding operate, if error checking switches back into the existing stage from the stage 15 in multiple times with correcting circuit 508, switch each time The stage gone back may be different.By taking Fig. 8 as an example, if front once switch to the existing stage to be to revert to the (Fig. 8 of stage 7 from the stage 15 In be labeled as " 1 "), switch to the existing stage to be to revert to the stage 9 (being labeled as in Fig. 8 " 2 ") from the stage 15 next time.
It is noted that 0~the stage of stage 15 in Fig. 8 is only an example.In other NM exemplary embodiments In, error checking can also be more or less with the sum in the exercisable stage of correcting circuit 508.Additionally, error checking with Correcting circuit 508 can also be skipped one or more stages in switching once, for example, from the stage 0 stage 2 etc. is directly switch to Deng.
From the point of view of specifically, it is assumed that error checking and correcting circuit 508 are currently based on a certain decoding condition (hereinafter also referred to the One decoding condition) a certain decoding operate (hereinafter also referred to the first decoding operate) is performed to the first data.If the first decoding operate Failure, memory management circuitry 502 can judge the first decoding operate whether meet a preset state (hereinafter also referred to first preset State).If the first decoding operate meets the first preset state, error checking can be based on another decoding condition with correcting circuit 508 (the hereinafter also referred to second decoding condition) performs another decoding operate (hereinafter also referred to the second decoding operate) to the first data, its In the rigor of error bit in the first data is positioned based on the second decoding condition higher than based on the first decoding condition positioning the The rigor of the error bit in one data.
Additionally, memory management circuitry 502 can also judge whether the first decoding operate meets another preset state (below Referred to as the second preset state).If the first decoding operate meets the second preset state, error checking can be based on correcting circuit 508 Another decoding condition (the hereinafter also referred to the 3rd decoding condition) performs another decoding operate the (the hereinafter also referred to the 3rd to the first data Decoding operate), wherein the rigor for positioning the error bit in the first data based on the 3rd decoding condition is less than based on the first solution Code-bar part positions the rigor of the error bit in the first data.If the first decoding operate does not meet the first preset state not being inconsistent yet The second preset state is closed, error checking can be again based on the first decoding condition and perform first to the first data with correcting circuit 508 Decoding operate.
Fig. 9 A are the schematic diagrames of the switch step shown by an exemplary embodiment of the invention.Fig. 9 A are refer to, it is false If error checking is currently operate within stage n (that is, the first decoding condition) with correcting circuit 508.If operating in the first of stage n Decoding operate failure and not yet reach the stop condition of whole iterative decoding operation (for example, total iterations reaches predetermined time Number), memory management circuitry 502 can judge whether the first decoding condition meets a stage conditions.For example, memory management circuitry 502 can judge that whether stage n is rigor minimum stage (for example, the stage 15 in Fig. 8) of Wrong localization bit.If the stage N is not rigor minimum stage of Wrong localization bit (for example during, stage n is probably the 0~stage of stage 14 in Fig. 8 Any one), memory management circuitry 502 can judge that the first decoding condition does not meet stage conditions.Additionally, memory management circuitry 502 can judge whether the sum of the bit that the first decoding operate is overturn meets a number condition.For example, if the first decoding operate The sum of the bit for being overturn is zero (that is, none of bit is reversed in the first decoding operate), memory management Circuit 502 can judge that the sum of the bit that the first decoding operate is overturn meets number condition.If conversely, the first decoding operate institute The sum of the bit of upset is not zero (that is, at least one bit is reversed in the first decoding operate), then memory management electricity Road 502 can judge that the sum of the bit that the first decoding operate is overturn does not meet number condition.If the first decoding condition does not meet The sum of the bit that stage conditions and the first decoding operate are overturn meets number condition, error checking and the meeting of correcting circuit 508 It is switched to and operates in stage n+1 (that is, the 3rd decoding condition).
In other words, in this exemplary embodiment, due to not having in the front decoding operate (that is, the first decoding operate) for once performing There is any bit of upset and the also lower decoding condition of rigor can be used, therefore error checking exists with the meeting of correcting circuit 508 The rigor of Wrong localization bit is reduced in decoding operate (that is, the 3rd decoding operate) next time, so as to improve number to be decoded The probability that at least one bit is reversed according in.
Fig. 9 B are the schematic diagrames of the switch step shown by another exemplary embodiment of the invention.Fig. 9 B are refer to, Assume that error checking is currently operate within stage m (that is, the first decoding condition) with correcting circuit 508.If operating in the of stage m The failure of one decoding operate and the stop condition of whole iterative decoding operation is not yet reached, memory management circuitry 502 can judge the Whether one decoding condition meets stage conditions.Because stage m has been the minimum stage (example of rigor of Wrong localization bit Such as, the stage 15 in Fig. 8), memory management circuitry 502 can judge that the first decoding condition meets stage conditions.Judging first Decoding condition meets after stage conditions, an iteration count value of the first decoding operate of counting of memory management circuitry 502, its In this iteration count value represent and operate in first decoding operate of stage m repeatedly (iteratively) is performed several times.So Afterwards, memory management circuitry 502 can judge whether iteration count value meets a count condition.If iteration count value is not inconsistent total number Condition, error checking may proceed to perform the first decoding operate for operating in stage m with correcting circuit 508.If iteration count value is accorded with Total said conditions, for example, iteration count value reaches 10 times, and error checking can switch back into Wrong localization bit with correcting circuit 508 The higher stage p of rigor (that is, the second decoding condition).
In other words, in this exemplary embodiment, the first decoding operate for operating in stage m had been performed many times repeatedly (for example, 10 times) and the first data still cannot be successfully decoded, indicate that very high probability is to repeat to be turned to be not required to too much The bit to be overturn.Therefore, error checking can be in decoding operate (that is, the second decoding operate) next time with correcting circuit 508 The middle rigor for improving Wrong localization bit, so as to reduce the probability that partial bit is turned over by mistake.Additionally, operate in stage p it Afterwards, error checking and correcting circuit 508 can continue and be operated at stage p+1 etc., such as the exemplary embodiment of Fig. 9 A, and here is just not Repeat.
Fig. 9 C are the schematic diagrames of the switch step shown by another exemplary embodiment of the invention.Fig. 9 C are refer to, The exemplary embodiment of Fig. 9 B is connected in, if error checking is operated at again stage m, current operation in rank with correcting circuit 508 Decoding operate (that is, the first decoding operate) failure of section m and not yet reach the stop condition of whole iterative decoding operation, memory Management circuit 502 can again judge that the first decoding operate meets stage conditions and counts the iteration count value of the first decoding operate. For example, this iteration count value represents from stage p and turns again to after stage m that the first decoding operate for operating in stage m is held altogether Go several times.Then, memory management circuitry 502 can judge whether iteration count value meets a count condition.For example, memory Management circuit 502 can judge whether be equal to 7 corresponding to the iteration count value of this first decoding operate for operating in stage m.If Iteration count value does not meet count condition, and (for example, less than 7), error checking can repeat to hold iteration count value with correcting circuit 508 Row operates in first decoding operate of stage m.If iteration count value coincidence counting condition, for example, iteration count value reaches 7, mistake The higher stage q of flase drop is looked into correcting circuit 508 can switch back into Wrong localization bit rigor (that is, the second new solution code-bars Part).After stage q is operated in, error checking can continue with correcting circuit 508 and be operated at stage q+1 etc., such as Fig. 9 A Exemplary embodiment, here is not just repeated.
It is noted that in an exemplary embodiment of Fig. 9 B and Fig. 9 C, for determine to be to revert to existing stage p (or Q) count condition for or persistently maintaining stage m is different.For example, in the same iterative decoding operation for the first data, deposit The count condition that reservoir management circuit 502 can select corresponding to different count values from multiple candidate's count conditions, using as Judgement is to revert to the foundation in existing stage.For example, in an exemplary embodiment of Fig. 9 B, memory management circuitry 502 can be with Candidate's count condition (hereinafter also referred to first candidate's count condition) is selected from multiple candidate's count conditions as current The count condition for using, wherein (for example, 10) first candidate's count condition corresponds to the first count value.Then, the one of Fig. 9 C In exemplary embodiment, memory management circuitry 502 is changed to select another candidate's count condition from this little candidate's count condition (hereinafter also referred to second candidate's count condition) as currently used count condition, wherein second candidate's count condition is corresponded to Second count value is (for example, 7).By the count value for reducing the count condition for sequentially using, whole iterative decoding operation can be improved Execution efficiency.However, in another exemplary embodiment, in the same iterative decoding operation for the first data, being used Count condition can also be constant.
In an exemplary embodiment of Fig. 9 B and Fig. 9 C, stage p (that is, p is not equal to q) also different from stage q, wherein stage P for Wrong localization bit rigor higher than stage q for the rigor of Wrong localization bit.For example, for the first number According to same iterative decoding operation in, memory management circuitry 502 can select appropriate decoding from multiple candidate solution code-bar parts Condition is used as the second decoding condition.For example, in an exemplary embodiment of Fig. 9 B, memory management circuitry 502 can be from multiple A candidate solution code-bar part (hereinafter also referred to the first candidate solution code-bar part) is selected in candidate solution code-bar part as what is will used Second decoding condition, it corresponds to stage p.Then, in an exemplary embodiment of Fig. 9 C, memory management circuitry 502 is changed to Another candidate solution code-bar part (hereinafter also referred to the second candidate solution code-bar part) is selected from this little candidate solution code-bar part as i.e. By the second decoding condition for using, it corresponds to stage q.By the way that the second decoding condition is changed into stage q from stage p, also may be used Improve the execution efficiency of whole iterative decoding operation.However, in another exemplary embodiment, changing for the same of the first data For in decoding operate, error checking and correcting circuit 508 can also be switched to (such as rank of same stage from stage m all the time Section p or stage q), rather than different stages.
Figure 10 is the schematic diagram of the odd-even check operation shown by an exemplary embodiment of the invention.Refer to figure 10, it is assumed that the first packet read from the first memory cell contains code word 1001, then in odd-even check operation, according to equation Formula (5), parity check matrix 1000 can be multiplied with code word 1001 and obtain and verify 1002 (that is, vectorial S) of vector.Wherein, code Each bit in word 1001 is to correspond to vectorial at least one of 1002 elements (that is, syndrome) of verification.For example, Bit V0 (correspondence is to the first row in parity check matrix 1000) in code word 1001 is to correspond to syndrome S1, S4 and S7； Bit V1 (correspondence is to the second row in parity check matrix 1000) is to correspond to syndrome S2, S3 and S6, by that analogy.If than Special V0 is error bit, then at least one of syndrome S1, S4 and S7 may be " 1 ".If bit V1 is error bit, Then at least one of syndrome S2, S3 and S6 may be " 1 ", by that analogy.In other words, if syndrome S0~S7 is all " 0 ", representing in code word 1001 may be without mistake, therefore error checking and correcting circuit 508 can direct output codons 1001.So And, if in code word 801 have mistake, at least one of syndrome S0~S7 may be " 1 ", and error checking with Correcting circuit 508 can be operated to the perform decoding of code word 1001.
In this exemplary embodiment, error checking with correcting circuit 508 is drilled using bit reversal (Bit-Flipping) Algorithm carrys out perform decoding operation, therefore error checking is to recognize the first number based on a upset threshold value with correcting circuit 508 According to the middle bit (that is, error bit) for needing and being reversed, each of which stage (or decoding condition) corresponds to a upset Threshold value.For example, in an exemplary embodiment of Fig. 8, the upset threshold value corresponding to the stage 0 is maximum, corresponding to the stage 15 Upset threshold value is minimum, and the upset threshold value in stage 0 to stage 15 is gradually lowered.However, in another exemplary embodiment, Error checking can also be using minimum-sum total (Min-Sum) algorithm or summation-product (Sum- with correcting circuit 508 Product) decoding algorithm such as algorithm carrys out perform decoding operation.
In this exemplary embodiment, error checking and correcting circuit 508 can according to parity check matrix 1000 with verify to The error weight of each bit during 1002 are measured to calculate code word 1001.For example, error checking will be corresponding with the meeting of correcting circuit 508 The syndrome of same bit is added to obtain the error weight of this bit into code word 1001.For example, E0~E8 is respectively intended to The error weight of bit V0~V8 is represented, the wherein error weight E0 of bit V0 is equal to the addition of syndrome S1, S4 and S7；Bit The error weight E1 of V1 is equal to the addition of syndrome S2, S3 and S6, by that analogy.It is noted that at this to syndrome S0~ The addition that S7 is done is general addition, rather than the addition of mould 2.For example, error checking and correcting circuit 508 can by with Lower equation (6) to obtain code word 1001 in each bit error weight, each element wherein in vector f can use The error weight of each bit in represent code word.
F=ST×H…(6)
After error weight is obtained, error checking can overturn error weight in code word 1001 and be more than with correcting circuit 508 The all or at least a portion bit of the upset threshold value for being used.Therefore, by switch step (or decoding condition), mistake inspection Looking into can also be adjusted to error checking and correcting circuit with correcting circuit 508 for the upset threshold value for recognizing error bit 508 in a certain decoding operate Wrong localization bit be rigorous or loosely also can be determined.
In an exemplary embodiment, error checking and correcting circuit 508 are to define the first number by below equation (7) The error weight of each bit according in, wherein equation (7) are also referred to as cost function (cost function).
EWi=α Ai+βBi…(7)
In equation (7), EWi represents the error weight of i-th bit (that is, bit Vi) in the first data, and Ai is equal to Ei in the exemplary embodiment of Figure 10, and whether the value of Bi is then equal to its initial value and sets corresponding to the currency of bit Vi. For example, it is assumed that the initial value of bit Vi is " 1 ", after decoding operate at least one times, if bit Vi is changed to " 0 ", then the value of Bi can be set as " 1 ", it is different from its initial value with the currency for representing bit Vi；Conversely, through at least one After secondary decoding operate, if bit Vi is remained " 1 ", the value of Bi can be set as " 0 ", to represent the currency etc. of bit Vi In its initial value.Additionally, α and β is all constant.Compared to directly using Ei as the error weight of bit Vi, equation (7) is used More parameters are adjusting the error weight EWi of bit Vi.In some cases, error weight EWi is compared to error weight Ei It is more accurate for the positioning of error bit.
In an exemplary embodiment, after the verification vector for obtaining the first data, error checking and the meeting of correcting circuit 508 Obtain the syndrome sum total of the first data.By taking Figure 10 as an example, error checking and correcting circuit 508 can the sub- S0~S7 of total check with Obtain the syndrome sum total corresponding to code word 1001.For example, if having k " 1 ", the verification of code word 1001 in syndrome S0~S7 Son sum total is k.Whether error checking can judge this syndrome sum total less than a preset value with correcting circuit 508.If this verification Son sum total is less than preset value, and error checking can be reduced the error weight value of each bit in the first data with correcting circuit 508, example Such as it is reduced to the second error weight value from the first error weight value.Reduce the first data in each bit error weight value it Afterwards, next decoding operate can be performed.For example, in next decoding operate (for example, the first decoding operate), if some Error weight value (that is, the second error weight value) after the reduction of bit is more than turning over corresponding to the first decoding condition for being used Revolving door threshold value, error checking can overturn this bit with correcting circuit 508 in the decoding operate of here first.If however, being counted Syndrome sum total is not less than preset value, and error checking will not actively reduce the mistake of each bit in the first data with correcting circuit 508 Miss weighted value.
In an exemplary embodiment, if it is determined that the syndrome sum total of the first data is less than preset value, error checking and correction Circuit 508 can be changed to using below equation (8) to calculate the first data in each bit error weight.Compared to using equation Formula (7), using equation (8) value of the error weight for calculating can be reduced.
EWi=α Ai…(8)
It is noted that, although above-mentioned exemplary embodiment be all using bit reversal algorithm as example, but at other In NM embodiment, error checking can also be using minimum-sum total algorithm or summation-product with correcting circuit 508 The decoding algorithms such as algorithm carry out perform decoding operation.Art tool usually intellectual should know to need by adjusting Whole which parameter to adjust various decoding algorithms in for Wrong localization bit rigor, here just do not repeat.
Figure 11 is the flow chart of the coding/decoding method shown by an exemplary embodiment of the invention.Figure 11 is refer to, In step S1101, from multiple first memory cell of rewritable nonvolatile memory module the first data are read.In step In S1102, the first decoding operate is performed to the first data based on the first decoding condition.It is noted that the present invention is not intended to limit This first decoding operate is which time decoding operate performed after the first data are read, as long as belonging to for the first data Same iterative decoding operation.In step S1103, judge whether the first decoding operate meets the first preset state.If First decoding operate meets the first preset state, in step S1104, second is performed to the first data based on the second decoding condition Decoding operate, wherein the rigor for positioning the error bit in the first data based on the second decoding condition is higher than based on the first decoding Condition positions the rigor of the error bit in the first data.If the first decoding operate does not meet the first preset state, in step In S1105, judge whether the first decoding operate meets the second preset state.If the first decoding operate meets the second preset state, In step S1106, the 3rd decoding operate is performed to the first data based on the 3rd decoding condition, wherein based on the 3rd decoding condition Position the error bit that the rigor of the error bit in the first data is positioned in the first data less than the first decoding condition that is based on Rigor.If the first decoding operate does not meet the first preset state and does not meet the second preset state yet, step S1105 it Afterwards, step S1102 can be repeatedly executed.It is noted that in the coding/decoding method of Figure 11, as long as reaching whole iterative decoding behaviour The stop condition (for example, successfully decoded or total iterations reach pre-determined number) of work, then whole iterative decoding operation will stop Only.
Figure 12 is the flow chart of the coding/decoding method shown by another exemplary embodiment of the invention.Refer to Figure 12, In step S1201, from multiple first memory cell of rewritable nonvolatile memory module the first data are read.In step In S1202, the first data are performed with odd-even check and operates the syndrome to obtain the first data to sum up.In step S1203, sentence Whether disconnected syndrome sum total is less than preset value.If syndrome sum total is less than preset value, in step S1204, by the first data The error weight value of each bit is reduced to the second error weight value from the first error weight value.In step S1205, based on a solution Code-bar part is operated to the first data perform decoding.For example, decoding condition now is the first decoding condition.If additionally, syndrome Sum total is not less than preset value, then also into step S1205 after step S1203.In step S1206, decoding operate is judged Whether first preset state is met.If decoding operate meets the first preset state, in step S1207, decoding condition is updated For the second decoding condition, wherein the rigor of the error bit in the first data is positioned based on the second decoding condition higher than based on the One decoding condition positions the rigor of the error bit in the first data.If decoding operate does not meet the first preset state, in step In rapid S1208, judge whether decoding operate meets the second preset state.If decoding operate meets the second preset state, in step In S1209, decoding condition is updated into the 3rd decoding condition, wherein positioning the mistake in the first data based on the 3rd decoding condition The rigor of bit is less than the rigor that the error bit in the first data is positioned based on the first decoding condition.If decoding operate is not Meet the first preset state and also do not meet the second preset state, after step S1208, step S1202 can be repeatedly executed.This Outward, after step S1207 and S1209, step S1202 also can be repeatedly executed.It is noted that in the coding/decoding method of Figure 12 In, as long as reaching the stop condition (for example, successfully decoded or total iterations reach pre-determined number) of whole iterative decoding operation, Then whole iterative decoding operation will stop.
However, each step has been described in detail as above in Figure 11 and Figure 12, here is just repeated no more.It should be noted that figure 11 can be implemented as multiple procedure codes or circuit with each step in Figure 12, and the present invention is not any limitation as.Additionally, Figure 11 and Figure 12 The method example above embodiment that can arrange in pairs or groups use, it is also possible to be used alone, the present invention is not any limitation as.
In sum, the present invention can flexibly adjust the rigorous of decoding operate Wrong localization bit in iterative decoding operation Degree.Additionally, by set switching law, the decoding efficiency of memory storage apparatus can be elevated.
Finally it should be noted that：Various embodiments above only to illustrate technical scheme, rather than a limitation；To the greatest extent Pipe has been described in detail with reference to foregoing embodiments to the present invention, it will be understood by those within the art that：Its according to So the technical scheme described in foregoing embodiments can be modified, either which part or all technical characteristic are entered Row equivalent；And these modifications or replacement, do not make the essence disengaging various embodiments of the present invention technology of appropriate technical solution The scope of scheme.

Claims (21)

1. a kind of coding/decoding method, for including the rewritable nonvolatile memory module of multiple memory cell, it is characterised in that The coding/decoding method includes：
Multiple first memory cell from the plurality of memory cell read the first data；
First decoding operate is performed to first data based on the first decoding condition；And
If first decoding operate meets the first preset state, second is performed to first data based on the second decoding condition Decoding operate,
Rigor wherein based on the error bit in the described second decoding condition positioning first data is higher than based on described First decoding condition positions the rigor of the error bit in first data.
2. coding/decoding method according to claim 1, it is characterised in that also include：
If first decoding operate meets the second preset state, the 3rd is performed to first data based on the 3rd decoding condition Decoding operate,
The rigor for wherein positioning the error bit in first data based on the 3rd decoding condition is less than and is based on The first decoding condition positions the rigor of the error bit in first data.
3. coding/decoding method according to claim 2, it is characterised in that also include：
If the first decoding condition meets stage conditions, the iteration count value of first decoding operate is counted；And
If the iteration count value coincidence counting condition, judge that first decoding operate meets first preset state.
4. coding/decoding method according to claim 3, it is characterised in that also include：
If the first decoding condition does not meet the sum of the bit that the stage conditions and first decoding operate are overturn Meet number condition, judge that first decoding operate meets second preset state.
5. coding/decoding method according to claim 3, it is characterised in that also include：
The count condition is selected from first candidate's count condition and second candidate's count condition,
Wherein described first candidate count condition corresponds to the first count value, and the second candidate count condition is corresponding to the second meter Numerical value, and first count value is different from second count value.
6. coding/decoding method according to claim 1, it is characterised in that also include：
The second decoding condition is selected from the first candidate solution code-bar part and the second candidate solution code-bar part,
Rigor wherein based on the error bit in the first candidate solution code-bar part location data is higher than based on described second Candidate solution code-bar part positions the rigor of the error bit in the data.
7. coding/decoding method according to claim 1, it is characterised in that also include：
First data are performed with odd-even check operates the syndrome to obtain first data to sum up；
If the syndrome sum total is less than preset value, by the error weight value of the bit in first data from the first mistake power Weight values are reduced to the second error weight value；And
If the second error weight value is more than the upset threshold value corresponding to the described first decoding condition, in the described first decoding The bit is overturn in operation.
8. a kind of memory storage apparatus, it is characterised in that include：
Connecting interface unit, to be connected to host computer system；
Rewritable nonvolatile memory module, including multiple memory cell；And
Memorizer control circuit unit, is connected to the connecting interface unit and the rewritable nonvolatile memory module,
The memorizer control circuit unit is to send reading command sequence, wherein the reading command sequence is indicated from described Multiple first memory cell in multiple memory cell read the first data,
The memorizer control circuit unit based on the first decoding condition also to perform the first decoding behaviour to first data Make,
If first decoding operate meets the first preset state, the memorizer control circuit unit is also to based on the second solution Code-bar part performs the second decoding operate to first data,
Rigor wherein based on the error bit in the described second decoding condition positioning first data is higher than based on described First decoding condition positions the rigor of the error bit in first data.
9. memory storage apparatus according to claim 8, it is characterised in that if first decoding operate meets second Preset state, the memorizer control circuit unit is also solved to perform the 3rd to first data based on the 3rd decoding condition Code operation,
The rigor for wherein positioning the error bit in first data based on the 3rd decoding condition is less than and is based on The first decoding condition positions the rigor of the error bit in first data.
10. memory storage apparatus according to claim 9, it is characterised in that if the first decoding condition meets rank Section condition, the memorizer control circuit unit also to count the iteration count value of first decoding operate,
If the iteration count value coincidence counting condition, the memorizer control circuit unit judges the first decoding operate symbol Close first preset state.
11. memory storage apparatus according to claim 10, it is characterised in that if the first decoding condition does not meet The sum of the bit that the stage conditions and first decoding operate are overturn meets number condition, the memory control electricity Road unit judges that first decoding operate meets second preset state.
12. memory storage apparatus according to claim 10, it is characterised in that the memorizer control circuit unit is also To select the count condition from first candidate's count condition and second candidate's count condition,
Wherein described first candidate count condition corresponds to the first count value, and the second candidate count condition is corresponding to the second meter Numerical value, and first count value is different from second count value.
13. memory storage apparatus according to claim 8, it is characterised in that the memorizer control circuit unit is also To select the second decoding condition from the first candidate solution code-bar part and the second candidate solution code-bar part,
Rigor wherein based on the error bit in the first candidate solution code-bar part location data is higher than based on described second Candidate solution code-bar part positions the rigor of the error bit in the data.
14. memory storage apparatus according to claim 8, it is characterised in that the memorizer control circuit unit is also The syndrome to obtain first data is operated to sum up first data are performed with odd-even check,
If the syndrome sum total is less than preset value, the memorizer control circuit unit is also to by first data The error weight value of bit is reduced to the second error weight value from the first error weight value,
If the second error weight value is more than the upset threshold value corresponding to the described first decoding condition, the memory control Circuit unit in first decoding operate also to overturn the bit.
15. a kind of memorizer control circuit units, to the rewritable nonvolatile memory for controlling to include multiple memory cell Module, it is characterised in that the memorizer control circuit unit includes：
HPI, to be connected to host computer system；
Memory interface, to be connected to the rewritable nonvolatile memory module；
Error checking and correcting circuit；And
Memory management circuitry, is connected to the HPI, the memory interface and the error checking and correcting circuit,
The memory management circuitry is to send reading command sequence, wherein the reading command sequence is indicated from the plurality of Multiple first memory cell in memory cell read the first data,
The error checking performs the first decoding operate to decode condition based on first with correcting circuit to first data,
If first decoding operate meets the first preset state, the error checking is with correcting circuit also to based on the second solution Code-bar part performs the second decoding operate to first data,
Wherein described error checking positions the mistake ratio in first data with correcting circuit based on the described second decoding condition Special rigor is positioned in first data with correcting circuit higher than the error checking based on the described first decoding condition The rigor of the error bit.
16. memorizer control circuit units according to claim 15, it is characterised in that if first decoding operate symbol The second preset state is closed, the error checking is with correcting circuit also to perform to first data based on the 3rd decoding condition 3rd decoding operate,
Wherein described error checking positions the mistake in first data with correcting circuit based on the described 3rd decoding condition The rigor of errored bit positions first data with correcting circuit less than the error checking based on the described first decoding condition In the error bit the rigor.
17. memorizer control circuit units according to claim 16, it is characterised in that if the first decoding condition symbol Close stage conditions, the memory management circuitry also to count the iteration count value of first decoding operate,
If the iteration count value coincidence counting condition, the memory management circuitry judges that first decoding operate meets institute State the first preset state.
18. memorizer control circuit units according to claim 17, it is characterised in that if the first decoding condition is not The sum for meeting the bit that the stage conditions and first decoding operate are overturn meets number condition, the memory pipe Reason circuit judges that first decoding operate meets second preset state.
19. memorizer control circuit units according to claim 17, it is characterised in that the memory management circuitry is also To select the count condition from first candidate's count condition and second candidate's count condition,
Wherein described first candidate count condition corresponds to the first count value, and the second candidate count condition is corresponding to the second meter Numerical value, and first count value is different from second count value.
20. memorizer control circuit units according to claim 15, it is characterised in that the memory management circuitry is also To select the second decoding condition from the first candidate solution code-bar part and the second candidate solution code-bar part,
Wherein described error checking is with correcting circuit based on the error bit in the first candidate solution code-bar part location data Rigor is positioned described in the data higher than the error checking and correcting circuit based on the second candidate solution code-bar part The rigor of error bit.
21. memorizer control circuit units according to claim 15, it is characterised in that the error checking and correction electricity Road also operates the syndrome to obtain first data to sum up first data are performed with odd-even check,
If the syndrome sum total is less than preset value, the error checking is with correcting circuit also to by first data The error weight value of bit is reduced to the second error weight value from the first error weight value,
If the second error weight value more than corresponding to described first decoding condition upset threshold value, the error checking with Correcting circuit in first decoding operate also to overturn the bit.
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