CN105304143A - Decoding method, memory control circuit unit and memory storage device - Google Patents

Abstract

The invention provides a decoding method, a memory control circuit unit and a memory storage device. The decoding method comprises the following steps: sending a reading instruction sequence which is used for reading a plurality of storage units to obtain a plurality of bits, and obtaining pieces of reliability information corresponding to the bits; calculating the sum of the reliability information which accords with a check condition, and adding the sum to balance information to obtain a weight corresponding to the first bit in the bits and a first syndrome; and judging whether the bits have at least one error, and executing an iteration decoding program according to the weight if the bits have at least one error.

Description

Coding/decoding method, memorizer control circuit unit and memory storage apparatus

Technical field

The invention relates to a kind of coding/decoding method, and relate to a kind of coding/decoding method for reproducible nonvolatile memorizer module, memorizer control circuit unit and memory storage apparatus especially.

Background technology

Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and the demand of consumer to medium is also increased rapidly.Due to reproducible nonvolatile memorizer module (such as, flash memory) there is data non-volatile, power saving, volume are little, and the characteristic such as mechanical structure, so be built in above-mentioned illustrated various portable multimedia devices in being applicable to very much.

In general, the data writing to reproducible nonvolatile memorizer module all can be encoded according to an error correcting code.The data read from reproducible nonvolatile memorizer module also can through corresponding decoding program.But the corrigendum ability of error correcting code has its upper limit, and the probability that in reproducible nonvolatile memorizer module, data make a mistake can change together along with serviceable life.Therefore, how to increase corrigendum ability and the correctness of decoding, for this reason the problem be concerned about of those skilled in the art.

Summary of the invention

The invention provides a kind of coding/decoding method, memorizer control circuit unit and memory storage apparatus, it can improve the corrigendum ability of decoding effectively.

One example of the present invention embodiment provides a kind of coding/decoding method for reproducible nonvolatile memorizer module, described reproducible nonvolatile memorizer module comprises multiple storage unit, this coding/decoding method comprises: send reading command sequence, wherein said reading command sequence is in order to read multiple storage unit to obtain multiple position; Obtain multiple reliability information, wherein each reliability information corresponds to one of them of institute's rheme; Calculate in described reliability information the summation of the multiple reliability information meeting examination condition; Described summation is added balancing information is to obtain corresponding to the weight of first in institute's rheme with the first syndrome; Judge whether institute's rheme has at least one mistake; And if institute's rheme has at least one mistake, perform iterative decoding procedures according to described weight.

In one example of the present invention embodiment, above-mentionedly judge whether this little position has at least one wrong step and comprise: odd-even check program is performed to obtain the multiple syndromes comprising the first syndrome to institute's rheme, wherein each institute's rheme be correspond to described syndrome at least one of them; And judge whether institute's rheme has at least one mistake according to described syndrome.Described odd-even check program is performed by parity-check matrix, and described parity-check matrix comprises multiple restriction (constraint), the step meeting the summation of the described reliability information of examination condition in the described reliability information of above-mentioned calculating comprises: according to the first restriction corresponding to described first syndrome in described restriction, determines the described reliability information meeting described examination condition from described reliability information.

In one example of the present invention embodiment, above-mentioned first restriction comprises multiple element, and from described reliability information, determine that the step meeting the described reliability information of described examination condition comprises: the multiple elements according to described element intermediate value being " 1 " according to described first restriction, from described reliability information, determine the described reliability information meeting described examination condition.

In one example of the present invention embodiment, above-mentioned described summation is added described balancing information with obtain correspond to described first comprise with the step of the described weight of described first syndrome: described summation is added described balancing information is to obtain the first appreciation information; And by described first appreciation information divided by the second appreciation information with obtain correspond to described first with the described weight of described first syndrome, wherein said second appreciation information is corresponding to described primary reliability information in described reliability information.

In one example of the present invention embodiment, above-mentioned coding/decoding method, also comprises: select to correspond to the deputy reliability information in institute's rheme from the described reliability information meeting described examination condition, wherein said second is different from described first; And Dynamic gene will be multiplied by obtain described balancing information corresponding to described deputy described reliability information.

One example of the present invention embodiment proposes a kind of memorizer control circuit unit for controlling reproducible nonvolatile memorizer module, and wherein reproducible nonvolatile memorizer module comprises multiple storage unit.This memorizer control circuit unit comprises host interface, memory interface, memory management circuitry and error checking circuit.Host interface is in order to be electrically connected to host computer system.Memory interface is in order to be electrically connected to reproducible nonvolatile memorizer module.Memory management circuitry is electrically connected to host interface and memory interface, and wherein memory management circuitry is in order to send reading command sequence, and described reading command sequence is in order to read described storage unit, to obtain multiple position.Error checking circuit is electrically connected to described memory management circuitry and in order to obtain multiple reliability information, wherein each reliability information corresponds to one of them of institute's rheme.At this, described summation also in order to calculate in described reliability information the summation of the multiple reliability information meeting examination condition, and is added that balancing information is to obtain corresponding to the weight of first in institute's rheme with the first syndrome by error checking circuit.In addition, also in order to judge, whether rheme has at least one mistake to error checking circuit, if institute's rheme has at least one mistake, error checking circuit is also in order to perform iterative decoding procedures according to described weight.

In one example of the present invention embodiment, above-mentioned error checking circuit judges that the operation whether institute's rheme has at least one mistake comprises: error checking circuit performs odd-even check program to obtain the multiple syndromes comprising described first syndrome to institute's rheme, wherein each institute's rheme be correspond to described syndrome at least one of them, and judge whether institute's rheme has at least one mistake according to described syndrome.Described odd-even check program is performed by parity-check matrix, and described parity-check matrix comprises multiple restriction.The operation that above-mentioned error checking circuit calculates in described reliability information the summation of the described reliability information meeting described examination condition comprises: error checking circuit, according to the first restriction corresponding to described first syndrome in described restriction, determines the reliability information meeting described examination condition from described reliability information.

In one example of the present invention embodiment, above-mentioned first restriction comprises multiple element, and according to described first restriction, error checking circuit determines that from described reliability information the operation meeting the reliability information of described examination condition comprises: error checking circuit is multiple elements of " 1 " according to described element intermediate value, from described reliability information, determine the reliability information meeting described examination condition.

In one example of the present invention embodiment, described summation is added that described balancing information comprises with the operation of the weight of described first syndrome corresponding to described first to obtain by above-mentioned error checking circuit: described summation is added that described balancing information is to obtain the first appreciation information by error checking circuit, and by described first appreciation information divided by the second appreciation information with obtain correspond to described first with the weight of described first syndrome, wherein said second appreciation information is corresponding to described primary reliability information in described reliability information.

In one example of the present invention embodiment, above-mentioned error checking circuit also in order to select to correspond to the deputy reliability information in institute's rheme from the described reliability information meeting described examination condition, wherein said second is different from described first, and error checking circuit will be also in order to will be multiplied by Dynamic gene to obtain described balancing information corresponding to described deputy described reliability information.

One example of the present invention embodiment proposes a kind of memory storage apparatus, and it comprises connecting interface unit, reproducible nonvolatile memorizer module and memorizer control circuit unit.Reproducible nonvolatile memorizer module comprises multiple storage unit.Connecting interface unit is in order to be electrically connected to host computer system.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, and in order to send reading command sequence, wherein said reading command sequence in order to read described storage unit, to obtain multiple position.At this, memorizer control circuit unit is also in order to obtain multiple reliability information, and wherein each reliability information corresponds to one of them of institute's rheme.In addition, described summation also in order to calculate in described reliability information the summation of the multiple reliability information meeting examination condition, and is added that balancing information is to obtain corresponding to the weight of first in institute's rheme with the first syndrome by memorizer control circuit unit.Also in order to judge, whether rheme has at least one mistake to memorizer control circuit unit, and if institute's rheme has at least one mistake, and memorizer control circuit unit is also in order to perform iterative decoding procedures according to described weight.

In one example of the present invention embodiment, the operation whether above-mentioned memorizer control circuit unit judges institute rheme has at least one mistake comprises: memorizer control circuit unit performs odd-even check program to obtain the multiple syndromes comprising described first syndrome to institute rheme, wherein each institute's rheme be correspond to described syndrome at least one of them; And according to described syndrome, memorizer control circuit unit judges whether institute's rheme has at least one mistake.Described odd-even check program is performed by parity-check matrix, and described parity-check matrix comprises multiple restriction.The operation that above-mentioned memorizer control circuit unit calculates in described reliability information the summation of the described reliability information meeting described examination condition comprises: memorizer control circuit unit, according to the first restriction corresponding to described first syndrome in described restriction, determines the reliability information meeting described examination condition from described reliability information.

In one example of the present invention embodiment, above-mentioned first restriction comprises multiple element, and according to described first restriction, memorizer control circuit unit determines that from described reliability information the operation meeting the described reliability information of described examination condition comprises: memorizer control circuit unit is multiple elements of " 1 " according to described element intermediate value, from described reliability information, determine the reliability information meeting described examination condition.

In one example of the present invention embodiment, described summation is added that described balancing information comprises with the operation of the weight of described first syndrome corresponding to described first to obtain by above-mentioned memorizer control circuit unit: described summation is added that described balancing information is to obtain the first appreciation information by memorizer control circuit unit; And memorizer control circuit unit by described first appreciation information divided by one second appreciation information with obtain correspond to described first with the weight of described first syndrome, wherein said second appreciation information is corresponding to described primary reliability information in described reliability information.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit also in order to select to correspond to the deputy reliability information in institute's rheme from the described reliability information meeting described examination condition, and wherein said second is different from described first.Memorizer control circuit unit will be also in order to will be multiplied by Dynamic gene to obtain described balancing information corresponding to described deputy described reliability information.

In one example of the present invention embodiment, the above-mentioned value corresponding to described deputy described reliability information is minimum in the value of the described reliability information meeting described examination condition.

In one example of the present invention embodiment, the above-mentioned value corresponding to described deputy described reliability information is only greater than the value of the reliability information corresponding to described first in the described reliability information meeting described examination condition.

In one example of the present invention embodiment, the value of above-mentioned balancing information is positive correlation (positivecorrelation) in the row weight of the first restriction corresponding in parity-check matrix of described first syndrome.

Based on above-mentioned, when the position of reading from reproducible nonvolatile memorizer module exists mistake, one example of the present invention embodiment according to corresponding to each weighted value calculation check weight information, and can determine to upgrade which position thus.Particularly, exemplary embodiment of the present invention proposes coding/decoding method, memorizer control circuit unit and memory storage apparatus are according to corresponding to minimum value in the reliability information of current calculated position of the reliability information of the entirety of each, non-corresponding and the weighted value calculating each corresponding to the reliability information of current calculated position in each limit.Base this, effectively can increase the corrigendum ability of decoding.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.

Accompanying drawing explanation

Fig. 1 is the example schematic of host computer system shown by one example of the present invention embodiment and memory storage apparatus;

Fig. 2 is the example schematic of computer, input/output device and memory storage apparatus shown by one example of the present invention embodiment;

Fig. 3 is the example schematic of host computer system shown by one example of the present invention embodiment and memory storage apparatus;

Fig. 4 is the schematic block diagram that the memory storage apparatus shown in Fig. 1 is shown;

Fig. 5 is the schematic block diagram of the reproducible nonvolatile memorizer module shown by one example of the present invention embodiment;

Fig. 6 is the example schematic of the memory cell array shown by one example of the present invention embodiment;

Fig. 7 is the example schematic of the management reproducible nonvolatile memorizer module shown by one example of the present invention embodiment;

Fig. 8 is the schematic block diagram of the memorizer control circuit unit shown by one example of the present invention embodiment;

Fig. 9 is the example schematic of the parity-check matrix shown by one example of the present invention embodiment;

Figure 10 is the example schematic of the critical voltage distribution of SLC type flash memory module shown by one example of the present invention embodiment;

Figure 11 is the example schematic of the matrix multiple shown by one example of the present invention embodiment;

Figure 12 is the example schematic of the weight matrix shown by one example of the present invention embodiment;

Figure 13 is the example schematic of code word shown by one example of the present invention embodiment, reliability information, corresponding relation between parity-check matrix and syndrome;

Figure 14 is the example schematic of the weight calculated shown by one example of the present invention embodiment;

Figure 15 is the example schematic of the matrix multiple shown by one example of the present invention embodiment;

Figure 16 is the example schematic of the verification weight information shown by one example of the present invention embodiment;

Figure 17 is the process flow diagram of the coding/decoding method shown by one example of the present invention embodiment.

Description of reference numerals:

1000: host computer system;

1100: computer;

1102: microprocessor;

1104: random access memory;

1106: input/output device;

1108: system bus;

1110: data transmission interface;

1202: mouse;

1204: keyboard;

1206: display;

1208: printer;

1212:U dish;

1214: storage card;

1216: solid state hard disc;

1310: digital camera;

1312:SD card;

1314:MMC card;

1316: memory stick;

1318:CF card;

1320: embedded memory storage;

100: memory storage apparatus;

102: connecting interface unit;

104: memorizer control circuit unit;

106: reproducible nonvolatile memorizer module;

2202: memory cell array;

2204: character line control circuit;

2206: bit line control circuit;

2208: row decoder;

2210: data input/output (i/o) buffer;

2212: control circuit;

702: storage unit;

704: bit line;

706: character line;

708: common source line;

712,714: transistor;

400 (0) ~ 400 (N): entity program unit;

202: memory management circuitry;

204: host interface;

206: memory interface;

208: error checking circuit;

210: memory buffer;

212: electric power management circuit;

900: parity-check matrix;

1010,1020: distribution;

1001: read voltage;

1030: overlapping region;

1101: code word;

1103: reliability information vector;

1105: verification vector;

1200: weight matrix;

S1701, S1703, S1705, S1707, S1709, S1711, S1713: the step of coding/decoding method.

Embodiment

Generally speaking, memory storage apparatus (also claiming, storage system) comprises reproducible nonvolatile memorizer module and controller (also claiming, control circuit).Usual memory storage apparatus uses together with host computer system, data can be write to memory storage apparatus or read data from memory storage apparatus to make host computer system.

Fig. 1 is the example schematic of host computer system shown by one example of the present invention embodiment and memory storage apparatus.Fig. 2 is the example schematic of computer, input/output device and memory storage apparatus shown by one example of the present invention embodiment.

Please refer to Fig. 1, host computer system 1000 generally comprises computer 1100 and I/O (input/output; Be called for short I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (randomaccessmemory; Be called for short RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Fig. 2, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2, input/output device 1106 can also comprise other devices.

In an exemplary embodiment, memory storage apparatus 100 is electrically connected by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memory storage apparatus 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106 or read data from memory storage apparatus 100.Such as, memory storage apparatus 100 can be USB flash disk 1212, storage card 1214 or solid state hard disc (SolidStateDrive as shown in Figure 2; Be called for short SSD) the type nonvolatile memory storage of 1216 grades.

Fig. 3 is the example schematic of host computer system shown by one example of the present invention embodiment and memory storage apparatus.

Generally speaking, host computer system 1000 is any system that can coordinate to store data substantially with memory storage apparatus 100.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but in another exemplary embodiment, host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile memory storage is then its SD card 1312 used, mmc card 1314, memory stick (memorystick) 1316, CF card 1318 or embedded memory storage 1320 (as shown in Figure 3).Embedded memory storage 1320 comprises embedded multi-media card (EmbeddedMMC; Be called for short eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.

Fig. 4 is the schematic block diagram that the memory storage apparatus shown in Fig. 1 is shown.

Please refer to Fig. 4, memory storage apparatus 100 comprises connecting interface unit 102, memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106.

In this exemplary embodiment, connecting interface unit 102 is compatible to Serial Advanced Technology Attachment (SerialAdvancedTechnologyAttachment; Abbreviate SAT A) standard.But it must be appreciated, the present invention is not limited thereto, connecting interface unit 102 also can be meet parallel advanced technology annex (ParallelAdvancedTechnologyAttachment; Be called for short PATA) standard, Institute of Electrical and Electric Engineers (InstituteofElectricalandElectronicEngineers; Be called for short IEEE) 1394 standards, high-speed peripheral component connecting interface (PeripheralComponentInterconnectExpress; Be called for short PCIExpress) standard, USB (universal serial bus) (UniversalSerialBus; Be called for short USB) standard, secure digital (SecureDigital; Be called for short SD) interface standard, a hypervelocity generation (UltraHighSpeed-I; Be called for short UHS-I) interface standard, hypervelocity two generation (UltraHighSpeed-II; Be called for short UHS-II) interface standard, memory stick (MemoryStick; Be called for short MS) interface standard, multimedia storage card (MultiMediaCard; Be called for short MMC) interface standard, built-in multimedia storage card (EmbeddedMultimediaCard; Be called for short eMMC) interface standard, general flash memory (UniversalFlashStorage; Be called for short UFS) interface standard, compact flash (CompactFlash; Be called for short CF) interface standard, integrated device electronics interface (IntegratedDeviceElectronics; Be called for short IDE) standard or other be applicable to standard.Connecting interface unit 102 can be encapsulated in a chip with memorizer control circuit unit 104, or connecting interface unit 102 is laid in one to comprise outside the chip of memorizer control circuit unit 104.

Memorizer control circuit unit 104 in order to perform in the form of hardware or multiple logic gate of form of firmware implementation or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the running such as to erase.

Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and in order to data that host system 1000 writes.Reproducible nonvolatile memorizer module 106 can be single-order storage unit (SingleLevelCell; Be called for short SLC) NAND type flash memory module, multi-level cell memory (MultiLevelCell; Be called for short MLC) NAND type flash memory module (that is, the flash memory module of 2 bit data can be stored in a storage unit), Complex Order storage unit (TripleLevelCell; Be called for short TLC) NAND type flash memory module (that is, the flash memory module of 3 bit data can be stored in a storage unit), other flash memory module or other there is the memory module of identical characteristics.

Fig. 5 is the schematic block diagram of the reproducible nonvolatile memorizer module shown by one example of the present invention embodiment.Fig. 6 is the example schematic of the memory cell array shown by one example of the present invention embodiment.

Please refer to Fig. 5, reproducible nonvolatile memorizer module 106 comprises memory cell array 2202, character line control circuit 2204, bit line control circuit 2206, row decoder (columndecoder) 2208, data input/output (i/o) buffer 2210 and control circuit 2212.

In this exemplary embodiment, memory cell array 2202 can comprise storing multiple storage unit 702 of data, multiple selection grid leak pole (selectgatedrain; Be called for short SGD) transistor 712 and multiple selection grid source electrode (selectgatesource; Be called for short SGS) transistor 714 and connect the multiple bit lines 704 of this little storage unit, many character lines 706, with common source line 708 (as shown in Figure 6).Storage unit 702 is configured in bit line 704 with on the point of crossing of character line 706 with array way (or three-dimensional stacking mode).When receiving write instruction or reading command from memorizer control circuit unit 104, control circuit 2212 meeting control character line control circuit 2204, bit line control circuit 2206, row decoder 2208, data input/output (i/o) buffer 2210 writes data and reads data to memory cell array 2202 or from memory cell array 2202, wherein character line control circuit 2204 is in order to control the voltage being imparted to character line 706, bit line control circuit 2206 is in order to control the voltage being imparted to bit line 704, row decoder 2208 according to the row address in instruction to select corresponding bit line, and data input/output (i/o) buffer 2210 is in order to temporal data.

Each storage unit in reproducible nonvolatile memorizer module 106 is to store one or more position with the change of critical voltage.Specifically, an electric charge capture layer is had between the control gate (controlgate) of each storage unit and passage.By bestowing a write voltage to control gate, the amount of electrons of electric charge capture layer can be changed, thus change the critical voltage of storage unit.This change critical voltage program also referred to as " data are write to storage unit " or " sequencing storage unit ".Along with the change of critical voltage, each storage unit of memory cell array 2202 has multiple store status.And can judge storage unit belongs to which store status by reading voltage, obtaining one or more position that storage unit stores by this.

Fig. 7 is the example schematic of the management reproducible nonvolatile memorizer module shown by one example of the present invention embodiment.

Please refer to Fig. 7, the storage unit 702 of reproducible nonvolatile memorizer module 106 can form multiple entity program unit, and this little entity program unit can form multiple entity erased cell 400 (0) ~ 400 (N).Specifically, the storage unit on same character line can form one or more entity program unit.If each storage unit can store the position of more than 2, then the entity program unit on same character line can be classified as lower entity program unit and upper entity program unit.Such as, the LSB of each storage unit belongs to lower entity program unit, and the MSB of each storage unit belongs to entity program unit.In general, in MLCNAND type flash memory, the writing speed of lower entity program unit can be greater than the writing speed of entity program unit, or the fiduciary level of lower entity program unit is the fiduciary level higher than upper entity program unit.In this exemplary embodiment, entity program unit is the minimum unit of sequencing.That is, entity program unit is the minimum unit of write data.Such as, entity program unit is physical page or entity fan (sector).If entity program unit is physical page, then each entity program unit generally includes data bit district and redundant digit district.Data bit district comprises multiple entity fan, and in order to store the data of user, and redundant digit district is in order to the data (such as, error correcting code) of storage system.In this exemplary embodiment, each data bit district comprises 32 entity fans, and the size of an entity fan is 512 hyte (byte; Be called for short B).But, in other exemplary embodiment, also can comprise in data bit district 8,16 or number more or less entity fan, the present invention do not limit entity fan size and number.On the other hand, entity erased cell is the least unit of erasing.Also namely, each entity erased cell contain minimal amount in the lump by the storage unit of erasing.Such as, entity erased cell is physical blocks.

Fig. 8 is the schematic block diagram of the memorizer control circuit unit shown by one example of the present invention embodiment.

Please refer to Fig. 8, memorizer control circuit unit 104 comprises memory management circuitry 202, host interface 204, memory interface 206 and error checking circuit 208.

Memory management circuitry 202 is in order to the overall operation of control store control circuit unit 104.Specifically, memory management circuitry 202 has multiple steering order, and when memory storage apparatus 100 operates, this little steering order can be performed to carry out data write, read and the running such as to erase.When the operation of memory management circuitry 202 is below described, be equal to the operation that memorizer control circuit unit 104 is described, below and repeat no more.

In this exemplary embodiment, the steering order of memory management circuitry 202 carrys out implementation with form of firmware.Such as, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and this little steering order is burned onto in this ROM (read-only memory).When memory storage apparatus 100 operates, this little steering order can by microprocessor unit perform to carry out data write, read and the running such as to erase.

In another exemplary embodiment, the steering order of memory management circuitry 202 also can procedure code form be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of reproducible nonvolatile memorizer module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has boot code (bootcode), and when memorizer control circuit unit 104 is enabled, microprocessor unit first can perform this boot code and the steering order be stored in reproducible nonvolatile memorizer module 106 is loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate this little steering order with carry out data write, read and the running such as to erase.

In addition, in another exemplary embodiment, the steering order of memory management circuitry 202 also an example, in hardware can carry out implementation.Such as, memory management circuitry 202 comprises microcontroller, Memory Management Unit, storer writing unit, storer reading unit, storer erased cell and data processing unit.Memory Management Unit, storer writing unit, storer reading unit, storer erased cell and data processing unit are electrically connected to microcontroller.Wherein, Memory Management Unit is in order to manage the entity erased cell of reproducible nonvolatile memorizer module 106; Storer writing unit is in order to assign write instruction data to be write in reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Storer reading unit is in order to assign reading command to read data from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Storer erased cell is in order to assign instruction of erasing data to be erased from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; And data processing unit is in order to the data processed for writing to reproducible nonvolatile memorizer module 106 and the data read from reproducible nonvolatile memorizer module 106.

Host interface 204 is electrically connected to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 also can be compatible to PATA standard, IEEE1394 standard, PCIExpress standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other data transmission standards be applicable to.

Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 206.

Error checking circuit 208 is electrically connected to memory management circuitry 202 and in order to execution error checking routine to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, error checking circuit 208 can be that the data of this write instruction corresponding produce corresponding error correcting code (errorcorrectingcode; Be called for short ECC) and/or error-detecging code (errordetectingcode; Be called for short EDC), and the data of this write instruction corresponding can write in reproducible nonvolatile memorizer module 106 with corresponding error correcting code or error-detecging code by memory management circuitry 202.Afterwards, can read error correcting code corresponding to these data or error-detecging code when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, and error checking circuit 208 can according to this error correcting code or error-detecging code to read data execution error checking routine simultaneously.

In an exemplary embodiment, memorizer control circuit unit 104 also comprises memory buffer 210 and electric power management circuit 212.

Memory buffer 210 is electrically connected to memory management circuitry 202 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of reproducible nonvolatile memorizer module 106.

Electric power management circuit 212 is electrically connected to memory management circuitry 202 and in order to the power supply of control store memory storage 100.

In this exemplary embodiment, error checking circuit 208 use low density parity check code (lowdensityparitycode; Be called for short LDPC).But in another exemplary embodiment, what error checking circuit 208 used also can be BCH code, convolution code (convolutionalcode), turbine code (turbocode), but is not limited thereto.

In this exemplary embodiment, according to a low-density parity, error checking circuit 208 can check that algorithm carrys out encoding and decoding.Checking in correcting code at low-density parity, is define effective code word by a parity-check matrix.Below parity-check matrix is labeled as matrix H, and a code word is labeled as CW.According to following equation (1), if parity-check matrix H is null vector with being multiplied of code word CW, represent that code word CW is effective code word.Wherein operator represent the matrix multiple of mould 2 (mod2).In other words, the kernel (nullspace) of matrix H just contains all effective code words.But the present invention does not limit the content of code word CW.Such as, code word CW also can comprise the error correcting code or error-detecging code that produce by any algorithm.

$H\⊗{\mathrm{CW}}^T=0...\left(1\right)$

Wherein the dimension of matrix H is that m-takes advantage of-n (m-by-n), and the dimension of code word CW is that 1-takes advantage of-n.M and n is positive integer.Include information bit and parity bit in code word CW, namely code word CW can be expressed as [MP], and wherein vector M is made up of information bit, and vectorial P is made up of parity bit.The dimension of vector M is that 1-takes advantage of-(n-m), and the dimension of vectorial P is 1-takes advantage of-m.Below information bit and parity bit are referred to as data bit.In other words, have n data bit in code word CW, wherein the length of information bit is (n-m) position, and the length of parity bit is m position, and namely the code check (coderate) of code word CW is (n-m)/n.

In general can use one when encoding and produce matrix (being labeled as G below), make all can meet following equation (2) for arbitrary vector M.The dimension wherein producing matrix G is (n-m)-take advantage of-n.

$M\⊗G=\left[\mathrm{M\; P}\right]=\mathrm{CW}...\left(2\right)$

The code word CW produced by equation (2) is effective code word.Therefore equation (2) can be substituted into equation (1), obtain following equation (3) by this.

$H\⊗G^T\⊗M^T=0...\left(3\right)$

Because vector M can be arbitrary vector, therefore following equation (4) inherently meets.That is, after decision parity-check matrix H, corresponding generation matrix G also can be determined.

$H\⊗G^T=0...\left(4\right)$

When a decoding code word CW, first can perform an odd-even check program to the data bit in code word, such as, parity-check matrix H and code word CW phase are multiplied by generation vector (being labeled as S below, as Suo Shi following equation (5)).If vectorial S is null vector, then can direct output codons CW.If vectorial S is not null vector, then represent that code word CW is not effective code word.

$H\⊗{\mathrm{CW}}^T=S...\left(5\right)$

The dimension of vector S is that m-takes advantage of-1, and wherein each element is also referred to as syndrome (syndrome).If code word CW is not effective code word, then error checking circuit 208 can perform a decoding program, to attempt correcting the error bit in code word CW.In an exemplary embodiment, the decoding program performed by error checking circuit 208 is an iteration (iteration) decoding program.That is, the program of decoding can constantly repeat, and arrives a predetermined threshold until successfully solve code word or perform number of times.

Fig. 9 is the example schematic of the parity-check matrix shown by one example of the present invention embodiment.

Please refer to Fig. 9, the dimension of parity-check matrix 900 is that 4-takes advantage of-9, but the present invention does not limit positive integer m and n is how many.Each row (row) of parity-check matrix 900 also represent a restriction (constraint).Such as, the first row of parity-check matrix 900 represents first respectively to the 4th row and is limited to the 4th restriction.Each restriction in parity-check matrix 900 comprises multiple element.With first of parity-check matrix 900 row (namely, first restriction) be example, if some code words are effective code word (validcodeword), then by after in this code word, the addition of mould 2 (modulo-2) is done in the 1st, 2,3 and the 4th position, can obtain put in place " 0 ".Have in this field and usually know that the knowledgeable will be understood that and how to encode by parity-check matrix 900, just repeat no more at this.In addition, parity-check matrix 900 is only an example matrix, and is not used to limit the present invention.

When multiple position will be write to reproducible nonvolatile memorizer module 106 by memory management circuitry 202, error checking circuit 208 can all produce m corresponding parity bit to every (n-m) individual position (that is, information bit) for being written into.Next, memory management circuitry 202 can write to reproducible nonvolatile memorizer module 106 using this n position as a code word.

Figure 10 is the example schematic of the critical voltage distribution of SLC type flash memory module shown by one example of the present invention embodiment.

Please refer to Figure 10, the critical voltage of transverse axis representative memory cell, and longitudinal axis representative memory cell number.Such as, Figure 10 is the critical voltage representing each storage unit in an entity program unit.In this hypothesis when the critical voltage of some storage unit is when dropping on distribution 1010, what this storage unit stored is position " 1 "; On the contrary, if the critical voltage of some storage unit is when dropping on distribution 1020, what this storage unit stored is position " 0 ".It is worth mentioning that, this exemplary embodiment is for SLC type flash memory module, therefore critical voltage be distributed with two kinds may.But, in other exemplary embodiment, the distribution of critical voltage may four kinds, eight kinds or other arbitrarily may, and read voltage can between any two distributions.In addition, the present invention do not limit yet each distribution representated by position.

When reading data from reproducible nonvolatile memorizer module 106, memory management circuitry 202 can send a reading command sequence to reproducible nonvolatile memorizer module 106.This reading command sequence comprises one or more instruction or procedure code, and in order to indicate multiple storage unit in reading entity program unit to obtain multiple position.Such as, the multiple storage unit in an entity program unit are read according to reading voltage 1001.If the critical voltage of some storage unit is less than this read voltage, then this storage unit meeting conducting, and memory management circuitry 202 can read position " 1 ".On the contrary, if the critical voltage of some storage unit is greater than this read voltage, then this storage unit can not conducting, and memory management circuitry 202 can read position " 0 ".

It should be noted that distribution 1010 comprises an overlapping region 1030 with distribution 1020.Overlapping region 1030 indicates that what store in some storage unit should be position " 1 " (belonging to distribution 1010), but its critical voltage is greater than and reads voltage 1001; Or, have what store in some storage unit should be position " 0 " (belonging to distribution 1020), but its critical voltage be less than and reads voltage 1001.In other words, in the position of reading, have part position can be wrong.In another exemplary embodiment, also can read out multiple position from a storage unit, the present invention is not limited.In addition, reading once also can be the storage unit of multiple storage unit in reading entity fan or any amount, and the present invention is not limited.

In this exemplary embodiment, when memory management circuitry 202 reads n position (forming a code word) from reproducible nonvolatile memorizer module 106, memory management circuitry 202 also can obtain the reliability information corresponding to each.At this, reliability information represents that corresponding position is decoded as position " 1 " or the probability of " 0 " (or claiming confidence degree).Particularly, when adopting different algorithms, the value corresponding to the reliability information of each obtained can not be identical.Such as, error checking circuit 208 can adopt summation-product algorithm (Sum-ProductAlgorithm), minimum value-summation algorithm (Min-SumAlgorithm) or bit flipping algorithm (bit-flippingAlgorithm), and the present invention does not limit to adopt which kind of algorithm.

Error checking circuit 208 can judge whether these positions have at least one mistake.Such as, in this exemplary embodiment, error checking circuit 208 can perform odd-even check programs to obtain multiple syndrome (syndrome) to these, wherein each be correspond to these syndromes at least one of them.In other words, these syndromes can form above-mentioned vectorial S.In an exemplary embodiment, above-mentioned vectorial S is also referred to as verification vector.According to the multiple syndromes in the vectorial S of verification, error checking circuit 208 can judge whether these positions have at least one mistake.Such as, if each syndrome verified in vectorial S is " 0 ", error checking circuit 208 can judge that these positions do not have any mistake, and judges that the code word be made up of these is effective code word; If one or more syndrome verified in vectorial S is " 1 ", then error checking circuit 208 can judge that these positions have at least one mistake, and judges that the code word be made up of these is not effective code word.

Figure 11 is the example schematic of the matrix multiple shown by one example of the present invention embodiment.

Please refer to Figure 11, the result that parity-check matrix 900 is multiplied with code word 1101 verifies vector 1105.Each in code word 1101 corresponds at least one syndrome in verification vector 1105.For example, the position V in code word 1101 ₁(corresponding to the first row (column) in parity-check matrix 900) corresponds to syndrome S ₁and S ₂; Position V ₂(corresponding to the second row in parity-check matrix 900) corresponds to syndrome S ₁and S ₃, by that analogy.If position V ₁there occurs mistake, then syndrome S ₁and S ₂may be " 1 "; If position V ₂there occurs mistake, then syndrome S ₁and S ₃may be " 1 ", by that analogy.In addition, the first restriction in parity-check matrix 900 corresponds to syndrome S ₁, the second restriction in parity-check matrix 900 corresponds to syndrome S ₂, the 3rd restriction in parity-check matrix 900 corresponds to syndrome S ₃, and the 4th restriction in parity-check matrix 900 corresponds to syndrome S ₄.

If the position V in code word 1101 ₁~ V ₉there is no mistake, then the position V in error checking circuit 208 meeting output codons 1101 ₁~ V ₉.If position V ₁~ V ₉have at least one mistake, error checking circuit 208 can contraposition V ₁~ V ₉perform an iterative decoding procedures to obtain multiple decoded bit.Particularly, before execution iterative decoding procedures, error checking circuit 208 can obtain corresponding to each weight with each syndrome.These weights can utilize a weight matrix to represent.These weights also can be recorded in a look-up table.Error checking circuit 208 can perform iterative decoding procedures according to this little weight.Or in an exemplary embodiment, obtain and correspond to each operation with the weight of each syndrome, also can be considered as is the part of iterative decoding procedures, and the present invention is not limited.

Figure 12 is the example schematic of the weight matrix shown by one example of the present invention embodiment.

Please refer to Figure 12, in weight matrix 1200, describe weights W _1,1~ W _4,9.Wherein, weights W _1,1correspond to position V ₁with syndrome S ₁; Weights W _1,2correspond to position V ₂with syndrome S ₁; Weights W _2,1correspond to position V ₁with syndrome S ₂, by that analogy.The matrix size of weight matrix 1200 is consistent with parity-check matrix 900.Such as, weight matrix 1200 also has m row and n row.

Error checking circuit 208 can calculate in obtained reliability information the summation of the multiple reliability information meeting an examination condition, and this summation is added a corresponding balancing information is to obtain a weight in weight matrix 1200.Below will to calculate weights W _1,1be described as example.

Figure 13 is the example schematic of code word shown by one example of the present invention embodiment, reliability information, corresponding relation between parity-check matrix and syndrome.

Please refer to Figure 13, correspond to each V in code word 1101 in this hypothesis ₁~ V ₉reliability information be respectively " 0.6 ", " 0.8 ", "-0.2 " in reliability information vector 1103, " 1.3 ", "-1.5 ", " 0.3 ", "-1.2 ", " 0.4 " and " 0.1 ".But, be only an example array at this reliability information vector 1103, and be not used to limit the present invention.In this exemplary embodiment, each reliability information in reliability information vector 1103 can be taken absolute value.Therefore, the reliability information in reliability information vector 1103 becomes " 0.6 ", " 0.8 ", " 0.2 ", " 1.3 ", " 1.5 ", " 0.3 ", " 1.2 ", " 0.4 " and " 0.1 ".If the absolute value corresponding to the reliability information of some positions is larger, then represent that the probability that this makes a mistake is lower; If the absolute value corresponding to the reliability information of some positions is less, then represent that the probability that this makes a mistake is higher.But in another exemplary embodiment, also can do arbitrary logical operation to each reliability information in reliability information vector 1103, the present invention is not limited.In addition, each reliability information in reliability information vector 1103 corresponds respectively to an element in each restriction of parity-check matrix 900.Such as, as shown in figure 13, " 0.6 " in reliability information vector 1103 corresponds to first to be limited to first element of coming from left side number in the 4th restriction, and " 0.8 " in reliability information vector 1103 corresponds to first to be limited to second element of coming from left side number in the 4th restriction, by that analogy.Due to the weights W in weight matrix 1200 _1,1correspond to the position V in code word 1101 ₁with the syndrome S in verification vector 1105 ₁, therefore in following exemplary embodiment, the position V in code word 1101 ₁also referred to as first, and the syndrome S in verification vector 1105 ₁also referred to as the first syndrome, so that illustrate how to calculate weights W _1,1.

In calculating weights W _1,1time, error checking circuit 208 according to the first restriction in parity-check matrix 900, can determine the multiple reliability information meeting examination condition from reliability information vector 1103.Such as, in the element included by error checking circuit 208 can limit according to first, its value is multiple elements of " 1 ", determines the multiple reliability information meeting this examination condition from reliability information vector 1103.Such as, in this exemplary embodiment, the element value of front four elements of coming from left side number in the first restriction is " 1 ", and the reliability information therefore meeting examination condition in reliability information vector 1103 is " 0.6 ", " 0.8 ", " 0.2 " and " 1.3 ".Afterwards, error checking circuit 208 can obtain the summation of the reliability information meeting this examination condition for " 2.9 ".

In this exemplary embodiment, each restriction corresponds to a balancing information.Above-mentioned summation can be added that the balancing information limited corresponding to first is to obtain weights W by error checking circuit 208 _1,1.More specifically, above-mentioned summation can be added that balancing information corresponding to the first restriction is to obtain the first appreciation information by error checking circuit 208, and by the first appreciation information divided by one second appreciation information to obtain weights W _1,1.

Error checking circuit 208 can meet the reliability information of examination condition from above-mentioned the reliability information selecting to correspond to another one (also referred to as second).Wherein, this second is different from first.Also, namely, in this exemplary embodiment, this second is a V ₂~ V ₄one of them.Particularly, in this exemplary embodiment, the selected value corresponding to deputy reliability information allly meets in the value of the reliability information of examination condition minimum, or the value corresponding to deputy reliability information meets all the value being only greater than the reliability information corresponding to first in the reliability information of examination condition.Such as, in this exemplary embodiment, first (that is, position V ₁) corresponding to the value of reliability information be " 0.6 ", therefore, error checking circuit 208 can select its value be that the reliability information of " 0.2 " is as corresponding to deputy reliability information from " 0.8 ", " 0.2 ", " 1.3 ".That is, in this exemplary embodiment, second is position V ₃, and be " 0.2 " corresponding to deputy reliability information.But in another example is implemented, second also can be selected according to arbitrary condition, and the present invention is not limited.Such as, in an exemplary embodiment, also the reliability information meeting examination condition can be inputted a look-up table or an algorithm, and using the output of this look-up table or this algorithm as corresponding to deputy reliability information.

In this exemplary embodiment, each restriction corresponds to a Dynamic gene α _m.Such as, α ₁correspond to the first restriction, α ₂correspond to the second restriction, α ₃correspond to the 3rd restriction, and α ₄correspond to the 4th restriction.After acquisition corresponds to deputy reliability information, error checking circuit 208 can will be multiplied by Dynamic gene α corresponding to deputy reliability information ₁to obtain the balancing information corresponding to the first restriction.By this, the value of the summation of the reliability information meeting examination condition and balancing information can be made suitable, avoid the value because of balancing information too little and make it be left in the basket.It is worth mentioning that, in this exemplary embodiment, Dynamic gene α _mbe integer or the real number being greater than " 1 ".But, in another exemplary embodiment, Dynamic gene α _malso can be arbitrary real number, the present invention not be limited.In addition, in another exemplary embodiment, Dynamic gene α _malso can be " 1 ".In this exemplary embodiment, suppose Dynamic gene α ₁for " 11.36 ", then error checking circuit 208 can obtain the first appreciation information for " 5.172 ".In addition, error checking circuit 208 meeting will corresponding to first (that is, position V ₁) reliability information as the second appreciation information.Also, namely, in this exemplary embodiment, the second appreciation information is " 0.6 ".By this, by by the first appreciation information divided by the second appreciation information, error checking circuit 208 can obtain weights W _1,1for " 8.62 ".Or in an exemplary embodiment, error checking circuit 208 can obtain the weights W in the weight matrix 1200 of Figure 12 by following equation (6) _1,1~ W _4,9.

$W_{m,n}=\frac{\underset{i\∈N\left(m\right)}{\mathrm{\Σ}}\left|y_i\right|+{\mathrm{\α}}_m*y_{m,n}^{\min }}{\left|y_n\right|}...\left(6\right)$

Wherein, for basis corresponds to the summation meeting the reliability information of examination condition of m restriction, be the first appreciation information, | y _n| be the second appreciation information, for corresponding to deputy reliability information, and for corresponding to the balancing information of m restriction.

In an exemplary embodiment, the value corresponding to the balancing information of m restriction is the row weight being positively correlated with m restriction.Such as, the value corresponding to the balancing information of the first restriction is the row weight being positively correlated with the first restriction; Value corresponding to the balancing information of the second restriction is the row weight being positively correlated with the second restriction, by that analogy.For example, the number that error checking circuit 208 can be the element of " 1 " according to the first restriction intermediate value decides the row weight of the first restriction.Such as, in the exemplary embodiment of Figure 13, have the value of four elements to be " 1 " in the first restriction, therefore error checking circuit 208 can determine that the row weight of the first restriction is for " 4 ".By that analogy, the row weight of the second restriction is " 6 ", and the row weight of the 3rd restriction is " 6 ", and the row weight of the 4th restriction is " 4 ".In addition, in another exemplary embodiment, the value of balancing information corresponding to m restriction also can be negative about or uncorrelated in the row weight of m restriction, the present invention is not limited.

In an exemplary embodiment, the row weight that m limits can be multiplied by an enlargement factor to obtain the Dynamic gene α corresponding to m restriction by error checking circuit 208 _m.Such as, the row weight that first limits can be multiplied by an enlargement factor to obtain Dynamic gene α by error checking circuit 208 ₁.Such as, error checking circuit 208 can calculate a mean value (also referred to as the first mean value) of reliability information all in reliability information vector 1103, and according to each restriction in parity-check matrix 900, meet from correspondence the minimum value and sub-minimum that obtain reliability information the reliability information of examination condition.Such as, minimum value and sub-minimum that error checking circuit 208 can obtain the reliability information corresponding to the first restriction are respectively " 0.2 " and " 0.6 ", minimum value and sub-minimum corresponding to the reliability information of the second restriction are respectively " 0.2 " and " 0.3 ", minimum value and sub-minimum corresponding to the reliability information of the 3rd restriction are respectively " 0.1 " and " 0.3 ", and correspond to the minimum value of reliability information of the 4th restriction and sub-minimum is respectively " 0.1 " and " 0.2 ".Afterwards, error checking circuit 208 can calculate the mean value (also referred to as the second mean value) after these minimum value and these sub-minimums add up, and by the first mean value divided by the second mean value to obtain this enlargement factor.In this exemplary embodiment, the enlargement factor that the row weight that each m limits is multiplied by is identical.But in another exemplary embodiment, the enlargement factor that the row weight that each m limits is multiplied by also can be different.In addition, in another exemplary embodiment, the minimum value of reliability information and sub-minimum also can be select with arbitrary rule, and the present invention is not limited.Or in an exemplary embodiment, error checking circuit 208 also can obtain Dynamic gene α by following equation (7) _m.

${\mathrm{\α}}_m=\mathrm{row}\_\mathrm{weight}\left(m\right)\×\frac{\mathrm{mean}\left(\right|y\left|\right)}{\mathrm{mean}\left(\right|y^{\min }\left|\right)}...\left(7\right)$

Wherein, row_weight (m) is the row weight of m restriction in parity-check matrix 900, mean (| y|) be above-mentioned first mean value, and mean (| y ^min|) be above-mentioned second mean value.Such as, in this exemplary embodiment, first mean value be " 0.71 " (namely, (0.6+0.8+0.2+1.3+1.5+0.3+1.2+0.4+0.1)/9=0.71), second mean value is " 0.25 " (that is, (0.2+0.2+0.1+0.1+0.6+0.3+0.3+0.2)/9=0.25).Therefore, can obtain Dynamic gene α 1 ~ α 4 is " 11.36 ", " 17.04 ", " 11.36 " and " 17.04 " respectively.

According to aforesaid operations, error checking circuit 208 can obtain the weights W 1,1 ~ W4,9 in the weight matrix 1200 of Figure 12 respectively.Such as, in this exemplary embodiment, in calculating weights W 2, when 1, first is a V1, and second is a V3.Error checking circuit 208 can according to the second restriction in parity-check matrix 900, the multiple reliability information determining to meet examination condition are " 0.6 ", " 0.2 ", " 1.3 ", " 1.5 ", " 0.3 " and " 1.2 " and its summation is " 5.1 ".Then, suppose that Dynamic gene α 2 is " 17.04 ", error checking circuit 208 can obtain the first appreciation information for " 8.508 " (namely, 5.1+ (17.04 × 0.2)), second appreciation information is " 0.6 " (that is, corresponding to primary reliability information), and weights W 2,1 is " 14.18 " (that is, 8.508/0.6=14.18).In weight matrix 1200 remaining weight calculating can the rest may be inferred, not in this to go forth.

Figure 14 is the example schematic of the weight calculated shown by one example of the present invention embodiment.

Please refer to Figure 14, in the first restriction of weight matrix 1200, corresponding to the weights W 1 of position V1 and syndrome S1,1 is " 8.62 ", and the weights W 1,2 corresponding to position V2 and syndrome S1 is " 6.47 ", corresponding to the weights W 1 of position V3 and syndrome S1,3 is " 48.58 ", and the weights W Isosorbide-5-Nitrae corresponding to position V4 and syndrome S1 is " 3.45 ".In the second restriction of weight matrix 1200, the weights W 2,1 corresponding to position V1 and syndrome S2 is " 14.18 ", weights W 2,3 corresponding to position V3 and syndrome is " 51.06 ", corresponding to the weights W 2 of position V4 and syndrome S2,4 is " 6.54 ", weights W 2,5 corresponding to position V5 and syndrome S2 is " 5.67 ", corresponding to the weights W 2 of position V6 and syndrome S2,6 is " 28.36 ", and the weights W 2,7 corresponding to position V7 and the second syndrome S2 is " 7.09 ", by that analogy.It is worth mentioning that, in this exemplary embodiment, it is the element of " 0 " that error checking circuit 208 may correspond to its value in parity-check matrix 900, the weight of part in weight matrix 1200 is set to " 0 ".

Figure 15 is the example schematic of the matrix multiple shown by one example of the present invention embodiment.

Please refer to Figure 15, in iterative decoding procedures, error checking circuit 208 can obtain the verification weight information of V1 ~ V9 according to above-mentioned syndrome and the weight calculated.For example, each syndrome can be multiplied by a weight by error checking circuit 208, and the result of total check and multiplied by weight is to obtain verification weight information.Such as, the verification weight information of position V1 can equal W1,1S1+W2,1S2, wherein weights W 1, and 1 and W2,1 is " 8.62 " and " 14.18 " in above-mentioned Figure 14.In this exemplary embodiment, error checking circuit 208 can be the value of weight that this syndrome is decided to correspond in " 1 " or " 0 " be is greater than 0 or be less than 0 according to a syndrome.Such as, if a syndrome is " 1 ", then the weight corresponding to this syndrome can be multiplied by " 1 "; If a syndrome is " 0 ", then the weight corresponding to this syndrome can be multiplied by "-1 ".To it should be noted that at this to the addition that syndrome S1 ~ S4 does it is general addition, instead of the addition of mould 2 (modulo-2).In other words, error checking circuit 208 can obtain verification weight information corresponding to position V1 ~ V9 by following equation (8).

$E_n=\underset{m\∈N\left(n\right)}{\mathrm{\Σ}}(2s_m-1)\left(\frac{\underset{m\∈N\left(n\right)}{\mathrm{\Σ}}\left|y_i\right|+{\mathrm{\α}}_m*y_{m,n}^{\min }}{\left|y_n\right|}\right)...\left(8\right).$

Wherein, vectorial E _nnamely can be used to represent each V ₁~ V ₉verification weight information.

Error checking circuit 208 can according to position V ₁~ V ₉verification weight information overturn (flip) these at least one of them.Such as, some or multiple position can be turned into " 0 " from " 1 " or be turned into " 1 " from " 0 " by error checking circuit 208.In an exemplary embodiment, the operation of above-mentioned flip bit is also referred to as bit flipping (bitflipping).Specifically, in iterative decoding procedures each time, only have a position at most in a code word and be reversed.Such as, the value of the verification weight information of this position be reversed can be greater than the value of the verification weight information of the position that other are not reversed.In addition, in another exemplary embodiment, error checking circuit 208 can judge whether the verification weight information of each in code word 1101 meets a weight condition.Such as, error checking circuit 208 can judge whether the value of the verification weight information of each is greater than a threshold value.If when the value of the verification weight information of some positions is greater than this threshold value, then error checking circuit 208 can judge that this verification weight information meets weight condition, and overturns this position.In other words, in an exemplary embodiment, the verification weight information of the position be reversed is the verification weight information meeting weight condition.

Figure 16 is the example schematic of the verification weight information shown by one example of the present invention embodiment.

Please refer to Figure 16, suppose the position V in code word 1101 ₁~ V ₉" 1 ", " 1 ", " 0 ", " 1 ", " 0 ", " 1 ", " 0 ", " 0 " and " 1 " respectively, the syndrome S in verification vector 1105 ₁~ S ₄be " 1 ", " 0 ", " 1 " and " 0 " respectively, then according to equation (8), error checking circuit 208 can obtain vectorial E _n, described vectorial E _nin order to represent position V ₁~ V ₉verification weight information be "-5.56 ", " 13.98 ", "-13.16 ", "-3.09 ", "-1.67 ", "-15.47 ", "-0.29 ", " 9.67 " and " 61.4 " respectively.In this exemplary embodiment, error checking circuit 208 can select after taking absolute value this bit it is worth maximum verification weight information (that is, " 15.47 ") in verification weight information, and by the position V of this verification weight information corresponding ₆upset.Then, this iterative decoding procedures can export the code word of another tool multiple.Such as, these positions can be " 1 ", " 1 ", " 0 ", " 1 ", " 0 ", " 0 ", " 0 ", " 0 " and " 1 " respectively.Then, error checking circuit 208 can judge whether these positions have mistake again.If do not have mistake, error checking circuit 208 can export these positions.If wrong, error checking circuit 208 can determine it is iterative decoding procedures or the stopping decoding that will perform another time.

In this exemplary embodiment, if there is mistake in error checking circuit 208 decision codeword 1101, then error checking circuit 208 counting one iterations, such as, adds 1 by iterations, and judges whether the iterations after counting reaches a termination number of times.At this, stop number of times is such as 30 times or more or less.If the iterations after counting reaches termination number of times, then error checking circuit 208 can judge to decode unsuccessfully, and stops decoding.If the iterations after counting does not reach termination number of times, then error checking circuit 208 can perform the iterative decoding procedures of another time.

Figure 17 is the process flow diagram of the coding/decoding method shown by one example of the present invention embodiment.

Please refer to Figure 17, first, in step S1701, send a reading command sequence, wherein said reading command sequence is in order to read multiple storage unit to obtain multiple position.In step S1703, obtain the reliability information corresponding to each.Then, in step S1705, the summation of the multiple reliability information meeting examination condition is calculated in described reliability information.In step S1707, described summation is added a balancing information is to obtain corresponding to the weight of first in institute's rheme with the first syndrome.Afterwards, in step S1709, judge whether institute's rheme has at least one mistake.If institute's rheme has described at least one mistake, in step S1711, perform iterative decoding procedures according to described weight.If institute's rheme does not have described mistake, in step S1713, export institute's rheme.

But in Figure 17, each step has described in detail as above, just repeats no more at this.It should be noted that in Figure 17, each step can implementation be multiple procedure code or circuit, the present invention is also not subject to the limits.In addition, the method for Figure 17 above embodiment of can arranging in pairs or groups uses, and also can be used alone, the present invention is also not subject to the limits.

In sum, when the position of reading from reproducible nonvolatile memorizer module exists mistake, the coding/decoding method of exemplary embodiment of the present invention, memorizer control circuit unit and memory storage apparatus can give the weighted value corresponding to the weight of coordination and different check is unsuitable in code word.By this, can increase and carry out the decoding efficiency of decoding according to verification weight information.

Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims (24)

1. a coding/decoding method, for reproducible nonvolatile memorizer module, it is characterized in that, this reproducible nonvolatile memorizer module comprises multiple storage unit, this coding/decoding method comprises:

Send reading command sequence, wherein this reading command sequence is in order to read those storage unit, to obtain multiple position;

Obtain multiple reliability information, wherein each those reliability information corresponds to those one of them;

Calculate in those reliability information the summation of the multiple reliability information meeting examination condition;

This summation is added balancing information is to obtain corresponding to the weight of first in those with the first syndrome;

Judge whether those positions have at least one mistake; And

If those positions have this at least one mistake, perform iterative decoding procedures according to this weight.

2. coding/decoding method according to claim 1, is characterized in that, judges whether those positions have this at least one wrong step and comprise:

Odd-even check programs are performed to obtain the multiple syndromes comprising this first syndrome to those, wherein each those be correspond to those syndromes at least one of them; And

Judge whether those positions have this at least one mistake according to those syndromes,

Wherein this odd-even check program is performed by parity-check matrix, and this parity-check matrix comprises multiple restriction,

The step wherein calculating this summation of those reliability information meeting this examination condition in those reliability information comprises:

According to the first restriction corresponding to this first syndrome in those restrictions, from those reliability information, determine those reliability information meeting this examination condition.

3. coding/decoding method according to claim 2, is characterized in that, this first restriction comprises multiple element, and from those reliability information, determines that the step meeting those reliability information of this examination condition comprises according to this first restriction:

According to multiple elements that those element intermediate values are " 1 ", from those reliability information, determine those reliability information meeting this examination condition.

4. coding/decoding method according to claim 1, is characterized in that, this summation is added this balancing information comprises with the step of this weight of this first syndrome corresponding to this first to obtain:

This summation is added this balancing information is to obtain the first appreciation information; And

By this first appreciation information divided by the second appreciation information with obtain correspond to this first with this weight of this first syndrome, wherein this second appreciation information is corresponding to this primary reliability information in those reliability information.

5. coding/decoding method according to claim 1, is characterized in that, also comprises:

Select to correspond to the deputy reliability information in those from those reliability information meeting this examination condition, wherein this second is different from this first; And

Dynamic gene will be multiplied by obtain this balancing information corresponding to this this reliability information deputy.

6. coding/decoding method according to claim 5, is characterized in that, the value corresponding to this this reliability information deputy is minimum in the value of those reliability information meeting this examination condition.

7. coding/decoding method according to claim 5, is characterized in that, the value corresponding to this this reliability information deputy is the value being only greater than the reliability information corresponding to this first in those reliability information meeting this examination condition.

8. coding/decoding method according to claim 1, is characterized in that, the value of this balancing information is the row weight being positively correlated with the first corresponding in parity-check matrix restriction of this first syndrome.

9. a memorizer control circuit unit, for reproducible nonvolatile memorizer module, is characterized in that, this reproducible nonvolatile memorizer module comprises multiple storage unit, and this memorizer control circuit unit comprises:

Host interface, in order to be electrically connected to host computer system;

Memory interface, in order to be electrically connected to this reproducible nonvolatile memorizer module;

Memory management circuitry, is electrically connected to this host interface and this memory interface, and in order to send reading command sequence, wherein this reading command sequence is in order to read those storage unit, to obtain multiple position; And

Error checking circuit, is electrically connected to this memory management circuitry, and in order to obtain multiple reliability information, wherein each those reliability information corresponds to those one of them;

This error checking circuit also in order to calculate in those reliability information the summation of the multiple reliability information meeting examination condition,

This error checking circuit also in order to this summation is added balancing information with obtain correspond to first in those with the weight of the first syndrome,

This error checking circuit also in order to judge whether those positions have at least one mistake,

If those positions have this at least one mistake, this error checking circuit is also in order to perform iterative decoding procedures according to this weight.

10. memorizer control circuit unit according to claim 9, is characterized in that, this error checking circuit judges that the operation whether those have this at least one mistake comprises:

This error checking circuit performs odd-even check programs to obtain the multiple syndromes comprising this first syndrome to those, wherein each those be correspond to those syndromes at least one of them; And

According to those syndromes, this error checking circuit judges whether those positions have this at least one mistake,

Wherein this odd-even check program is performed by parity-check matrix, and this parity-check matrix comprises multiple restriction,

The operation that wherein this error checking circuit calculates this summation of those reliability information meeting this examination condition in those reliability information comprises:

This error checking circuit, according to the first restriction corresponding to this first syndrome in those restrictions, determines those reliability information meeting this examination condition from those reliability information.

11. memorizer control circuit unit according to claim 10, it is characterized in that, this first restriction comprises multiple element, and according to this first restriction, this error checking circuit determines that from those reliability information the operation meeting those reliability information of this examination condition comprises:

This error checking circuit is multiple elements of " 1 " according to those element intermediate values, determines those reliability information meeting this examination condition from those reliability information.

12. memorizer control circuit unit according to claim 9, is characterized in that, this summation is added that this balancing information comprises with the operation of this weight of this first syndrome corresponding to this first to obtain by this error checking circuit:

This summation is added that this balancing information is to obtain the first appreciation information by this error checking circuit; And

This error checking circuit by this first appreciation information divided by the second appreciation information with obtain correspond to this first with this weight of this first syndrome, wherein this second appreciation information is corresponding to this primary reliability information in those reliability information.

13. memorizer control circuit unit according to claim 9, it is characterized in that, this error checking circuit also in order to select to correspond to the deputy reliability information in those from those reliability information meeting this examination condition, and wherein this second is different from this first

This error checking circuit will be also in order to will be multiplied by Dynamic gene to obtain this balancing information corresponding to this this reliability information deputy.

14. memorizer control circuit unit according to claim 13, is characterized in that, the value corresponding to this this reliability information deputy is minimum in the value of those reliability information meeting this examination condition.

15. memorizer control circuit unit according to claim 13, is characterized in that, the value corresponding to this this reliability information deputy is only greater than the value of the reliability information corresponding to this first in those reliability information meeting this examination condition.

16. memorizer control circuit unit according to claim 9, is characterized in that, the value of this balancing information is the row weight being positively correlated with the first corresponding in parity-check matrix restriction of this first syndrome.

17. 1 kinds of memory storage apparatus, is characterized in that, comprising:

Connecting interface unit, in order to be electrically connected to host computer system;

Reproducible nonvolatile memorizer module, comprises multiple storage unit; And

Memorizer control circuit unit, is electrically connected to this connecting interface unit and this reproducible nonvolatile memorizer module,

Wherein this memorizer control circuit unit is in order to send reading command sequence, and wherein this reading command sequence is in order to read those storage unit, to obtain multiple position,

This memorizer control circuit unit is also in order to obtain multiple reliability information, and wherein each those reliability information corresponds to those one of them,

This memorizer control circuit unit also in order to calculate in those reliability information the summation of the multiple reliability information meeting examination condition,

This memorizer control circuit unit also in order to this summation is added balancing information with obtain correspond to first in those with a weight of the first syndrome,

This memorizer control circuit unit also in order to judge whether those positions have at least one mistake,

If those positions have this at least one mistake, this memorizer control circuit unit is also in order to perform an iterative decoding procedures according to this weight.

18. memory storage apparatus according to claim 17, is characterized in that, those operations whether with this at least one mistake of this memorizer control circuit unit judges comprise:

This memorizer control circuit unit performs odd-even check programs to obtain the multiple syndromes comprising this first syndrome to those, wherein each those be correspond to those syndromes at least one of them; And

According to those syndromes, this memorizer control circuit unit judges whether those positions have this at least one mistake,

Wherein this odd-even check program is performed by parity-check matrix, and this parity-check matrix comprises multiple restriction,

The operation that wherein this memorizer control circuit unit calculates this summation of those reliability information meeting this examination condition in those reliability information comprises:

This memorizer control circuit unit, according to the first restriction corresponding to this first syndrome in those restrictions, determines those reliability information meeting this examination condition from those reliability information.

19. memory storage apparatus according to claim 18, it is characterized in that, this first restriction comprises multiple element, and according to this first restriction, this memorizer control circuit unit determines that from those reliability information the operation meeting those reliability information of this examination condition comprises:

This memorizer control circuit unit is multiple elements of " 1 " according to those element intermediate values, determines those reliability information meeting this examination condition from those reliability information.

20. memory storage apparatus according to claim 17, is characterized in that, this summation is added that this balancing information comprises with the operation of this weight of this first syndrome corresponding to this first to obtain by this memorizer control circuit unit:

This summation is added that this balancing information is to obtain the first appreciation information by this memorizer control circuit unit; And

This memorizer control circuit unit by this first appreciation information divided by the second appreciation information with obtain correspond to this first with this weight of this first syndrome, wherein this second appreciation information is corresponding to this primary reliability information in those reliability information.

21. memory storage apparatus according to claim 17, it is characterized in that, this memorizer control circuit unit also in order to select to correspond to the deputy reliability information in those from those reliability information meeting this examination condition, and wherein this second is different from this first

This memorizer control circuit unit will be also in order to will be multiplied by Dynamic gene to obtain this balancing information corresponding to this this reliability information deputy.

22. memory storage apparatus according to claim 21, is characterized in that, the value corresponding to this this reliability information deputy is minimum in the value of those reliability information meeting this examination condition.

23. memory storage apparatus according to claim 21, is characterized in that, the value corresponding to this this reliability information deputy is only greater than the value of the reliability information corresponding to this first in those reliability information meeting this examination condition.

24. memory storage apparatus according to claim 17, is characterized in that, the value of this balancing information is the row weight being positively correlated with the first corresponding in parity-check matrix restriction of this first syndrome.