CN106843771B - Memory reads method, memorizer control circuit unit and memory storage apparatus again - Google Patents

Memory reads method, memorizer control circuit unit and memory storage apparatus again Download PDF

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Publication number
CN106843771B
CN106843771B CN201710061592.1A CN201710061592A CN106843771B CN 106843771 B CN106843771 B CN 106843771B CN 201710061592 A CN201710061592 A CN 201710061592A CN 106843771 B CN106843771 B CN 106843771B
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parameter group
read
stressed
weight
reads
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CN106843771A (en
Inventor
叶志刚
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Hefei Core Electronics Co Ltd
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Hefei Core Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The present invention provides a kind of memory and reads method, memorizer control circuit unit and memory storage apparatus again.The described method includes: reading putting in order for parameter group again according to multiple weight settings of multiple stressed parameter groups；Data are read from entity program unit according to voltage is read；If the data can not correctly be corrected by corresponding error-correcting code, the stressed parameter group of adjustment is chosen from the stressed parameter group according to described put in order；Parameter group is read again again from entity program unit reading new data according to described adjust；If the new data can correctly be corrected by the corresponding error-correcting code, determine that described adjust reads parameter group again as available stressed parameter group；And the weight for reading parameter group again can be used described in adjustment.

Description

Memory reads method, memorizer control circuit unit and memory storage apparatus again
Technical field
The present invention relates to a kind of memories to read method again, and is used for duplicative non-volatile memories more particularly to one kind The memory of device module reads method and memorizer control circuit unit and memory storage apparatus using the method again.
Background technique
Digital camera, mobile phone and MP3 are very rapid in growth over the years, so that demand of the consumer to storage media Also rapidly increase.Since type nonvolatile (rewritable non-volatile memory) has data Non-volatile, power saving, it is small in size, without the characteristics such as mechanical structure, read or write speed be fast, be most suitable for portable electronic product, such as pen Remember this computer.Solid state hard disk is exactly a kind of memory storage apparatus using flash memory module as storage media.Therefore, closely Year, flash memory industry was as a ring quite popular in electronic industry.
In general, the entity program unit in flash memory module is the number by being arranged on same character line A storage unit is formed.It is the threshold value by changing storage unit when being intended to Data programming to entity program unit Voltage realizes the function of storing data to define the storage state of storage unit.However, it is possible to be made because number of erasing is excessively high At storage unit wear away, be long placed in, the different factors such as reading interference, make the threshold voltage of the storage unit of flash memory module Distributions shift, so that the storage state of storage unit can not be correctly identified.Thus, when application predetermined threshold value voltage to word When symbol line stores the data in entity program unit to read, wrong binary digit can occur for read data.
When wrong binary digit occurs for data read from entity program unit, flash memory module is deposited Memory control circuit unit can be attempted to correct read data.If read data, memory can not be corrected correctly Control circuit unit can entity program unit to read operation to be executed execute and read operation again.In general, memory control Circuit unit processed can adjust the default voltage that reads according to parameter is read provided by manufacturer again to hold to entity program unit Row reads operation again to obtain new data.However, memorizer control circuit unit is only capable of foundation during executing stressed operation Fixed priority chooses stressed parameter.In the case, if effectively the priority of stressed parameter is lower, storage After device control circuit unit first need to execute stressed operation using a large amount of invalid stressed parameters, it could choose to effective weight Read parameter.Thus lead to expend quite a lot of time in the stressed operation of execution.
Summary of the invention
The present invention provides a kind of memory and reads method, memorizer control circuit unit and memory storage apparatus again, can Effectively shorten read again operation the execution time.
One example of the present invention embodiment provides a kind of stressed method of memory, for including making carbon copies for a plurality of character line Formula non-volatile memory module.This method includes: to read again according to multiple first weight settings of multiple stressed parameter groups The first order sequence of parameter group, wherein each reads corresponding first weight of parameter group again.This method also includes: according to One reading voltage reads the first data from the first instance programmed cell on the first character line, and if the first data without Method is correctly corrected by the first corresponding error-correcting code, chooses the first tune from the stressed parameter group according to first order sequence Bulk wight reads parameter group.This method further include: parameter group is read again according to the first adjustment and is read from first instance programmed cell again Take the first new data.This method further include: if the first new data can correctly be corrected by the first corresponding error-correcting code, determine It is the first available stressed parameter group, and the first weight of the available stressed parameter group of adjustment first that the first adjustment, which reads parameter group again,.
In one example of the present invention embodiment, above-mentioned memory reads method again further include: if the first new data without Method is correctly corrected by the first corresponding error-correcting code, chooses the again from the stressed parameter group according to first order sequence One adjusts stressed parameter group.
In one example of the present invention embodiment, it includes at least one reading voltage adjustment that the first adjustment, which reads parameter group again, Value, it is above-mentioned that the step of parameter group reads the first new data from first instance programmed cell again is read again according to the first adjustment It include: to be adjusted to the first reading voltage newly to read electricity according at least one reading voltage change that the first adjustment reads parameter group again Pressure, and the first new data is read from first instance programmed cell according to the new voltage that reads again.
In one example of the present invention embodiment, it includes a reading speed adjusted value that the first adjustment, which reads parameter group again, Above-mentioned reads the step of parameter group reads the first new data from first instance programmed cell again packet again according to the first adjustment It includes: clock frequency being adjusted according to the reading speed adjusted value that the first adjustment reads parameter group again, and according to adjusted clock frequency Rate reads the first new data from first instance programmed cell.
In one example of the present invention embodiment, the step of the first weight of above-mentioned adjustment first available stressed parameter group It include: that the first weight of the first available stressed parameter group is adjusted to higher weights value from lower weighted value.
In one example of the present invention embodiment, above-mentioned memory reads method again further include: record first is available to be read again The first of parameter group successfully reads number again.The step of first weight of above-mentioned adjustment first available stressed parameter group includes: root The first weight for successfully reading the available stressed parameter group of number adjustment first again according to the first of the first available stressed parameter group.
In one example of the present invention embodiment, above-mentioned memory reads method again further include: record first is available to be read again Parameter group is recently using stressed parameter group.The step of first weight of above-mentioned adjustment first available stressed parameter group includes: The first weight of the first available stressed parameter group is adjusted to highest weight weight values using stressed parameter group according to nearest.
In one example of the present invention embodiment, above-mentioned memory reads method again further include: according to the stressed parameter Read the second order sequence of parameter group described in multiple second weight settings of group again, wherein it is one corresponding to read parameter group again for each Second weight；The second data are read from the second instance programmed cell on the first character line according to the second reading voltage；If If the second data can not correctly be corrected by the second corresponding error-correcting code, according to second order sequence from the stressed parameter group Middle selection second adjustment reads parameter group again；Parameter group is read again according to second adjustment to read from second instance programmed cell again Second new data；If the second new data can correctly be corrected by the second corresponding error-correcting code, determine that second adjustment reads ginseng again Array is the second available stressed parameter group；And the second weight of the available stressed parameter group of adjustment second.
In one example of the present invention embodiment, the first order sequence is different from the second order sequence.
In one example of the present invention embodiment, the first instance programmed cell is lower entity program unit, and And the second instance programmed cell is upper entity program unit.
In one example of the present invention embodiment, above-mentioned memory reads method again further include: according to adjusted first Other that can be adjusted with the first weight of stressed parameter group in the stressed parameter group except the first available stressed parameter group are read again First weight of parameter group, and the first weight of the adjusted stressed parameter group stored non-volatile to duplicative Memory module.
One example of the present invention embodiment proposes a kind of non-volatile for controlling the duplicative including a plurality of character line The memorizer control circuit unit of memory module.This memorizer control circuit unit include host interface, memory interface with And memory management circuitry.Host interface couples host system.Memory interface is coupled to type nonvolatile Module.Memory management circuitry is coupled to host interface and memory interface.Memory management circuitry is according to multiple stressed parameters Read the first order sequence of parameter group described in multiple first weight settings of group again, wherein it is one corresponding to read parameter group again for each First weight.Furthermore memory management circuitry, which is sent, reads instruction sequence to indicate to read voltage from the first character according to first The first data are read in first instance programmed cell on line.If the first data can not be by the first corresponding error-correcting code just It really corrects, memory management circuitry chooses the first adjustment from the stressed parameter group according to first order sequence and reads parameter again Group.Also, memory management circuitry reads parameter group again according to the first adjustment and reads from first instance programmed cell again One new data.If the first new data can correctly be corrected by the first corresponding error-correcting code, memory management circuitry determines the One, which adjusts stressed parameter group, can be used the first weight for reading parameter group again for the first available stressed parameter group, and adjustment first.
In one example of the present invention embodiment, if the first new data can not be by the first corresponding error-correcting code correctly Correction, above-mentioned memory management circuitry choose the first adjustment weight from the stressed parameter group according to first order sequence again Read parameter group.
In one example of the present invention embodiment, it includes at least one reading voltage adjustment that the first adjustment, which reads parameter group again, Value, above-mentioned memory management circuitry read at least the one of parameter group again according to the first adjustment and read voltage change for the first reading Voltage is adjusted to newly to read voltage, and sends another reading instruction sequence to indicate that the new reading voltage of basis is again real from first The first new data is read in body programmed cell.
In one example of the present invention embodiment, the first adjustment is read parameter group again and is adjusted including an at least reading speed Value, above-mentioned memory management circuitry adjust clock frequency to read the reading speed adjusted value of parameter group again according to the first adjustment Rate, and the first new data is read from first instance programmed cell according to adjusted clock frequency.
In one example of the present invention embodiment, above-mentioned memory management circuitry is by the of the first available stressed parameter group One weight is adjusted to higher weights value from lower weighted value.
In one example of the present invention embodiment, the available stressed parameter group of above-mentioned memory management circuitry record first First successfully reads number again, and successfully reads according to the first of the first available stressed parameter group that number adjustment first is available to read again again First weight of parameter group.
In one example of the present invention embodiment, the available stressed parameter group of above-mentioned memory management circuitry record first is Recently using stressed parameter group, and parameter group is read again for the first available the first weight tune for reading parameter group again according to nearest use Whole is highest weight weight values.
In one example of the present invention embodiment, above-mentioned memory management circuitry is multiple according to the stressed parameter group Read the second order sequence of parameter group described in second weight setting again, wherein each reads corresponding one second power of parameter group again Weight；Another reading instruction sequence is sent to indicate to read voltage from the second instance sequencing list on the first character line according to second The second data are read in member.If the second data can not correctly be corrected by the second corresponding error-correcting code, above-mentioned memory Management circuit chooses second adjustment from the stressed parameter group according to second order sequence and reads parameter group again, and according to second It adjusts stressed parameter group and reads the second new data from second instance programmed cell again.If the second new data can be by second Corresponding error-correcting code correctly corrects, and it is second available that above-mentioned memory management circuitry, which determines that second adjustment reads parameter group again, It reads parameter group again, and adjusts the second weight of the second available stressed parameter group.
In one example of the present invention embodiment, the first order sequence is different from the second order sequence.
In one example of the present invention embodiment, the first instance programmed cell is lower entity program unit, and And the second instance programmed cell is upper entity program unit.
In one example of the present invention embodiment, above-mentioned memory management circuitry is to available according to adjusted first The first weight for reading parameter group again adjusts first available other stressed parameters read again except parameter group in the stressed parameter group First weight of group, and the first weight of the adjusted stressed parameter group is stored to duplicative non-volatile memories Device module.
One example of the present invention embodiment proposes a kind of memory storage apparatus, including connecting interface unit, duplicative Non-volatile memory module and memorizer control circuit unit.Connecting interface unit is coupled to host system.Duplicative Non-volatile memory module includes a plurality of character line.Memorizer control circuit unit is coupled to connecting interface unit and can make carbon copies Formula non-volatile memory module.Memorizer control circuit unit is coupled to host interface and memory interface.Memory control Circuit unit reads the first order sequence of parameter group again according to multiple first weight settings of multiple stressed parameter groups, wherein Each reads corresponding first weight of parameter group again.Furthermore memorizer control circuit unit, which is sent, reads instruction sequence to refer to Show and the first data are read from the first instance programmed cell on the first character line according to the first reading voltage.If the first number According to can not correctly be corrected by the first corresponding error-correcting code, memorizer control circuit unit is according to first order sequence from described It reads again and chooses the stressed parameter group of the first adjustment in parameter group.Also, memorizer control circuit unit reads ginseng again according to the first adjustment Array reads the first new data from first instance programmed cell again.If the first new data can be by the first corresponding wrong school Code correctly corrects, and it is the first available stressed parameter group that memorizer control circuit unit, which determines that the first adjustment reads parameter group again, And the first weight of the available stressed parameter group of adjustment first.
In one example of the present invention embodiment, if the first new data can not be by the first corresponding error-correcting code correctly Correction, above-mentioned memorizer control circuit unit choose the first tune from the stressed parameter group according to first order sequence again Bulk wight reads parameter group.
In one example of the present invention embodiment, it includes at least one reading voltage adjustment that the first adjustment, which reads parameter group again, Value, above-mentioned memorizer control circuit unit read at least the one of parameter group again according to the first adjustment and read voltage change for first Voltage is read to be adjusted to newly to read voltage, and send another readings instruction sequence with indicate basis newly reading voltage again from the The first new data is read in one entity program unit.
In one example of the present invention embodiment, the first adjustment is read parameter group again and is adjusted including an at least reading speed Value, above-mentioned memorizer control circuit unit adjust clock to read the reading speed adjusted value of parameter group again according to the first adjustment Frequency, and the first new data is read from first instance programmed cell according to adjusted clock frequency.
In one example of the present invention embodiment, stressed parameter group is can be used by first in above-mentioned memorizer control circuit unit The first weight be adjusted to higher weights value from lower weighted value.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit record first can use stressed parameter The first of group successfully reads number again, and it is available according to the first of the first available stressed parameter group successfully to read number adjustment first again Read the first weight of parameter group again.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit record first can use stressed parameter Group reads parameter group again to use recently, and according to nearest the first power that stressed parameter group can be used by first using parameter group is read again Recanalization is highest weight weight values.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is according to the stressed parameter group Read the second order sequence of parameter group described in multiple second weight settings again, wherein it is one second corresponding to read parameter group again for each Weight；Another reading instruction sequence is sent to indicate to read voltage from the second instance sequencing on the first character line according to second The second data are read in unit.If the second data can not correctly be corrected by the second corresponding error-correcting code, above-mentioned storage Device control circuit unit chooses second adjustment from the stressed parameter group according to second order sequence and reads parameter group, and root again Parameter group is read again according to second adjustment reads the second new data from second instance programmed cell again.If the second new data can It is correctly corrected by the second corresponding error-correcting code, above-mentioned memorizer control circuit unit determines that second adjustment reads parameter group again Stressed parameter group can be used for second, and adjust the second weight of the second available stressed parameter group.
In one example of the present invention embodiment, the first order sequence is different from the second order sequence.
In one example of the present invention embodiment, the first instance programmed cell is lower entity program unit, and And the second instance programmed cell is upper entity program unit.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit is to according to adjusted first Other that can be adjusted with the first weight of stressed parameter group in the stressed parameter group except the first available stressed parameter group are read again First weight of parameter group, and the first weight of the adjusted stressed parameter group stored non-volatile to duplicative Memory module.
Based on above-mentioned, the present invention is all heavy by adjusting being reset with the weight of stressed parameter group for being determined Read putting in order for parameter group.So that can be read again next time in the primary available stressed parameter group read again and determined in operation It is preferentially chosen for adjusting stressed parameter group in operation.Thus, it is possible to reduce determine available stressed parameter group when Between, so effectively shorten read again operation the execution time.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate shown attached drawing It is described in detail below.
Detailed description of the invention
Fig. 1 is host system, memory storage apparatus and the input/output shown in an exemplary embodiment according to the present invention (I/O) schematic diagram of device；
Fig. 2 is host system, memory storage apparatus and input shown in another exemplary embodiment according to the present invention/defeated The schematic diagram of (I/O) device out；
Fig. 3 is the signal of the host system and memory storage apparatus shown in another exemplary embodiment according to the present invention Figure；
Fig. 4 is the summary square of the host system and memory storage apparatus shown in an exemplary embodiment according to the present invention Figure；
Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown in an exemplary embodiment according to the present invention；
Fig. 6 is the schematic diagram of the threshold voltage distribution of the storage unit shown in an exemplary embodiment according to the present invention；
Fig. 7 is that the weight of the stressed parameter group of adjustment shown in an exemplary embodiment according to the present invention is shown with what is put in order It is intended to；
Fig. 8 is that the adjustment shown in another exemplary embodiment according to the present invention reads the weight of parameter group again and puts in order Schematic diagram；
Fig. 9 is that the adjustment shown in another exemplary embodiment according to the present invention reads the weight of parameter group again and puts in order Schematic diagram；
Figure 10 is the schematic diagram of the stressed method of memory shown in an exemplary embodiment according to the present invention；
Figure 11 is the schematic diagram of the stressed method of memory shown in another exemplary embodiment according to the present invention.
Description of symbols:
10: memory storage apparatus；
11: host system；
110: system bus；
111: processor；
112: random access memory；
113: read-only memory；
114: data transmission interface；
12: input/output (I/O) device；
20: motherboard；
201:U disk；
202: memory card；
203: solid state hard disk；
204: radio memory storage device；
205: GPS module；
206: network interface card；
207: radio transmitting device；
208: keyboard；
209: screen；
210: loudspeaker；
30: storage device；
31: host system；
32:SD card；
33:CF card；
34: embedded storage device；
341: embedded multi-media card；
342: embedded type multi-core piece sealed storage device；
402: connecting interface unit；
404: memorizer control circuit unit；
406: reproducible nonvolatile memorizer module；
502: memory management circuitry；
504: host interface；
506: memory interface；
508: error checking and correcting circuit；
510: buffer storage；
512: electric power management circuit；
610,620,610 ', 620 ': state；
" 0 ", " 1 ": position；
601,602: reading voltage；
A~H: parameter group is read again；
710,720,730,810,820,830,910,920,930: weight record sheet；
Seq_711、Seq_721、Seq_731、Seq_811、Seq_821、Seq_831、Seq_911、Seq_921、Seq_ 931: putting in order；
S1001: the step of putting in order of parameter group is read again according to the weight setting of stressed parameter group；
S1003: the step of data are read from the entity program unit on character line according to reading voltage；
S1005: the step of whether read data can correctly be corrected by corresponding error-correcting code judged；
S1007: the step of exporting the data corrected；
S1009: the step of adjusting stressed parameter group, is chosen from stressed parameter group according to putting in order for setting；
S1011: the step of parameter group reads new data from entity program unit again is read again according to adjusting；
S1013: the step of whether read new data can correctly be corrected by corresponding error-correcting code judged；
S1015: it determines to adjust and reads parameter group again as available stressed parameter group, and adjust the available weight for reading parameter group again The step of；
S1101: the first order sequence of parameter group is read again according to the first weight setting of stressed parameter group, and according to weight The step of reading the second order sequence of the stressed parameter group of the second weight setting of parameter group；
S1103: the step of data are read from the entity program unit on character line according to default reading voltage；
S1105: the step of whether read data can correctly be corrected by corresponding error-correcting code judged；
S1107: the step of exporting the data corrected；
S1109: the entity program unit of judgement read operation to be executed is lower entity program unit or upper entity journey Sequence unit；
S1111: if the entity program unit of read operation to be executed is lower entity program unit, according to first order Sequence chooses the step of the first adjustment reads parameter group again from stressed parameter group；
S1113: parameter group is read again according to the first adjustment and reads the first new data from this lower entity program unit again The step of；
S1115: the step of whether read first new data can correctly be corrected by corresponding error-correcting code judged；
S1117: determine that the first adjustment reads parameter group again as the first available stressed parameter group, and it is available stressed to adjust first The step of first weight of parameter group；
S1119: if the entity program unit of read operation to be executed is upper entity program unit, according to second order Sequence chooses the step of second adjustment reads parameter group again from stressed parameter group；
S1121: parameter group is read again according to second adjustment and reads the second new data in entity program unit from this again The step of；
S1123: the step of whether read second new data can correctly be corrected by corresponding error-correcting code judged；
S1125: determine that second adjustment reads parameter group again as the second available stressed parameter group, and it is available stressed to adjust second The step of second weight of parameter group.
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module and controller (also referred to as, control circuit unit).Be commonly stored device storage device be used together with host system so that Host system can write data into memory storage apparatus or read from memory storage apparatus data.
Fig. 1 is according to host system, memory storage apparatus and input/output (I/O) dress shown in an exemplary embodiment The schematic diagram set, and Fig. 2 is the host system according to depicted in another exemplary embodiment, memory storage apparatus and input/defeated The schematic diagram of (I/O) device out.
Fig. 1 and Fig. 2 are please referred to, host system 11 generally comprises processor 111, random access memory (random Access memory, RAM) 112, read-only memory (read only memory, ROM) 113 and data transmission interface 114.Place Reason device 111, random access memory 112, read-only memory 113 and data transmission interface 114 are coupled to system bus (system bus)110。
In this exemplary embodiment, host system 11 is by data transmission interface 114 and 10 coupling of memory storage apparatus It connects.For example, host system 11 can be write data into via data transmission interface 114 to memory storage apparatus 10 or from memory Data are read in storage device 10.In addition, host system 11 is coupled by system bus 110 and I/O device 12.For example, main Output signal can be sent to I/O device 12 via system bus 110 or receive input signal from I/O device 12 by machine system 11.
In this exemplary embodiment, processor 111, random access memory 112, read-only memory 113 and data transmission Interface 114 is on the motherboard 20 for may be provided at host system 11.The number of data transmission interface 114 can be one or more. By data transmission interface 114, motherboard 20 can be coupled to memory storage apparatus 10 via wired or wireless way.Storage Device storage device 10 can be for example USB flash disk 201, memory card 202, solid state hard disk (Solid State Drive, SSD) 203 or wireless Memory storage apparatus 204.Radio memory storage device 204 can be for example wireless near field communication (Near Field Communication Storage, NFC) memory storage apparatus, radio facsimile (WiFi) memory storage apparatus, bluetooth (Bluetooth) memory storage apparatus or low-power consumption bluetooth memory storage apparatus (for example, iBeacon) etc. are with various wireless Memory storage apparatus based on the communication technology.Determine in addition, motherboard 20 can also be coupled to the whole world by system bus 110 Position system (Global Positioning System, GPS) module 205, network interface card 206, radio transmitting device 207, key The various I/O device such as disk 208, screen 209, loudspeaker 210.For example, motherboard 20 can be by wirelessly passing in an exemplary embodiment Defeated 207 access wireless memory storage apparatus 204 of device.
In an exemplary embodiment, mentioned host system is substantially to cooperate with memory storage apparatus to store The arbitrary system of data.Although host system is explained with computer system, however, Fig. 3 is in above-mentioned exemplary embodiment The schematic diagram of host system and memory storage apparatus according to another exemplary embodiment.Referring to figure 3., in another example In embodiment, host system 31 is also possible to digital camera, video camera, communication device, audio player, video player or flat The systems such as plate computer, and memory storage apparatus 30 can be its used SD card 32, CF card 33 or embedded storage device 34 Etc. various non-volatile memory storage device.Embedded storage device 34 include embedded multi-media card (embedded MMC, EMMC) 341 and/or embedded type multi-core piece sealed storage device (embedded Multi Chip Package, eMCP) 342 etc. The all types of embedded storage devices being coupled directly to memory module on the substrate of host system.
Fig. 4 is the schematic block diagram according to host system and memory storage apparatus shown in an exemplary embodiment.
Referring to figure 4., memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.
In this exemplary embodiment, connecting interface unit 402 is compatible with the advanced attachment of sequence (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, connecting interface unit 402 are also possible to meet advanced attachment (Parallel Advanced Technology Attachment, PATA) mark side by side Quasi-, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface standard, peace Digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, insertion Formula multimedia storage card (Embedded Multimedia Card, eMMC) interface standard, general flash memory (Universal Flash Storage, UFS) interface standard, embedded type multi-core piece encapsulate (embedded Multi Chip Package, eMCP) interface standard, compact flash (Compact Flash, CF) interface standard, integrated form driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.In this exemplary embodiment, connection Interface unit 402 can be encapsulated in memorizer control circuit unit 404 in a chip or connecting interface unit 402 is cloth Outside a chip comprising memorizer control circuit unit.
Memorizer control circuit unit 404 is to execute in the form of hardware or the multiple logic gates or control of form of firmware implementation System instruction, and writing for data is carried out in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The running such as enter, read and erase.
Reproducible nonvolatile memorizer module 406 is coupled to memorizer control circuit unit 404 and to deposit The data that storage host system 11 is written.Reproducible nonvolatile memorizer module 406 can be single-order storage unit (Single Level Cell, SLC) NAND type flash memory module is (that is, can store 1 data two in a storage unit The flash memory module of system position), multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory mould Block (that is, flash memory module that 2 data binary digits can be stored in a storage unit), Complex Order storage unit (Trinary Level Cell, TLC) NAND type flash memory module is (that is, can store 3 data two in a storage unit The flash memory module of system position), other flash memory modules or other memory modules with the same characteristics.
In this exemplary embodiment, the storage unit of reproducible nonvolatile memorizer module 406 can constitute multiple realities Body programmed cell, and these entity program units can constitute multiple entity erased cells.For example, on same character line Storage unit can form one or more entity program units.If each storage unit can store 2 or more data Binary digit, then the entity program unit on same character line can at least be classified as lower entity program unit and upper reality Body programmed cell.For example, each storage unit of SLC NAND type flash memory can store the number of 1 binary digit According to therefore, in SLC NAND type flash memory, the several storage units being arranged on same character line are one corresponding Entity program unit.For SLC NAND type flash memory, each storage of MLC NAND type flash memory Unit can store the data of 2 binary digits, and wherein each storage state (that is, " 11 ", " 10 ", " 01 " and " 00 ") includes most Low effective binary digit (Least Significant Bit, LSB) and the effective binary digit (Most of highest Significant Bit,MSB).For example, the value for the 1st binary digit counted in storage state from left side is LSB, and from a left side The value for the 2nd binary digit that side is counted is MSB.Therefore, the several storage units being arranged on same character line constitute 2 A entity program unit, wherein thus entity program unit composed by the LSB of a little storage units is known as lower entity program Change unit (low physical programming unit), and thus entity program composed by the MSB of a little storage units Change unit and is known as upper entity program unit (upper physical programming unit).In general, in MLC In NAND type flash memory, the writing speed of lower entity program unit can be greater than the write-in speed of upper entity program unit The reliability of degree and/or lower entity program unit is above the reliability of entity program unit.
Similarly, in TLC NAND type flash memory, each storage unit can store the data of 3 binary digits, Wherein each storage state (that is, " 111 ", " 110 ", " 101 ", " 100 ", " 011 ", " 010 ", " 001 " and " 000 ") includes a left side Effective binary digit (the Center in centre of the LSB for the 1st binary digit that side is counted, the 2nd binary digit counted from left side Significant Bit, CSB) and the MSB of the 3rd binary digit counted from left side.Therefore, it is arranged in same character Several storage units on line constitute 3 entity program units, wherein thus entity composed by the LSB of a little storage units Programmed cell is known as lower entity program unit, and thus entity program unit composed by the CSB of a little storage units is known as Middle entity program unit, and thus entity program unit composed by the MSB of a little storage units is known as upper entity program Change unit.
In this exemplary embodiment, entity program unit is the minimum unit of sequencing.That is, entity program unit is The minimum unit of data is written.For example, entity program unit is physical page (page) or entity fan (sector).If real Body programmed cell is physical page, then these entity program units generally include data binary digit area and redundancy (redundancy) binary digit area.Data binary digit area includes multiple entities fan, to store user's data, and redundancy Binary digit area is to memory system data (for example, error-correcting code).In this exemplary embodiment, data binary digit area packet It is fanned containing 32 entities, and the size of entity fan is 512 binary system hytes (byte, B).However, in other exemplary embodiments In, it also may include 8,16 or the more or fewer entity fans of number in data binary digit area, and each entity is fanned Size be also possible to it is greater or lesser.On the other hand, entity erased cell is the minimum unit erased.That is, each entity Erased cell contains the storage unit of minimal amount being erased together.For example, entity erased cell is physical blocks (block)。
In this exemplary embodiment, each of reproducible nonvolatile memorizer module 406 storage unit be with The change of voltage (also referred to as threshold voltage) stores one or more binary digits.Specifically, the control of each storage unit There is an electric charge capture layer between door (control gate) processed and channel.It, can be with by bestowing a write-in voltage to controlling door Change charge and mend the amount of electrons for catching layer, and then changes the threshold voltage of storage unit.This operation for changing threshold voltage is also referred to as " writing the data to storage unit " or " sequencing storage unit ".With the change of threshold voltage, duplicative is non-volatile Each of memory module 406 storage unit has multiple storage states.It may determine that one by bestowing reading voltage Storage unit is which storage state belonged to, and obtains one or more binary digits that this storage unit is stored whereby.
Fig. 5 is the schematic block diagram according to the memorizer control circuit unit shown in an exemplary embodiment.
Referring to figure 5., memorizer control circuit unit 404 includes memory management circuitry 502, host interface 504 and deposits Memory interface 506, buffer storage 510, electric power management circuit 512 and error checking and correcting circuit 508.
Overall operation of the memory management circuitry 502 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 502, has multiple control instructions, and when memory storage apparatus 10 operates, these control instructions can quilt It executes the running such as to carry out the write-in of data, read and erase.
In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with form of firmware.For example, Memory management circuitry 502 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is by imprinting so far read-only memory.When memory storage apparatus 10 operates, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.
In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 502 can also be in the form of procedure code The specific region of reproducible nonvolatile memorizer module 406 is stored in (for example, being exclusively used in storage system in memory module The system area of data) in.In addition, memory management circuitry 502 has microprocessor unit (not shown), read-only memory (not Show) and random access memory (not shown).In particular, this read-only memory has driving code, and when memory controls When circuit unit 404 is enabled, microprocessor unit can first carry out this driving code section, and will to be stored in duplicative non-volatile Control instruction in memory module 406 is loaded into the random access memory of memory management circuitry 502.Later, micro- place Reason device unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.
In addition, the control instruction of memory management circuitry 502 can also be with a hardware in another exemplary embodiment of the present invention Form carrys out implementation.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity Circuit is erased on road, memory reading circuitry, memory and data processing circuit is coupled to microcontroller.Wherein, storage unit Manage entity erased cell of the circuit to manage reproducible nonvolatile memorizer module 406；Memory write circuit is used It writes data into duplicative is non-volatile and deposits to assign write instruction to reproducible nonvolatile memorizer module 406 In memory modules 406；Memory reading circuitry to reproducible nonvolatile memorizer module 406 assign reading instruction with Data are read from reproducible nonvolatile memorizer module 406；Memory erases circuit to non-volatile to duplicative Property memory module 406 assign erase instruction data to be erased from reproducible nonvolatile memorizer module 406；And it counts According to processing circuit to handle be intended to be written data to reproducible nonvolatile memorizer module 406 and from duplicative it is non- The data read in volatile 406.
Host interface 504 is coupled to memory management circuitry 502 and to be coupled to connecting interface unit 402, with Receive the instruction and data transmitted with identification host system 11.That is, instruction and data that host system 11 is transmitted Memory management circuitry 502 can be sent to by host interface 504.In this exemplary embodiment, host interface 504 is compatible In SATA standard.However, it is necessary to be appreciated that the invention is not limited thereto, host interface 504 be also possible to be compatible with PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS Standard, MMC standard, CF standard, IDE standard or other suitable data transmission standards.
Memory interface 506 is coupled to memory management circuitry 502 and duplicative is non-volatile to be deposited to access Memory modules 406.It can be via memory to the data of reproducible nonvolatile memorizer module 406 that is, being intended to be written Interface 506 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.
Buffer storage 510 is coupled to memory management circuitry 502 and is configured to temporarily store from host system 11 Data and instruction or the data from reproducible nonvolatile memorizer module 406.
Electric power management circuit 512 is coupled to memory management circuitry 502 and to control memory storage apparatus 10 Power supply.
Error checking and correcting circuit 508 be coupled to memory management circuitry 502 and to execute error checking with Correction program is to ensure the correctness of data.Specifically, it is write when memory management circuitry 502 is received from host system 11 When entering to instruct, error checking can generate corresponding error checking and school with correcting circuit 508 for the data of this corresponding write instruction Code (Error Checking and Correcting Code, ECC Code), and the meeting of memory management circuitry 502 will be right The data of this write instruction are answered to be written with corresponding error checking and correcting code to reproducible nonvolatile memorizer module 406 In.It later, can be simultaneously when reading data from reproducible nonvolatile memorizer module 406 when memory management circuitry 502 Read the corresponding error checking of this data and correcting code, and error checking and correcting circuit 508 can according to this error checking with Correcting code executes error checking and correction program to read data.
Fig. 6 is the schematic diagram of the threshold voltage distribution of the storage unit shown in an exemplary embodiment according to the present invention.
In Fig. 6, the threshold voltage of horizontal axis representative memory cell, and longitudinal axis representative memory cell number.
Please refer to Fig. 6, it is assumed that state 610 corresponds to binary digit " 1 " and state 620 corresponds to binary digit " 0 ".If If the threshold voltage of some storage unit belongs to state 610, what this storage unit was stored is binary digit " 1 "；Relatively, If the threshold voltage of some storage unit belongs to state 620, what this storage unit was stored is binary digit " 0 ".Palpus It is noted that in this exemplary embodiment, a state in threshold voltage distribution it is corresponding to bit (that is, " 0 " or " 1 "), and there are two types of possible states for the threshold voltage distribution of storage unit.However, in other exemplary embodiments, threshold value Each of voltage's distribiuting state can also correspond to the distribution of the threshold voltage to multiple binary digits and storage unit There are four types of possibility, eight kinds or any other a state.In addition, the present invention does not limit binary system representated by each state yet Position.For example, state 610 may correspond to binary digit " 0 " in another exemplary embodiment, and state 620 then corresponds to two System position " 1 ".
In this exemplary embodiment, when to read data from reproducible nonvolatile memorizer module 406, memory Management circuit 502 can send a reading instruction sequence to reproducible nonvolatile memorizer module 406.This reads instruction sequence To indicate that reproducible nonvolatile memorizer module 406 reads number from multiple storage units (also referred to as the first storage unit) According to.In this exemplary embodiment, the first storage unit is to belong to the same entity program unit.However, real in another example It applies in example, the first storage unit is also possible to belong to different entity program units.It does not shift in threshold voltage distribution Situation under, the threshold voltage of the first storage unit is distributed as state 610 and state 620.Instruction sequence is read according to this, can be answered Data can be read from the first storage unit according to the reading voltage 601 in Fig. 6 by writing formula non-volatile memory module 406.It reads Default reading voltage when voltage 601 can dispatch from the factory for reproducible nonvolatile memorizer module 406, can be used to identify that first deposits The state 610 and state 620 of storage unit.That is, threshold voltage is less than the storage for reading voltage 601 in the first storage unit Unit can be switched on, and memory management circuitry 502 can read binary digit " 1 ".Relatively, threshold value in the first storage unit The storage unit that voltage is greater than reading voltage 601 will not be switched on, and memory management circuitry 502 can read binary digit “0”。
However, because of different factor, such as data are long placed in, storage unit abrasion and reading interference etc., will lead to first The threshold voltage distributions shift of storage unit, so that the first storage unit can not be correctly identified out using voltage 601 is read Storage state.
Assuming that the threshold voltage distribution of the first storage unit has deviated, the state 610 and 620 point for causing threshold voltage to be distributed It Pian Yi not be state 610 ' and 620 '.In the case, have that some storage units are stored in the first storage unit should It is binary digit " 1 " (belonging to state 610 '), but its threshold voltage is greater than applied reading voltage 601；Alternatively, being deposited first Have that some storage units are stored in storage unit should be binary digit " 0 " (belonging to state 620 '), but its threshold voltage is small In the reading voltage 601 applied.In other words, via applying in the reading read data of voltage 601, there is the binary system of part It position can be wrong.Therefore, after receiving read data from reproducible nonvolatile memorizer module 406, mistake inspection The error-correcting code for looking into data streams read corresponding with the meeting of correcting circuit 508 together reading whether there is with verifying in data streams read Mistake.If it is determined that there are mistakes in data streams read, then error checking and correcting circuit 508 can execute decoding operate to attempt school Mistake in positive data streams read.And the mistake in the data streams read can not be by error checking and correcting circuit 508 correctly When decoding (such as the wrong binary digit number of data streams read is more than protective capability of error checking and correcting circuit 508), Will lead to data streams read can not correctly be corrected and generate wrong data.
In this exemplary embodiment, when data streams read can not be by correctly timing, the meeting pair of memory management circuitry 502 Entity program unit on the character line of read operation to be executed executes stressed (retry read) operation can be wrong to obtain Erroneous detection looks into the data correctly corrected with correcting circuit 508.And during executing stressed operation, memory management circuitry 502 can determine available stressed parameter group from multiple stressed parameter groups, and according to the available stressed parameter group determined from Data are re-read in first instance programmed cell on first character line to obtain correct data.
And each of above-mentioned read again in parameter group may include at least one parameter.For example, in a stressed parameter group Parameter will include and one or more read voltage changes.Reading voltage change can be duplicative non-volatile memories Parameter provided by the manufacturer of device module 406.Therefore, memory management circuitry 502 can be according to available stressed parameter group institute Including reading voltage change come obtain can with read voltage.It is deposited when bestowing available reading voltage to duplicative is non-volatile When memory modules 406 from an entity program unit to read data, read data can be by error checking and correction Circuit 508 correctly corrects.However, the parameter of a stressed parameter group can also be reading speed in another exemplary embodiment Adjusted value, and memory management circuitry 502 can adjust clock frequency when executing read operation according to reading speed adjusted value. In addition, can also will be used to obtain soft binary digit (soft corresponding to decodable data in another exemplary embodiment Bit) voltage level is set as the parameter in a stressed parameter group.Base this, memory management circuitry 502 can according to this read again The soft binary digit voltage level of parameter group executes stressed operation.However, above-mentioned parameter is only for example, the present invention is not intended to limit Read the parameter in parameter group again.
In this exemplary embodiment, each stressed parameter group can have corresponding one or more weights.In particular, storage Device manages the meeting of circuit 502 according to the weight of stressed parameter group come the stressed parameter group that sorts, and according to putting in order after sequence To be used to execute the stressed parameter group for reading operation again (also referred to as adjust and read parameter group again) to choose.For example, it is assumed that one is read again The parameter of parameter group is a reading voltage change, and by taking Fig. 6 as an example, memory management circuitry 502 is according to putting in order sequentially It has selected one and adjusts stressed parameter group, and voltage 601 will be read according to the reading voltage change for reading parameter group again is adjusted It is adjusted to read voltage 602.In turn, it is electric according to reading to indicate to send a reading instruction sequence for memory management circuitry 502 Pressure 602 re-reads data from first instance programmed cell.Voltage 602 is read from first instance sequencing list if bestowing Read data can be by error checking and correcting circuit 508 correctly timing in member, then ginseng is read in selected adjustment again Array is available stressed parameter group.On the other hand, it is read from first instance programmed cell if bestowing and reading voltage 602 The data taken can not correctly be corrected by error checking and correcting circuit 508, and memory management circuitry 502 can execute again selection The operation for reading parameter group again is adjusted, until determining available stressed parameter group.
Although being to be stored in first instance programmed cell according to a reading voltage to read in this exemplary embodiment Data, however the present invention is not limited thereto.In another exemplary embodiment, it can also be deposited according to multiple reading voltages to read Store up the data in first instance programmed cell.And the parameter in a stressed parameter group may include multiple reading voltage adjustment Value, and memory management circuitry 502 can be adjusted according to multiple reading voltage changes for from first instance programmed cell The middle multiple reading voltages for reading data.
After determining available stressed parameter group, memory management circuitry 502 can adjust the power of available stressed parameter group Weight.In an exemplary embodiment, memory management circuitry 502 can also be adjusted according to adjusted with the weight of stressed parameter group Whole other read the weight of parameter group again.In turn, memory management circuitry 502 can be reset all according to adjusted weight Read putting in order for parameter group again.
Fig. 7 is that the weight of the stressed parameter group of adjustment shown in an exemplary embodiment according to the present invention is shown with what is put in order It is intended to.For purposes of illustration only, being to bestow the first reading voltage to the first character line to read storage in exemplary embodiment below Data instance on the first character line in first instance programmed cell illustrates.Also, one in this exemplary embodiment A stressed parameter group is a corresponding weight (also referred to as the first weight).
Fig. 7 is please referred to, for executing the stressed parameter group for reading operation again including reading parameter group A~H again.Read parameter group A again ~H is respectively provided with corresponding weight, and reading parameter group A~H again can sort according to weight.In duplicative non-volatile memories When the manufacture of device module 406 is completed, the weight for reading parameter group A~H again may respectively be an initial weight value.Read parameter group A~H meeting again Initial arrangement sequence is initially ordered as according to initial weight value.In this exemplary embodiment, initial weight value can be by Manufacturer provides.As shown in weight record sheet 710, the initial weight value for reading the weight of parameter group A~H again is 1~8 respectively, Therefore it reads parameter group A~H again and the Seq_711 that puts in order is ordered as according to initial weight value.Here, weighted value " 1 " is to generation Table highest weight weight values, weighted value " 8 " is to represent lowest weightings value.Memory management circuitry 502 can be arrived according to highest weight weight values The sequence of lowest weightings value is come the stressed parameter group A~H that sorts.Therefore, parameter group A~H is read again to be sorted according to initial weight value For the Seq_711 that puts in order.It is noted that 8 stressed parameter group A~H of this exemplary embodiment are only for example.However, In In other exemplary embodiments, the stressed parameter group of less or more number can be set.The present invention is not intended to limit stressed parameter group Number.
When according to first read voltage from first instance programmed cell read data can not by error checking with Correctly timing, memory management circuitry 502 can be according to stressed parameter group A~H come to first instance program for correcting circuit 508 Change unit and executes stressed operation.Above-mentioned first, which reads voltage, to read voltage to be default.When memory management circuitry 502 first When operation is read in secondary execution again, memory management circuitry 502 can be according to initial arrangement sequence (namely the Seq_711 that puts in order) first It chooses and reads parameter group A again as stressed parameter group is adjusted to execute stressed operation.It is to read parameter again in this exemplary embodiment The parameter of a reading voltage change is respectively included in group A~H to illustrate.Memory management circuitry 502 is according to stressed The reading voltage change of parameter group A is adjusted to newly to read voltage by voltage is read.In turn, memory management circuitry 502 is sent One reading instruction sequence is to indicate to read out new data (also referred to as from first instance programmed cell according to the new voltage that reads First new data).If can not be by correctly timing, memory management circuitry according to the new reading read new data of voltage 502 can sequentially be chosen according to the Seq_711 that puts in order read again parameter group B as adjust read parameter group again execute it is stressed operate with Reacquire new data.The rest may be inferred, and memory management circuitry 502 is sequentially chosen according to the Seq_711 that puts in order to stressed ginseng Array D adjusts reading voltage as stressed parameter group is adjusted, and read out according to the new reading voltage adjusted out New data can be corrected correctly, and memory management circuitry 502 can determine that reading parameter group D again is this stressed operation executed Stressed parameter group can be used.
In this exemplary embodiment, it is nearest that memory management circuitry 502, which will record the available stressed parameter group determined, Using stressed parameter group, and according to the weight for adjusting all stressed parameter groups using stressed parameter group recently.Memory pipe Reason circuit 502 can will be adjusted to higher weights value from lower weighted value using the weight for reading parameter group again recently, and by other The weight for reading parameter group again is adjusted to lower weighted value from higher weights value correspondence.For example, the record weight of memory management circuitry 502 Reading parameter group D is to use to read parameter group again recently, and the weight of stressed parameter group D is adjusted to weighted value from weighted value " 4 " " 1 " (namely highest weight weight values).In this exemplary embodiment, memory management circuitry 502 can be by the power of stressed parameter group A~C It is adjusted separately again as weighted value " 2 ", " 3 ", " 4 ", and the weight for reading parameter group E~H again will not be then adjusted, such as weight record sheet Shown in 720.Memory management circuitry 502 puts in order according to the stressed parameter group A~H's of weight adjusted reset as row Column sequence Seq_721.
However, memory management circuitry 502 can distinguish the weight of stressed parameter group E~H in another exemplary embodiment Weighted value " 2 ", " 3 ", " 4 ", " 5 " are adjusted to, and the weight of stressed parameter group A~C correspondence is adjusted to " 6 ", " 7 ", " 8 ". That is, memory management circuitry 502 according to weight adjusted reset read again parameter group A~H put in order for DEFGHABC。
Since the storage unit situation of type nonvolatile 406 is roughly the same, lead to storage unit Threshold voltage distributions shift the reason of may also be identical.Base this, most recently used reads parameter group (namely available stressed parameter again Group) there is higher probability to be also decided to be available stressed parameter group in the stressed operation that next time executes.Therefore, it will use recently The weight for reading parameter group again is adjusted to highest weight weight values, can preferentially choose when that need to execute and read operation again next time recently using weight Parameter group is read as adjustment and reads parameter group again.
When executing next stressed operation, memory management circuitry 502 can preferentially be chosen according to the Seq_721 that puts in order and arrive Stressed parameter group D reads parameter group again as adjustment, and reads parameter group again according to the above method to determine can be used.Assuming that storage Device manages circuit 502 and determines that reading parameter group G again is available stressed parameter group according to the Seq_721 that puts in order.Memory management It is recently using reading parameter group again, and by the weight of stressed parameter group G from weighted value that circuit 502, which will record stressed parameter group G, " 7 " are adjusted to weighted value " 1 " and the weighted value of stressed parameter group A~F are added 1 respectively to adjust its weight.Such as weight record Shown in table 730, the weight for reading parameter group D again is adjusted to weighted value " 2 " from weighted value " 1 ", reads the weight of parameter group A again from power Weight values " 2 " are adjusted to weighted value " 3 ", and the weight for reading parameter group F again is adjusted to weighted value " 7 " from weighted value " 6 ".In turn, Memory management circuitry 502 is reset according to weight adjusted reads the putting in order to put in order of parameter group A~H again Seq_731。
Fig. 8 is that the adjustment shown in another exemplary embodiment according to the present invention reads the weight of parameter group again and puts in order Schematic diagram.Unlike the exemplary embodiment of Fig. 7, in the exemplary embodiment of Fig. 8, memory management circuitry 502 be will record Number is read in the success for reading parameter group again again, and adjusts weight according to number is successfully read again.
Please refer to Fig. 8, if when a stressed parameter group is decided to be available stressed parameter group, this read again parameter group at Function is read number again and can be updated.In this exemplary embodiment, it is assumed that read the current success of parameter group A~H again and read number and power again Weight is as shown in weight record sheet 810.For example, it is respectively " 7 " that number is read in the success for reading parameter group A and B again, which again, parameter group A is read again Weight with B is respectively weighted value " 1 " and weighted value " 2 ", and reads parameter group again and be ordered as the Seq_811 that puts in order.In Primary to read again in operation, memory management circuitry 502 determines that reading parameter group B again is available weight according to the Seq_811 that puts in order Read parameter group.It add at this point, the success of stressed parameter group B can be read again number by memory management circuitry 502 1 with by stressed parameter group The success of B reads number again and is updated to " 8 ".Then, memory management circuitry 502 can relatively read parameter group B again and other read ginseng again Number is read in the success of array again, and judges that reading parameter group B again has most successfully stressed numbers.Therefore, memory management The weight setting of stressed parameter group B is weighted value " 1 " by circuit 502, and the weighted value of stressed parameter group A is added 1 will weigh The weight for reading parameter group A is updated to weighted value " 2 ", as shown in weight record sheet 820.In turn, 502 basis of memory management circuitry The weight stressed parameter group A~H's of reset adjusted puts in order as the Seq_821 that puts in order.That is, next time holds When row reads operation again, memory management circuitry 502 can preferentially be chosen according to the Seq_821 that puts in order to at most successfully reading The stressed parameter group B of number is taken to read parameter group again as adjustment.Due to successfully read again the higher stressed parameter group of number have it is higher Probability become available stressed parameter group when executing and reading operation again next time.Therefore, the higher stressed ginseng of number will successfully be read again The weight of array is adjusted to higher weights value so that next time execute read again operation when can preferentially choose have higher probability become can Stressed operation is executed with the stressed parameter group of stressed parameter group.
Assuming that memory management circuitry 502 determines to read again according to the Seq_821 that puts in order when next time executes stressed operation Parameter group H is available stressed parameter group.Memory management circuitry 502 can read the success of stressed parameter group H again number and be updated to " 2 ", as shown in weight record sheet 831.Memory management circuitry 502 successfully reads number again according to stressed parameter group H is updated " 2 " judge that the success for reading parameter group H again reads number again and is greater than the stressed number of success for reading parameter group F and G again.Therefore, it stores The weight of stressed parameter group H is adjusted to weighted value " 6 " by device management circuit 502, and the weighted value of stressed parameter group F and G is added 1 Its weight is adjusted to weighted value " 7 " and weighted value " 8 " respectively.In turn, memory management circuitry 502 is according to power adjusted The stressed parameter group A~H's of heavy new settings puts in order as the Seq_831 that puts in order.
In above-mentioned exemplary embodiment, memory management circuitry 502 can deposit the weight of stressed parameter group adjusted Storage is into reproducible nonvolatile memorizer module 406.However, in another exemplary embodiment, memory management circuitry 502 The weight of stressed parameter group adjusted can not also be stored into reproducible nonvolatile memorizer module 406.
Fig. 9 is that the adjustment shown in another exemplary embodiment according to the present invention reads the weight of parameter group again and puts in order Schematic diagram.It in the exemplary embodiment of Fig. 9, is illustrated by taking MLC NAND quick-flash memory as an example.That is, same Storage unit on character line can form lower entity program unit and upper entity program unit.Also, read parameter group A again ~H respectively corresponds 2 weights such as the first weight and the second weight.
Fig. 9 is please referred to, as shown in weight record sheet 910, identical first power can initially be corresponded to by reading parameter group A~H again Weight and the second weight, therefore the putting in order of corresponding first weight (also referred to as first order sequence) and the row of corresponding second weight Column sequence (also referred to as second order sequence) can initially correspond to the identical Seq_911 that puts in order.
In this exemplary embodiment, memory management circuitry 502 can be respectively according to lower entity program unit and upper reality Body programmed cell executes the result of stressed operation to adjust the first weight and the second weight of stressed parameter group A~H.
When read data can not be correctly corrected from entity program unit once, memory management circuitry 502 can putting in order Seq_911 and choose to adjust and read parameter group again to execute and read operation again to determine according to corresponding first weight Make available stressed parameter group (the also referred to as first available stressed parameter group).Assuming that determining when this executes and reads operation again Reading parameter group E again is the first available stressed parameter group.As shown in weight record sheet 920, memory management circuitry 502 can will be read again The first weight of parameter group E is adjusted to weighted value " 1 ", and the first weight of stressed parameter group A~D is adjusted separately as weight It is worth " 2 ", weighted value " 3 ", weighted value " 4 ", weighted value " 5 ".Base this, read again parameter group A~H first order sequence be set to Put in order Seq_921.If next time need to execute stressed operation to any lower entity program unit, memory management circuitry 502 will determine the first available stressed parameter group according to Seq_921 is put in order.
At this point, the second order sequence for reading parameter group A~H again is still arrangement since the second weight is not yet adjusted Sequence Seq_911.When the read data from one above entity program unit (also referred to as second instance programmed cell) When (also referred to as the second data) can not be correctly corrected, memory management circuitry 502 can according to second order sequence (namely row Column sequence Seq_911) it reads parameter group again to choose to adjust and executes and read operation again to determine available stressed parameter group (also referred to as Second available stressed parameter group).Assuming that memory management circuitry 502, which is sequentially chosen, reads ginseng again when this executes and reads operation again Array A, B, C are used as to adjust and read parameter group again and determine that reading parameter group C again can be used stressed parameter group for second.As weight is remembered It records shown in table 930, the second weight of stressed parameter group C can be adjusted to weighted value " 1 " by memory management circuitry 502, and will The second weight for reading parameter group A, B again adjusts separately as weighted value " 2 ", weighted value " 3 ".Base this, it is corresponding to read parameter group A~H again Putting in order for second weight is set to the Seq_931 that puts in order.If next time need to hold any upper entity program unit When row reads operation again, memory management circuitry 502 will determine the second available stressed parameter according to Seq_931 is put in order Group.
That is, memory management circuitry 502 can be to belong to according to execute the entity program unit for reading operation again Lower entity program unit or upper entity program unit put in order or correspond to the determine to use corresponding first weight Two weights put in order.Although above-mentioned exemplary embodiment is come with MLC NAND quick-flash memory for example, however, originally Invent it is without being limited thereto, can also come according to above-mentioned principle to other multilayered memory unit NAND type flash memories execute read again behaviour Make.For example, by taking MLC NAND quick-flash memory as an example, 3 weights (such as the first power can be respectively corresponded by reading parameter group A~H again Weight, the second weight and third weight), memory management circuitry 502 foundation can correspond to putting in order, corresponding to for the first weight respectively The putting in order of second weight corresponds to the putting in order to lower entity program unit, middle entity program list of third weight First, upper entity program unit, which executes, reads operation again, and updates the first weight, the second weight, third weight respectively.
In addition, although above-mentioned exemplary embodiment is by each available stressed parameter group for executing and reading operation again and being determined The weight of (namely recently using stressed parameter group) is adjusted to highest weight weight values.However, the weight for reading parameter group again is also possible to It is adjusted according to number or other modes are successfully read again, the present invention is not limited thereto.
Figure 10 is the schematic diagram of the stressed method of memory shown in an exemplary embodiment according to the present invention.
Figure 10 is please referred to, in step S1001, memory management circuitry 502 can be according to the weight setting for reading parameter group again Read putting in order for parameter group again.
In the step s 1003, it is electric according to reading to indicate to send a reading instruction sequence for memory management circuitry 502 Pressure reads data from the entity program unit on character line.In an exemplary embodiment, this entity program unit can be The lower entity program unit or upper entity program unit of MLC NAND quick-flash memory.In another exemplary embodiment, this Entity program unit can be lower entity program unit, middle entity program unit or the upper reality of TLC NAND quick-flash memory Body programmed cell.
In step S1005, whether memory management circuitry 502 judges read data can be by corresponding error correction Code correctly corrects.For example, it is that the entity program on Data programming to character line will be written that this, which corresponds to error-correcting code, When unit, the error-correcting code according to caused by write-in data as error checking and correcting circuit 508.
If read data can be corresponded to error-correcting code correctly timing, in step S1007, memory by this Management circuit 502 can export the data corrected.
If read data can not be corresponded to error-correcting code correctly timing, 502 meeting of memory management circuitry Execute step S1009.In step S1009, memory management circuitry 502 can putting in order from stressed parameter group according to setting Middle selection, which adjusts, reads parameter group again.Then, in step S1011, memory management circuitry 502 can read parameter group again according to adjusting Again new data is read from entity program unit.In an exemplary embodiment, memory management circuitry 502 can be according to tune Bulk wight read parameter group reading voltage change by read voltage be adjusted to newly to read voltage, and according to newly reading voltage come from Entity program unit reads data.
After reading new data, in step S1013, memory management circuitry 502 judges read new data Whether can correctly be corrected by corresponding error-correcting code.
If read new data can not correctly be corrected by corresponding error-correcting code, 502 meeting of memory management circuitry Step S1009 is executed again reads parameter group again to choose to adjust again.
If read new data can correctly be corrected by corresponding error-correcting code, in step S1015, memory pipe Reason circuit 502 can determine that adjusting stressed parameter group is available stressed parameter group, and adjust the weight of available stressed parameter group.This Outside, the exportable new data corrected of memory management circuitry 502.Thereafter, memory management circuitry 502 can execute step again S1001 reads putting in order for parameter group again to reset according to adjusted weight.
Figure 11 is the schematic diagram of the stressed method of memory shown in another exemplary embodiment according to the present invention.With Figure 10's Unlike exemplary embodiment, in this exemplary embodiment, there are a stressed parameter group 2 weights to be respectively intended to as right The lower entity program unit and upper entity program unit of MLC NAND quick-flash memory execute the foundation for reading operation again.
Figure 11 is please referred to, in step S1101, memory management circuitry 502 can be according to the first weight for reading parameter group again The first order sequence for reading parameter group again is set, and reads the second of parameter group again according to the second weight setting of stressed parameter group It puts in order.
In step S1103, memory management circuitry 502 sends a reading instruction sequence to indicate to read according to default Voltage reads data from the entity program unit on character line.In this exemplary embodiment, read entity program Unit can be the lower entity program unit or upper entity program unit of MLC NAND quick-flash memory.For reading lower entity Programmed cell can be different reading voltage levels from the default reading voltage of upper entity program unit.
In step S1105, whether memory management circuitry 502 judges read data can be by corresponding error correction Code correctly corrects.For example, it is that the entity program on Data programming to character line will be written that this, which corresponds to error-correcting code, When unit, the error-correcting code according to caused by write-in data as error checking and correcting circuit 508.
If read data can correctly be corrected by corresponding error-correcting code, in step S1107, memory management Circuit 502 can export the data corrected.
If read data can not correctly be corrected by corresponding error-correcting code, memory management circuitry 502 can be held Row step S1109.In step S1109, memory management circuitry 502 judges the entity program unit of read operation to be executed It is lower entity program unit or upper entity program unit.
In step S1111, if the entity program unit of read operation to be executed is lower entity program unit, deposit Reservoir management circuit 502 can choose the first adjustment from stressed parameter group according to first order sequence and read parameter group again.Then, In In step S1113, memory management circuitry 502 can read parameter group again according to the first adjustment and read from this lower entity program unit Take the first new data.Also, in step S1115, whether memory management circuitry 502 judges read first new data It can correctly be corrected by corresponding error-correcting code.If read first new data can not be by corresponding error-correcting code correctly Correction, memory management circuitry 502 can execute again step S1109 and read parameter group again to choose the first adjustment again.If institute The first new data read can correctly be corrected by corresponding error-correcting code, in step S1117, memory management circuitry 502 Can determine that the first adjustment reads parameter group again is the first available stressed parameter group, and adjusts the first of the first available stressed parameter group Weight.Thereafter, memory management circuitry 502 can execute again step S1101 to reset according to adjusted first weight Read the first order sequence of parameter group again.
On the other hand, in step S1119, if the entity program unit of read operation to be executed is upper entity program When unit, memory management circuitry 502 can choose second adjustment from stressed parameter group according to second order sequence and read parameter again Group.Then, in step S1121, memory management circuitry 502 can read parameter group entity program from this again according to second adjustment Change in unit and reads the second new data.Also, in step S1123, memory management circuitry 502 judges read second Whether new data can correctly be corrected by corresponding error-correcting code.If read second new data can not be by corresponding wrong school Code correctly corrects, and memory management circuitry 502 can execute again step S1119 and read parameter again to choose second adjustment again Group.If read second new data can correctly be corrected by corresponding error-correcting code, in step S1125, memory pipe Reason circuit 502 can determine that second adjustment reads parameter group again as the second available stressed parameter group, and adjust the second available stressed ginseng Second weight of array.Thereafter, memory management circuitry 502 can execute step S1101 according to adjusted second power again Heavy new settings reads the second order sequence of parameter group again.
In conclusion weight of the present invention by adjusting stressed parameter group, the arrangement that can reset stressed parameter group is suitable Sequence.So that executing the primary available stressed parameter group read again and determined in operation to certain entity program unit, it can be to it Its entity program unit executes to read again in operation next time and is preferentially chosen for adjusting stressed parameter group.In addition, of the invention It can be also to belong to lower entity program list according to the entity program unit of read operation to be executed by setting different weights First, middle entity program unit or upper entity program unit are chosen from the putting in order of the different weight of correspondence respectively It adjusts and reads parameter group again, to determine available stressed parameter group.Thus, it is possible to reduce determine available stressed parameter group Time, and then effectively shorten read again operation the execution time.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims (24)

1. a kind of memory reads method again, which is characterized in that for the duplicative non-volatile memories including a plurality of character line Device module, the memory read method again and include:
According to the first order of the multiple stressed parameter group of multiple first weight settings of multiple stressed parameter groups sequence, wherein Each of the multiple stressed parameter group read again parameter group correspond among the multiple first weight one of them first Weight；
It is read from the first instance programmed cell on the first character line in a plurality of character line according to the first reading voltage Take the first data；
If first data can not correctly be corrected by the first corresponding error-correcting code, according to the first order sequence from The first adjustment is chosen in the multiple stressed parameter group reads parameter group again；
Parameter group is read again according to the first adjustment reads the first new data from the first instance programmed cell again；
If first new data can correctly be corrected by the described first corresponding error-correcting code, the first adjustment weight is determined Reading parameter group is the first available stressed parameter group；And
Adjust the first weight of the described first available stressed parameter group.
2. memory according to claim 1 reads method again, which is characterized in that further include:
If first new data can not correctly be corrected by the described first corresponding error-correcting code, according to the first order Sequence chooses the first adjustment again from the multiple stressed parameter group and reads parameter group again.
3. memory according to claim 1 reads method again, which is characterized in that the first adjustment reads parameter group again and includes At least one reads voltage change, wherein reading parameter group again again from the first instance sequencing list according to the first adjustment The step of first new data is read in member include:
At least one reads voltage change for the first reading voltage tune according to the stressed parameter group of the first adjustment It is whole to read voltage to be new；And
First new data is read from the first instance programmed cell again according to the new reading voltage.
4. memory according to claim 1 reads method again, which is characterized in that the first adjustment reads parameter group again and includes Reading speed adjusted value is read from the first instance programmed cell again wherein reading parameter group again according to the first adjustment The step of taking first new data include:
Clock frequency is adjusted according to the reading speed adjusted value of the first adjustment parameter group；And
First new data is read from the first instance programmed cell according to the adjusted clock frequency.
5. memory according to claim 1 reads method again, which is characterized in that the available stressed parameter group of adjustment described first The first weight the step of include:
First weight of the described first available stressed parameter group is adjusted to the second weighted value from the first weighted value, wherein described Second weighted value is higher than first weighted value.
6. memory according to claim 1 reads method again, which is characterized in that further include:
Record the described first available stressed parameter group first successfully reads number again,
The step of wherein adjusting the first weight of the described first available stressed parameter group include:
The available stressed parameter of number adjustment described first is successfully read again according to described the first of the described first available stressed parameter group First weight of group.
7. memory according to claim 1 reads method again, which is characterized in that further include:
Recording the described first available stressed parameter group is to use to read parameter group again recently,
The step of wherein adjusting the first weight of the described first available stressed parameter group include:
Parameter group is read again according to the nearest use, and the first weight of the described first available stressed parameter group is adjusted to highest weight Weight values.
8. memory according to claim 1 reads method again, which is characterized in that further include:
Sequentially according to the second order of the multiple stressed parameter group of multiple second weight settings of the multiple stressed parameter group, Wherein the stressed parameter group of each of the multiple stressed parameter group corresponds to one of them among the multiple second weight Second weight；
The second data are read from the second instance programmed cell on first character line according to the second reading voltage；
If second data can not correctly be corrected by the second corresponding error-correcting code, according to the second order sequence from Second adjustment is chosen in the multiple stressed parameter group reads parameter group again；
Parameter group is read again according to the second adjustment reads the second new data from the second instance programmed cell again；
If second new data can correctly be corrected by the described second corresponding error-correcting code, the second adjustment weight is determined Reading parameter group is the second available stressed parameter group；And
Adjust the second weight of the described second available stressed parameter group.
9. memory according to claim 8 reads method again, which is characterized in that the first order sequence is different from described Second order sequence.
10. memory according to claim 8 reads method again, which is characterized in that the first instance programmed cell is Lower entity program unit, and the second instance programmed cell is upper entity program unit.
11. memory according to claim 1 reads method again, which is characterized in that further include:
It is adjusted described in the multiple stressed parameter group according to the first weight of the adjusted described first available stressed parameter group Other except first available stressed parameter group read the first weight of parameter group again；And
The multiple first weight of adjusted the multiple stressed parameter group is stored non-volatile to the duplicative Memory module.
12. a kind of memorizer control circuit unit, which is characterized in that non-easily for controlling the duplicative including a plurality of character line The property lost memory module, the memorizer control circuit unit include:
Host interface, to couple host system；
Memory interface, to be coupled to the reproducible nonvolatile memorizer module；And
Memory management circuitry is coupled to the host interface and the memory interface,
Wherein the memory management circuitry is to the multiple heavy according to multiple first weight settings of multiple stressed parameter groups The first order sequence of parameter group is read, each of the multiple stressed parameter group reads parameter group again and corresponds to the multiple first One of them first weight among weight,
Wherein the memory management circuitry reads instruction sequence to send to indicate to read voltage from described more according to first The first data are read in the first instance programmed cell on the first character line in character line,
If wherein first data can not correctly be corrected by the first corresponding error-correcting code, the memory management circuitry Parameter group is read again to choose the first adjustment from the multiple stressed parameter group according to the first order sequence,
Wherein the memory management circuitry is to read parameter group again again from the first instance journey according to the first adjustment The first new data is read in sequence unit,
If wherein first new data can correctly be corrected by the described first corresponding error-correcting code, the memory management Circuit is the first available stressed parameter group to determine that the first adjustment reads parameter group again,
Wherein first weight of the memory management circuitry to adjust the described first available stressed parameter group.
13. memorizer control circuit unit according to claim 12, which is characterized in that if first new data without Method is correctly corrected by the described first corresponding error-correcting code, and the memory management circuitry is to suitable according to the first order Sequence chooses the first adjustment again from the multiple stressed parameter group and reads parameter group again.
14. memorizer control circuit unit according to claim 12, which is characterized in that the first adjustment reads parameter again Group includes at least one reading voltage change, and the memory management circuitry is to read parameter group again according to the first adjustment At least one reading voltage change is adjusted to the first reading voltage newly to read voltage, and sends another reading and refer to Sequence is enabled to indicate to read the described first new number from the first instance programmed cell again according to the new reading voltage According to.
15. memorizer control circuit unit according to claim 12, which is characterized in that the memory management circuitry is used The first weight of the described first available stressed parameter group is adjusted to the second weighted value from the first weighted value, wherein described the Two weighted values are higher than first weighted value.
16. memorizer control circuit unit according to claim 12, which is characterized in that the memory management circuitry is used Number is successfully read again with record the described first available stressed parameter group first, and successfully reads number tune again according to described first First weight of the whole described first available stressed parameter group.
17. memorizer control circuit unit according to claim 12, which is characterized in that the memory management circuitry is used With according to the second order of the multiple stressed parameter group of multiple second weight settings of the multiple stressed parameter group sequence, Described in each of multiple stressed parameter groups read again parameter group correspond among the multiple second weight one of them the Two weights,
Wherein the memory management circuitry indicates that reading voltage according to second reads to send another reading instruction sequence The second data are read from the second instance programmed cell on first character line,
If wherein second data can not correctly be corrected by the second corresponding error-correcting code, the memory management circuitry Parameter group is read again to choose second adjustment from the multiple stressed parameter group according to the second order sequence,
Wherein the memory management circuitry is to read parameter group again again from the second instance journey according to the second adjustment The second new data is read in sequence unit,
If wherein second new data can correctly be corrected by the described second corresponding error-correcting code, the memory management Circuit is the second available stressed parameter group to determine that the second adjustment reads parameter group again,
Wherein second weight of the memory management circuitry to adjust the described second available stressed parameter group.
18. memorizer control circuit unit according to claim 17, which is characterized in that the first order sequence is different In the second order sequence.
19. a kind of memory storage apparatus characterized by comprising
Connecting interface unit, to be coupled to host system；
Reproducible nonvolatile memorizer module, including a plurality of character line；
Memorizer control circuit unit is coupled to the connecting interface unit and the type nonvolatile mould Block,
Wherein the memorizer control circuit unit is to more described in multiple first weight settings according to multiple stressed parameter groups The first order sequence of a stressed parameter group, wherein described in the stressed parameter group of each of the multiple stressed parameter group is corresponding One of them first weight among multiple first weights,
Wherein the memorizer control circuit unit reads instruction sequence to send to indicate to read voltage from institute according to first It states in the first instance programmed cell on the first character line in a plurality of character line and reads the first data,
If wherein first data can not correctly be corrected by the first corresponding error-correcting code, the memorizer control circuit Unit reads parameter group again to choose the first adjustment from the multiple stressed parameter group according to the first order sequence,
Wherein the memorizer control circuit unit is again real from described first to read parameter group again according to the first adjustment The first new data is read in body programmed cell,
If wherein first new data can correctly be corrected by the described first corresponding error-correcting code, the memory control Circuit unit is the first available stressed parameter group to determine that the first adjustment reads parameter group again,
Wherein first weight of the memorizer control circuit unit to adjust the described first available stressed parameter group.
20. memory storage apparatus according to claim 19, which is characterized in that if first new data can not be by Described first corresponding error-correcting code correctly corrects, and the memorizer control circuit unit is to suitable according to the first order Sequence chooses the first adjustment again from the multiple stressed parameter group and reads parameter group again.
21. memory storage apparatus according to claim 19, which is characterized in that the first adjustment reads parameter group packet again At least one reading voltage change is included, wherein the memorizer control circuit unit is to read parameter again according to the first adjustment At least one reading voltage change of group is adjusted to the first reading voltage newly to read voltage, and sends another reading Instruction fetch sequence is to indicate to read described first from the first instance programmed cell again according to the new reading voltage New data.
22. memory storage apparatus according to claim 19, which is characterized in that the memorizer control circuit unit is used The first weight of the described first available stressed parameter group is adjusted to the second weighted value from the first weighted value, wherein described the Two weighted values are higher than first weighted value.
23. memory storage apparatus according to claim 19, which is characterized in that the memorizer control circuit unit is used Number is successfully read again with record the described first available stressed parameter group first, and successfully reads number tune again according to described first First weight of the whole described first available stressed parameter group.
24. memory storage apparatus according to claim 19, which is characterized in that the memorizer control circuit unit is used With according to the second order of the multiple stressed parameter group of multiple second weight settings of the multiple stressed parameter group sequence, Described in each of multiple stressed parameter groups read again parameter group correspond among the multiple second weight one of them the Two weights,
Wherein the memorizer control circuit unit indicates to read voltage according to second to send another reading instruction sequence The second data are read from the second instance programmed cell on first character line,
If wherein second data can not correctly be corrected by the second corresponding error-correcting code, the memorizer control circuit Unit reads parameter group again to choose second adjustment from the multiple stressed parameter group according to the second order sequence,
Wherein the memorizer control circuit unit is again real from described second to read parameter group again according to the second adjustment The second new data is read in body programmed cell,
If wherein second new data can correctly be corrected by the described second corresponding error-correcting code, the memory control Circuit unit is the second available stressed parameter group to determine that the second adjustment reads parameter group again,
Wherein second weight of the memorizer control circuit unit to adjust the described second available stressed parameter group.
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