CN106158040A - Read voltage level estimating and measuring method, memory storage apparatus and control circuit unit - Google Patents

Read voltage level estimating and measuring method, memory storage apparatus and control circuit unit Download PDF

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Publication number
CN106158040A
CN106158040A CN201510189551.1A CN201510189551A CN106158040A CN 106158040 A CN106158040 A CN 106158040A CN 201510189551 A CN201510189551 A CN 201510189551A CN 106158040 A CN106158040 A CN 106158040A
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unit
decoding
decoded
control circuit
voltage level
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CN106158040B (en
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林纬
王天庆
赖国欣
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

The present invention provides a kind of read voltage level estimating and measuring method, memory storage apparatus and control circuit unit.Described method includes: read the first area in reproducible nonvolatile memorizer module according to the first read voltage level, and to obtain the first coding unit, wherein said first coding unit belongs to block code；Described first coding unit is performed the first decoding program and records the first decoded information；Reading described first area according to the second read voltage level, to obtain the second coding unit, wherein said second coding unit belongs to described block code；Described second coding unit is performed the second decoding program and records the second decoded information；And estimate according to described first decoded information and described second decoded information and obtain third reading and take voltage quasi position.Thereby, the operating capability of reproducible nonvolatile memorizer module for using block code can be promoted.

Description

Read voltage level estimating and measuring method, memory storage apparatus and control circuit unit
Technical field
The invention relates to a kind of storage management method, and accurate in particular to a kind of read voltage Position estimating and measuring method, memory storage apparatus and control circuit unit.
Background technology
Digital camera, mobile phone and MP3 player are the rapidest in growth over the years so that disappear The demand of storage media is increased by expense person the most rapidly.Due to reproducible nonvolatile memorizer module (example Such as, flash memory) to have data non-volatile, power saving, volume little, and the spy such as mechanical structure Property, so being especially suitable for being built in above-mentioned illustrated various portable multimedia devices.
In general, in order to ensure the correctness of data, by non-to duplicative for the write of a certain pen data Before volatile, these data can be encoded.And the data after encoding can be written into answering Write in formula non-volatile memory module.When being intended to read this pen data, the data after coding can be read Out and be decoded.If data can be successfully decoded, represent that the number of error bit therein is few And these a little error bits can be corrected.But, if data cannot be successfully decoded (that is, decoding unsuccessfully), The most different read voltage may be used to re-read data.But, in some cases, even if Available multiple read voltage were used, and the data read out still cannot successfully be solved Code, causes digital independent failure.Particularly, for using block code to carry out the data encoded, this The situation of sample is even more serious.
Summary of the invention
The present invention provides a kind of read voltage level estimating and measuring method, memory storage apparatus and control circuit list Unit, can promote the operating capability of reproducible nonvolatile memorizer module for using block code.
One example of the present invention embodiment provides a kind of read voltage level estimating and measuring method, and it is for making carbon copies Formula non-volatile memory module, described read voltage level estimating and measuring method includes: read electricity according to first Pressure level reads the first area in described reproducible nonvolatile memorizer module, to obtain first Coding unit, wherein said first coding unit belongs to block code；Described first coding unit is performed the One decoding program and record the first decoded information；Described first is read according to the second read voltage level Region, to obtain the second coding unit, wherein said second coding unit belongs to described block code；To institute State the second coding unit perform the second decoding program and record the second decoded information；And according to described One decoded information and described second decoded information are estimated and are obtained third reading and take voltage quasi position.
In one example of the present invention embodiment, described block code is made up of many sub-coding units, described The first bit in sub-coding unit is to be determined by multiple encoding procedures.
In one example of the present invention embodiment, described encoding procedure has different coding directions.
In one example of the present invention embodiment, described first decoded information includes the first numerical value, described Two decoded informations include second value, wherein according to described first decoded information and described second decoded information Estimate and obtain described third reading and take the step of voltage quasi position and include: relatively described first numerical value is with described According to comparative result, second value also determines that described third reading takes voltage quasi position.
In one example of the present invention embodiment, described first numerical value and the first of described first decoding program Decoded result is relevant, and described second value is relevant with the second decoded result of described second decoding program.
In one example of the present invention embodiment, described first numerical value is to be positively correlated with described first decoding journey First successfully decoded unit number of sequence, described second value is be positively correlated with described second decoding program Two successfully decoded unit number.
In one example of the present invention embodiment, described read voltage level estimating and measuring method also includes: according to Described first decoded result obtains the first row successfully decoded unit number and first row successfully decoded unit number；Root Described first is determined according to described the first row successfully decoded unit number and described first row successfully decoded unit number Numerical value；The second row successfully decoded unit number and secondary series successfully decoded is obtained according to described second decoded result Unit number；And according to described second row successfully decoded unit number and described secondary series successfully decoded unit number Determine described second value.
In one example of the present invention embodiment, according to described first decoded information and described second decoding letter Breath is estimated and is obtained described third reading and takes the step of voltage quasi position and include: will described first read voltage standard Position and one of them of described second read voltage level are determined as described third reading and take voltage quasi position.
In one example of the present invention embodiment, described read voltage level estimating and measuring method also includes: judge The whether failure of described first decoding program, wherein reads described the according to described second read voltage level The step in one region is to perform after judging described first decoding program failure.
In one example of the present invention embodiment, described read voltage level estimating and measuring method also includes: according to Described third reading takes voltage quasi position and performs relevant with described reproducible nonvolatile memorizer module pre- If operation, wherein said predetermined registration operation includes at least one of following operation: read described firstth district Territory is to obtain corresponding to the multiple soft bit of the 3rd decoding unit and to come the described 3rd according to described soft bit Decoding unit performs iterative decoding；Determine multiple memory element in described first area extent of deterioration or The voltage's distribiuting state of described memory element；And determine the pre-set programs corresponding to described first area Voltage.
In one example of the present invention embodiment, described read voltage level estimating and measuring method also includes: according to Described third reading takes voltage quasi position to read described first area, to obtain the 3rd coding unit；And it is right Described 3rd coding unit performs the 3rd decoding program.
In one example of the present invention embodiment, described first decoding program is with described second decoding program all Decode for hard bit mode.
Another example of the present invention embodiment provides a kind of memory storage apparatus, and it includes connecting interface list Unit, reproducible nonvolatile memorizer module and memorizer control circuit unit.Described connection interface list Unit is electrically connected to host computer system.Described memorizer control circuit unit is electrically connected to described connection Interface unit and described reproducible nonvolatile memorizer module.Wherein said memorizer control circuit list Unit is in order to send the first reading job sequence, and wherein said first reads job sequence in order to indicate according to the One read voltage level reads the first area in described reproducible nonvolatile memorizer module, with Obtaining the first coding unit, wherein said first coding unit belongs to block code, wherein said memorizer control Circuit unit processed is also in order to perform the first decoding program to described first coding unit and to record the first decoding Information, wherein said memorizer control circuit unit is also in order to send the second reading job sequence, Qi Zhongsuo State the second reading job sequence and read described first area in order to indicate according to the second read voltage level, To obtain the second coding unit, wherein said second coding unit belongs to described block code, wherein said deposits Memory control circuit unit also in order to perform the second decoding program and to record to described second coding unit Two decoded informations, wherein said memorizer control circuit unit also in order to according to described first decoded information with Described second decoded information is estimated and is obtained third reading and takes voltage quasi position.
In one example of the present invention embodiment, described block code is made up of many sub-coding units, described The first bit in sub-coding unit is to be determined by multiple encoding procedures.
In one example of the present invention embodiment, described encoding procedure has different coding directions.
In one example of the present invention embodiment, described first decoded information includes the first numerical value, described Two decoded informations include second value, and wherein said memorizer control circuit unit is according to described first decoding Information is estimated with described second decoded information and is obtained described third reading and takes the operation of voltage quasi position and include: Compare described first numerical value and described second value and determine described third reading power taking pressure according to comparative result Level.
In one example of the present invention embodiment, described first numerical value and the first of described first decoding program Decoded result is relevant, and described second value is relevant with the second decoded result of described second decoding program.
In one example of the present invention embodiment, described first numerical value is to be positively correlated with described first decoding journey First successfully decoded unit number of sequence, described second value is be positively correlated with described second decoding program Two successfully decoded unit number.
In one example of the present invention embodiment, described memorizer control circuit unit is also in order to according to described First decoded result obtains the first row successfully decoded unit number and first row successfully decoded unit number, Qi Zhongsuo State memorizer control circuit unit also in order to according to described the first row successfully decoded unit number and described first row Successfully decoded unit number determines described first numerical value, wherein said memorizer control circuit unit also in order to The second row successfully decoded unit number and secondary series successfully decoded unit is obtained according to described second decoded result Number, wherein said memorizer control circuit unit also in order to according to described second row successfully decoded unit number with Described secondary series successfully decoded unit number determines described second value.
In one example of the present invention embodiment, described memorizer control circuit unit solves according to described first Code information and described second decoded information are estimated and are obtained described third reading and take the operation bag of voltage quasi position Include: one of them of described first read voltage level and described second read voltage level is determined as institute State third reading and take voltage quasi position.
In one example of the present invention embodiment, described memorizer control circuit unit is also described in order to judge First decoding program is the most failed, and wherein said memorizer control circuit unit sends described second reading and refers to The operation making sequence is to perform after judging described first decoding program failure.
In one example of the present invention embodiment, described memorizer control circuit unit is also in order to according to described Third reading takes voltage quasi position and performs the default behaviour relevant with described reproducible nonvolatile memorizer module Making, wherein said predetermined registration operation includes at least one of following operation: described firstth district is read in instruction Territory is to obtain corresponding to the multiple soft bit of the 3rd decoding unit and to come the described 3rd according to described soft bit Decoding unit performs iterative decoding；Determine multiple memory element in described first area extent of deterioration or The voltage's distribiuting state of described memory element；And determine the pre-set programs corresponding to described first area Voltage.
In one example of the present invention embodiment, described memorizer control circuit unit is also in order to indicate basis Described third reading takes voltage quasi position to read described first area, to obtain the 3rd coding unit, Qi Zhongsuo State memorizer control circuit unit also in order to described 3rd coding unit is performed the 3rd decoding program.
In one example of the present invention embodiment, described first decoding program is with described second decoding program all Decode for hard bit mode.
Another example of the present invention embodiment provides a kind of memorizer control circuit unit, and it can for control Manifolding formula non-volatile memory module, described memorizer control circuit unit includes HPI, storage Device interface, error checking and correcting circuit and memory management circuitry.Described HPI is in order to electrically to connect It is connected to host computer system.Described memory interface is electrically connected to described duplicative non-volatile memories Device module.Described memory management circuitry be electrically connected to described HPI, described memory interface and Described error checking and correcting circuit, wherein said memory management circuitry is in order to send the first reading instruction Sequence, wherein said first reads job sequence reads institute in order to indicate according to the first read voltage level State the first area in reproducible nonvolatile memorizer module, to obtain the first coding unit, wherein Described first coding unit belongs to block code, and wherein said error checking and correcting circuit are in order to described the One coding unit performs the first decoding program, and described memory management circuitry is also in order to record the first solution Code information, wherein said memory management circuitry is also in order to send the second reading job sequence, wherein said Second reads job sequence reads described first area in order to indicate according to the second read voltage level, with Obtaining the second coding unit, wherein said second coding unit belongs to described block code, wherein said mistake Check with correcting circuit also in order to described second coding unit to be performed the second decoding program, and described in deposit Reservoir management circuit is also in order to record the second decoded information, and wherein said memory management circuitry is also in order to root Estimate according to described first decoded information and described second decoded information and obtain third reading and take voltage quasi position.
In one example of the present invention embodiment, described block code is made up of many sub-coding units, described The first bit in sub-coding unit is to be determined by multiple encoding procedures.
In one example of the present invention embodiment, described encoding procedure has different coding directions.
In one example of the present invention embodiment, described first decoded information includes the first numerical value, described Two decoded informations include second value, and wherein said memory management circuitry is according to described first decoded information Estimate with described second decoded information and obtain described third reading and take the operation of voltage quasi position and include: compare Described first numerical value determines described third reading power taking pressure standard with described second value and according to comparative result Position.
In one example of the present invention embodiment, described first numerical value and the first of described first decoding program Decoded result is relevant, and described second value is relevant with the second decoded result of described second decoding program.
In one example of the present invention embodiment, described first numerical value is to be positively correlated with described first decoding journey First successfully decoded unit number of sequence, described second value is be positively correlated with described second decoding program Two successfully decoded unit number.
In one example of the present invention embodiment, described memory management circuitry is also in order to according to described first Decoded result obtains the first row successfully decoded unit number and first row successfully decoded unit number, wherein said deposits Reservoir management circuit is also in order to according to described the first row successfully decoded unit number and described first row successfully decoded Unit number determines described first numerical value, and wherein said memory management circuitry is also in order to according to described second Decoded result obtains the second row successfully decoded unit number and secondary series successfully decoded unit number, wherein said deposits Reservoir management circuit is also in order to according to described second row successfully decoded unit number and described secondary series successfully decoded Unit number determines described second value.
In one example of the present invention embodiment, described memory management circuitry is according to described first decoding letter Breath is estimated with described second decoded information and is obtained described third reading and takes the operation of voltage quasi position and include: general Described first read voltage level is determined as the described 3rd with one of them of described second read voltage level Read voltage level.
In one example of the present invention embodiment, described memory management circuitry is also in order to judge described first Decoding program is the most failed, and wherein said memory management circuitry sends described second and reads job sequence Operation is to perform after judging described first decoding program failure.
In one example of the present invention embodiment, described memory management circuitry is also in order to according to the described 3rd Read voltage level performs the predetermined registration operation relevant with described reproducible nonvolatile memorizer module, Wherein said predetermined registration operation includes at least one of following operation: instruction read described first area with Obtain corresponding to the multiple soft bit of the 3rd decoding unit and described error checking and correcting circuit also in order to Described 3rd decoding unit is performed iterative decoding according to described soft bit；Determine in described first area The extent of deterioration of multiple memory element or the voltage's distribiuting state of described memory element；And determine correspondence Pre-set programs voltage in described first area.
In one example of the present invention embodiment, described memory management circuitry is also in order to indicate according to described Third reading takes voltage quasi position to read described first area, to obtain the 3rd coding unit, and wherein said mistake Flase drop is looked into correcting circuit also in order to described 3rd coding unit is performed the 3rd decoding program.
In one example of the present invention embodiment, described first decoding program is with described second decoding program all Decode for hard bit mode.
Based on above-mentioned, read voltage level estimating and measuring method, memorizer storage that the embodiment of the present invention provides fill Put and control circuit unit, utilizing different read voltage levels to read memorizer and to attempt institute After the decoding data obtained, the decoded information corresponding to different decoding programs can be recorded. Thereafter, these a little decoded informations i.e. can be used as estimating the foundation of a suitable read voltage level.Mat This, the operating capability for the reproducible nonvolatile memorizer module of use block code can be elevated.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate Accompanying drawing is described in detail below.
Accompanying drawing explanation
Fig. 1 is according to the host computer system shown by one example of the present invention embodiment and memory storage apparatus Schematic diagram；
Fig. 2 is according to computer, input/output device and the storage shown by one example of the present invention embodiment The schematic diagram of device storage device；
Fig. 3 is according to the host computer system shown by one example of the present invention embodiment and memory storage apparatus Schematic diagram；
Fig. 4 is the schematic block diagram of the memory storage apparatus shown in Fig. 1；
Fig. 5 is according to the type nonvolatile mould shown by one example of the present invention embodiment The schematic block diagram of block；
Fig. 6 is the schematic diagram according to the memory cell array shown by one example of the present invention embodiment；
Fig. 7 is the summary according to the memorizer control circuit unit shown by one example of the present invention embodiment Block chart；
Fig. 8 is according to the management duplicative non-volatile memories shown by one example of the present invention embodiment The schematic diagram of device module；
Fig. 9 is that the critical voltage according to the multiple memory element shown by one example of the present invention embodiment divides The schematic diagram of cloth；
Figure 10 is the schematic diagram according to the coding unit shown by one example of the present invention embodiment；
Figure 11 is according to the schematic diagram reading multiple soft bits shown by one example of the present invention embodiment；
Figure 12 is according to the read voltage level estimating and measuring method shown by one example of the present invention embodiment Flow chart.
Description of reference numerals:
10: memory storage apparatus；
11: host computer system；
12: computer；
122: microprocessor；
124: random access memory；
126: system bus；
128: data transmission interface；
13: input/output device；
21: mouse；
22: keyboard；
23: display；
24: printer；
25: portable disk；
26: storage card；
27: solid state hard disc；
31: digital camera；
32:SD card；
33:MMC card；
34: memory stick；
35:CF card；
36: embedded storage device；
402: connect interface unit；
404: memorizer control circuit unit；
406: reproducible nonvolatile memorizer module；
502: memory cell array；
504: word-line control circuit；
506: bit line control circuit；
508: row decoder；
510: data input/output buffer；
512: control circuit；
602: memory element；
604: bit line；
606: word-line；
608: common source line；
612,614: transistor；
702: memory management circuitry；
704: HPI；
706: memory interface；
708: error checking and correcting circuit；
710: buffer storage；
712: electric power management circuit；
800 (0)～800 (R): entity erased cell；
810 (0)～810 (D): logical block；
802: memory block；
806: system area；
901,902,911,912,1110,1120: distribution；
913: overlapping region；
Vread-0～Vread-3、V1～V5: read voltage level；
1010: coding unit；
1011～101n: sub-coding unit；
b11～bnm: bit；
1101～1106: voltage range；
b1～b5: soft bit；
S1201～S1206: step.
Detailed description of the invention
It is said that in general, memory storage apparatus (also referred to as, storage system) includes that duplicative is non-volatile Property memory module (rewritable non-volatile memory module) with controller (also referred to as, control electricity Road).Being commonly stored device storage device is to be used together with host computer system, so that data can be write by host computer system Enter to memory storage apparatus or from memory storage apparatus, read data.
Fig. 1 is according to the host computer system shown by one example of the present invention embodiment and memory storage apparatus Schematic diagram.Fig. 2 is according to the computer shown by one example of the present invention embodiment, input/output device Schematic diagram with memory storage apparatus.
Refer to Fig. 1, host computer system 11 generally comprises computer 12, and (input/output is called for short with input/output I/O) device 13.Computer 12 includes microprocessor 122, random access memory (random access Memory, is called for short RAM) 124, system bus 126 and data transmission interface 128.Input/output device 13 include mouse 21, keyboard 22, display 23 and printer 24 such as Fig. 2.It will be appreciated that The unrestricted input/output device of device 13 shown in Fig. 2, input/output device 13 can also include that other fill Put.
In an exemplary embodiment, memory storage apparatus 10 is by data transmission interface 128 and main frame Other elements of system 11 are electrically connected with.By microprocessor 122, random access memory 124 with defeated Enter/running of output device 13 can write data into memory storage apparatus 10 or from memorizer storage dress Put reading data in 10.Such as, memory storage apparatus 10 can be portable disk 25 as shown in Figure 2, The duplicative of storage card 26 or solid state hard disc (Solid State Drive is called for short SSD) 27 grades is non-volatile to be deposited Reservoir storage device.
Fig. 3 is according to the host computer system shown by one example of the present invention embodiment and memory storage apparatus Schematic diagram.
It is said that in general, host computer system 11 is for coordinating to store number with memory storage apparatus 10 substantially According to any system.Although in this exemplary embodiment, host computer system 11 is to explain with computer system, But, in another exemplary embodiment, host computer system 11 can be digital camera, camera, communicator, The system such as audio player or video player.Such as, it is digital camera (camera) 31 in host computer system Time, type nonvolatile storage device is then by its SD card 32 used, mmc card 33, memory stick (memory stick) 34, CF card 35 or embedded storage device 36 (as shown in Figure 3). Embedded storage device 36 includes embedded multi-media card (Embedded MMC is called for short eMMC).It is worth One is mentioned that, embedded multi-media card is directly to be electrically connected on the substrate of host computer system.
Fig. 4 is the schematic block diagram of the memory storage apparatus shown in Fig. 1.
Refer to Fig. 4, memory storage apparatus 10 includes connecting interface unit 402, memorizer controls electricity Road unit 404 and reproducible nonvolatile memorizer module 406.
In this exemplary embodiment, connecting interface unit 402 is to be compatible to Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, is called for short SATA) standard.However, it is necessary to be appreciated that, this Invention is not limited to this, and connecting interface unit 402 can also be to meet parallel advanced technology adnexa (Parallel Advanced Technology Attachment, be called for short PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers is called for short IEEE) 1394 standards, external components Interconnection (Peripheral Component Interconnect Express, be called for short PCI Express) standard, general Universal serial bus (Universal Serial Bus is called for short USB) standard, safety digit (Secure Digital, abbreviation SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I is called for short UHS-I) interface standard, ultrahigh speed Secondary (Ultra High Speed-II is called for short UHS-II) interface standard, memory stick (Memory Stick, abbreviation MS) interface standard, multimedia storage card (Multi Media Card, be called for short MMC) interface standard, embedded Multimedia storage card (Embedded Multimedia Card is called for short eMMC) interface standard, general flash memory Reservoir (Universal Flash Storage is called for short UFS) interface standard, compact flash (Compact Flash, letter Claim CF) interface standard, Integrated Device Electronics (Integrated Device Electronics, be called for short IDE) standard or Other standards being suitable for.Connect interface unit 402 and can be encapsulated in one with memorizer control circuit unit 404 In individual chip, or connection interface unit 402 is to be laid in one to comprise memorizer control circuit unit 404 Chip outside.
Memorizer control circuit unit 404 is in order to perform in the form of hardware or the multiple of form of firmware implementation patrol Volume grid or control instruction and according to the instruction of host computer system 11 at type nonvolatile mould Block 406 carries out the write of data, running of reading and erase etc..
Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404 and the data that write in order to host system 11.Reproducible nonvolatile memorizer module 406 can be single layer cell (Single Level Cell is called for short SLC) NAND type flash memory module (that is, the flash memory module of 1 Bit data can be stored in one memory element), multilevel-cell (Multi Level Cell, is called for short MLC) NAND type flash memory module (that is, can store 2 in one memory element The flash memory module of individual Bit data), three-layer unit (Triple Level Cell, be called for short TLC) NAND Type flash memory module (that is, can store the flash memory mould of 3 Bit datas in one memory element Block), other flash memory module or other there is the memory module of identical characteristics.
Fig. 5 is according to the type nonvolatile mould shown by one example of the present invention embodiment The schematic block diagram of block.Fig. 6 is according to the memory cell array shown by one example of the present invention embodiment Schematic diagram.
Refer to Fig. 5, reproducible nonvolatile memorizer module 406 include memory cell array 502, Word-line control circuit 504, bit line control circuit 506, row decoder (column decoder) 508, Data input/output buffer 510 and control circuit 512.
In this exemplary embodiment, memory cell array 502 can include the multiple storages storing data Unit 602, multiple selection grid leak pole (select gate drain is called for short SGD) transistor 612 and multiple selections Grid source electrode (select gate source, be called for short SGS) transistor 614 and to connect these a little memory element many Bar bit line 604, a plurality of word-line 606 and common source line 608 (as shown in Figure 6).Memory element 602 is to be arranged in intersecting of bit line 604 and word-line 606 by array way (or three-dimensional stacking in the way of) On point.When receiving write instruction from memorizer control circuit unit 404 or read instruction, control electricity Road 512 can control character line control circuit 504, bit line control circuit 506, row decoder 508, number Memory cell array 502 is write data to or from memory cell array according to input/output (i/o) buffer 510 Reading data in 502, wherein word-line control circuit 504 is in order to control the electricity bestowed to word-line 606 Pressure, bit line control circuit 506 in order to control the voltage bestowed to bit line 604, row decoder 508 According to the column address in instruction to select corresponding bit line, and data input/output buffer 510 is used With temporal data.
Each memory element in reproducible nonvolatile memorizer module 406 is with voltage (the most also Be referred to as critical voltage) change store one or more bit.Specifically, the control of each memory element An electric charge capture layer is had between grid processed (control gate) and passage.By bestowing a write voltage to control Grid processed, thus it is possible to vary the amount of electrons of electric charge capture layer, thus change the critical voltage of memory element. This changes the program also referred to as " writing the data to memory element " of critical voltage or " sequencing storage is single Unit ".Along with the change of critical voltage, each memory element of memory cell array 502 has multiple depositing Storage state.And may determine which storage state is memory element be belonging to by bestowing read voltage, Thereby obtain one or more bit that memory element is stored.
Fig. 7 is the summary according to the memorizer control circuit unit shown by one example of the present invention embodiment Block chart.
Refer to Fig. 7, memorizer control circuit unit 404 includes that memory management circuitry 702, main frame connect Mouth 704, memory interface 706 and error checking and correcting circuit 708.
Memory management circuitry 702 is in order to control the overall operation of memorizer control circuit unit 404.Tool For body, memory management circuitry 702 has multiple control instruction, and at memory storage apparatus 10 During running, these a little control instructions can be performed to carry out the write of data, running of reading and erase etc..With During the operation of lower explanation memory management circuitry 702, it is equal to memorizer control circuit unit 404 is described Operation.
In this exemplary embodiment, the control instruction of memory management circuitry 702 is to come in fact with form of firmware Make.Such as, memory management circuitry 702 has microprocessor unit (not shown) with read only memory (not Illustrate), and these a little control instructions are to be programmed so far in read only memory.When memory storage apparatus 10 During running, these a little control instructions can by microprocessor unit perform to carry out data write, read with The running such as erase.
In another exemplary embodiment, the control instruction of memory management circuitry 702 can also procedure code shape Formula is stored in the specific region of reproducible nonvolatile memorizer module 406 (such as, in memory module It is exclusively used in the system area of storage system data) in.Additionally, memory management circuitry 702 has microprocessor Unit (not shown), read only memory (not shown) and random access memory (not shown).Particularly, this Read only memory has boot code (boot code), and when memorizer control circuit unit 404 is enabled Time, microprocessor unit can first carry out this boot code will be stored in type nonvolatile mould Control instruction in block 406 is loaded in the random access memory of memory management circuitry 702.Afterwards, Microprocessor unit can operate these a little control instructions to carry out the write of data, running of reading and erase etc..
Additionally, in another exemplary embodiment, the control instruction of memory management circuitry 702 can also one Example, in hardware carrys out implementation.Such as, memory management circuitry 702 includes that microcontroller, solid element manage Circuit, memorizer write circuit, memory reading circuitry, memorizer are erased circuit and data processing circuit. Solid element management circuit, memorizer write circuit, memory reading circuitry, memorizer erase circuit with Data processing circuit is electrically connected to microcontroller.Wherein, solid element management circuit can in order to manage The entity erased cell of manifolding formula non-volatile memory module 406；Memorizer write circuit is in order to can Manifolding formula non-volatile memory module 406 assigns write instruction sequence to write data into duplicative In non-volatile memory module 406；Memory reading circuitry is in order to duplicative non-volatile memories Device module 406 assigns reading job sequence to read from reproducible nonvolatile memorizer module 406 Data；Memorizer erases circuit in order to reproducible nonvolatile memorizer module 406 is assigned finger of erasing Make sequence data to be erased from reproducible nonvolatile memorizer module 406；And data process electricity Road is intended to write to the data of reproducible nonvolatile memorizer module 406 and from making carbon copies in order to process The data read in formula non-volatile memory module 406.Write instruction sequence, read job sequence and Job sequence of erasing can distinctly include one or more procedure code or order code and in order to indicate duplicative non- Volatile 406 performs corresponding write, operation of reading and erase etc..
HPI 704 is electrically connected to memory management circuitry 702 and in order to receive and to identify master Instruction that machine system 11 is transmitted and data.It is to say, the instruction that transmitted of host computer system 11 and number According to being sent to memory management circuitry 702 by HPI 704.In this exemplary embodiment, HPI 704 is to be compatible to SATA standard.However, it is necessary to be appreciated that and the invention is not restricted to this, HPI 704 can also be to be compatible to PATA standard, IEEE 1394 standard, PCI Express mark Standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, EMMC standard, UFS standard, CF standard, IDE standard or other data transmission standards being suitable for.
Memory interface 706 is electrically connected to memory management circuitry 702 and can make carbon copies in order to access Formula non-volatile memory module 406.It is to say, be intended to write to type nonvolatile The data of module 406 can be converted to reproducible nonvolatile memorizer module via memory interface 706 406 receptible forms.Specifically, if memory management circuitry 702 duplicative to be accessed is non- Volatile 406, memory interface 706 can transmit the job sequence of correspondence.These instructions Sequence can include one or more signal, or the data in bus.Such as, in reading job sequence, The information such as the identification code of reading, storage address can be included.
Error checking and correcting circuit 708 are electrically connected to memory management circuitry 702 and in order to hold Row error checking and correction program are to guarantee the correctness of data.Specifically, memory management circuitry is worked as 702 when receiving write instruction from host computer system 11, and error checking can be corresponding with correcting circuit 708 The data of this write instruction produce corresponding error correcting code (error correcting code is called for short ECC) and/ Or error checking code (error detecting code is called for short EDC), and memory management circuitry 702 meeting The data of this write instruction corresponding are write to answering with corresponding error correcting code and/or error checking code Write in formula non-volatile memory module 406.Afterwards, when memory management circuitry 702 is from duplicative Can read, when non-volatile memory module 406 reads data, the error correcting code that these data are corresponding simultaneously And/or error checking code, and error checking can be according to this error correcting code and/or mistake with correcting circuit 708 The check code data to being read perform error checking and correction program by mistake.
In an exemplary embodiment, memorizer control circuit unit 404 also include buffer storage 710 with Electric power management circuit 712.Buffer storage 710 be electrically connected to memory management circuitry 702 and It is configured to temporarily store and comes from data and the instruction of host computer system 11 or come from duplicative non-volatile memories The data of device module 406.Electric power management circuit 712 is electrically connected to memory management circuitry 702 also And in order to control the power supply of memory storage apparatus 10.
Fig. 8 is according to the management duplicative non-volatile memories shown by one example of the present invention embodiment The schematic diagram of device module.It will be appreciated that be described herein reproducible nonvolatile memorizer module 406 The running of entity erased cell time, operate reality with the word such as " selection ", " packet ", " division ", " association " Body erased cell is concept in logic.It is to say, the reality of reproducible nonvolatile memorizer module The physical location of body erased cell is not changed, but in logic to type nonvolatile mould The entity erased cell of block operates.
The memory element of reproducible nonvolatile memorizer module 406 can constitute multiple entity program list Unit, and these a little entity program unit can constitute multiple entity erased cell.Specifically, same Memory element on word-line can form one or more entity program unit.If each memory element can Store the bit of more than 2, then the entity program unit on same word-line at least can be classified as Lower entity program unit and upper entity program unit.Such as, the minimum effective bit of a memory element (Least Significant Bit is called for short LSB) is belonging to lower entity program unit, and a memory element The highest significant bit (Most Significant Bit, be called for short MSB) be belonging to entity program unit. In general, in MLC NAND type flash memory, the writing speed of lower entity program unit The writing speed of upper entity program unit can be more than, or the reliability of lower entity program unit is above The reliability of upper entity program unit.In this exemplary embodiment, entity program unit is sequencing Minimum unit.That is, entity program unit is the minimum unit of write data.Such as, entity program Changing unit is physical page or entity fan (sector).If entity program unit is physical page, the most often One entity program unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises many Individual entity is fanned, and in order to store the data of user, and (such as, redundancy ratio special zone in order to store the data of system Error correcting code).In this exemplary embodiment, data bit district comprises 32 entity fans, and a reality The size of body fan is 512 bit groups (byte is called for short B).But, in other exemplary embodiment, data ratio Also can comprise 8,16 or number more or less of entity fan in special zone, the present invention is not limiting as reality The size of body fan and number.On the other hand, entity erased cell is the least unit erased.That is, Each entity erased cell contains the memory element being erased in the lump of minimal amount.Such as, entity is erased Unit is physical blocks.
Refer to Fig. 8, memory management circuitry 702 can be by reproducible nonvolatile memorizer module 406 Entity erased cell 800 (0)～800 (R) be logically divided into multiple region, for example, memory block 802 with System area 806.
The entity erased cell of memory block 802 is to store the data from host computer system 11.Memory block Valid data and invalid data can be stored in 802.Such as, a valid data are deleted when host computer system Time, deleted data may also be stored in memory block 802, but can be marked as invalid data. Do not store the most idle (spare) entity erased cell of entity erased cell of valid data.Such as, It is erased later entity erased cell and will become idle entity erased cell.If memory block 802 or be When having entity erased cell to damage in system district 806, the entity erased cell in memory block 802 can also be used Replace the entity erased cell of damage.If memory block 802 does not has can entity erased cell come When replacing the entity erased cell damaged, then whole memorizer may be deposited by memory management circuitry 702 Storage device 10 is declared as write protection (write protect) state, and cannot write data again.Additionally, have The entity erased cell of storage valid data is also referred to as non-idle (non-spare) entity erased cell.
The entity erased cell of system area 806 is to record system data, and wherein this system data includes Manufacturer and model, the entity erased cell number of memory chip, each entity about memory chip The entity program unit number etc. of erased cell.
Memory block 802 can be according to different memorizer rule from the quantity of the entity erased cell of system area 806 Lattice and different.Further, it is necessary to be appreciated that, in the running of memory storage apparatus 10, entity Erased cell closes and is coupled to the packet relation of memory block 802 and system area 806 and can dynamically change.Such as, When the entity erased cell in system area 806 damages and is replaced by the entity erased cell of memory block 802, Then the script entity erased cell in memory block 802 can be associated to system area 806.
Memory management circuitry 702 meeting configuration logic unit 810 (0)～810 (D) is to map to memory block 802 In entity erased cell 800 (0)～800 (A).Such as, in this exemplary embodiment, host computer system 11 It is to access the data in memory block 802, therefore, each logical block by logical address 810 (0)～810 (D) refer to a logical address.Additionally, in an exemplary embodiment, each logic list Unit 810 (0)～810 (D) may also mean that logic fan, logical order unit, a logic are smeared Form except unit or by multiple continuous print logical addresses.Each logical block 810 (0)～810 (D) is to reflect It is incident upon one or more solid element.In this exemplary embodiment, a solid element refers to that an entity is smeared Except unit.But, in another exemplary embodiment, solid element can also be a physical address, One entity fan, an entity program unit or be made up of multiple continuous print physical address, this Bright it is not any limitation as.Mapping between logical block and solid element can be closed by memory management circuitry 702 System is recorded in one or more logic-entity mapping.When host computer system 11 is intended to from memory storage apparatus 10 When reading data or write data to memory storage apparatus 10, memory management circuitry 702 can be according to this One or more logic-entity mapping performs the data access for memory storage apparatus 10.
Fig. 9 is that the critical voltage according to the multiple memory element shown by one example of the present invention embodiment divides The schematic diagram of cloth.
Refer to Fig. 9, the critical voltage of transverse axis representative memory cell, and longitudinal axis representative memory cell number. Such as, Fig. 9 is to represent the critical voltage of each memory element in a solid element.It is assumed herein that when certain The critical voltage of one memory element is to fall when being distributed 901, and what this memory element was stored is bit " 1 "； On the contrary, if the critical voltage of some memory element is to fall when being distributed 902, this memory element is deposited Storage is bit " 0 ".It is noted that in this exemplary embodiment, each memory element be in order to Store a bit, thus critical voltage be distributed two kinds may.But, in other exemplary embodiment, If a memory element is to store multiple bit, then the distribution of corresponding critical voltage then may have four Kind, eight kinds or other the most individual possibilities.Additionally, the present invention is also not intended to each ratio representated by distribution Special.
When to read data from reproducible nonvolatile memorizer module 406, memory management circuitry 702 can send a reading job sequence to reproducible nonvolatile memorizer module 406.This reads instruction Sequence includes one or more instruction or procedure code.This reads job sequence in order to indicate a certain entity list of reading Multiple memory element in unit are to obtain multiple bits.Such as, read job sequence according to this, can make carbon copies Formula non-volatile memory module 406 can use read voltage Vread-0Read these a little memory element and Send corresponding Bit data to memory management circuitry 702.Such as, if some memory element Critical voltage is less than read voltage Vread-0(such as, belong to the memory element of distribution 901), then memorizer pipe Reason circuit 702 can read bit " 1 "；If the critical voltage of some memory element is more than read voltage Vread-0(such as, belong to the memory element of distribution 902), then memory management circuitry 702 can read bit “0”。
But, along with the use time of reproducible nonvolatile memorizer module 406 increases and/or operation Environment changes, and distribution 901 and 902 can occur performance degradation (degradation).After there is performance degradation, Distribution 901 may be the most close to each other the most overlapped with 902.Such as, distribution 911 and distribution 912 are respectively intended to the distribution 901 and 902 after representing performance degradation.Distribution 911 comprises one with distribution 912 Individual overlapping region 913.Overlapping region 913 indicates that stored in some memory element should be bit " 1 ", but its critical voltage is more than read voltage Vread-0；Or, have and some memory element stored Should be bit " 0 ", but its critical voltage is less than read voltage Vread-0.After there is performance degradation, if holding Continuous use read voltage Vread-0Read and belong to distribution 911 or the memory element of distribution 912, then read To bit may comprise more mistake.Such as, it is mistaken for belonging to by the memory element belonging to distribution 911 In distribution 912, or it is mistaken for belonging to distribution 911 by the memory element belonging to distribution 912.Therefore, exist In this exemplary embodiment, the bit read can be decoded by error checking with correcting circuit 708, from And correct mistake therein.In following exemplary embodiment, it is accurate that read voltage is also referred to as read voltage Position (read voltage level).Each read voltage level has at least one magnitude of voltage.
In this exemplary embodiment, error checking and correcting circuit 708 can encode and be intended to store to duplicative The data of non-volatile memory module 406 also produce a coding unit.This coding unit is belonging to district Block code.Memory management circuitry 702 can send a write instruction sequence and deposit to duplicative is non-volatile Memory modules 406.This write instruction sequence comprises at least one instruction or procedure code.This write instruction sequence In order to indicate, in this coding unit write to reproducible nonvolatile memorizer module 406 is fitted When region (hereinafter also referred to first area).Such as, first area can be at least one solid element.Root Write instruction sequence accordingly, this coding unit can be deposited by reproducible nonvolatile memorizer module 406 Store up so far first area.Thereafter, when the data of first area are read in memory management circuitry 702 instruction, Reproducible nonvolatile memorizer module 406 can read this coding unit from first area, and wrong Flase drop is looked into and can be performed a decoding program to decode this coding unit with correcting circuit 708.
Figure 10 is the schematic diagram according to the coding unit shown by one example of the present invention embodiment.
Refer to Figure 10, coding unit 1010 includes bit b11～bnm.If by bit b11～bnmIt is grouped into Sub-coding unit 1011～101n, the most each sub-coding unit 1011～101n has m bit.n Any positive integer of 1 is all may be greater than with m.In this exemplary embodiment, the bit of part is by many Individual encoding procedure is determined.Such as, can be row (row) direction (such as, from left to right) by coding direction Encoding procedure is considered as first kind encoding procedure, and by volume that coding direction is column direction (such as, from top to bottom) Coded program is considered as Equations of The Second Kind encoding procedure.In an exemplary embodiment, first kind encoding procedure also referred to as row (row) encoding procedure, and Equations of The Second Kind encoding procedure also referred to as row (column) encoding procedure.
In this exemplary embodiment, first kind encoding procedure can first be performed, and encodes journey according to the first kind The coding result of sequence, Equations of The Second Kind encoding procedure can continue and be performed.For example, it is assumed that the user to be stored Packet b Han bit11～b1p、b21～b2p、…、br1～brp, then in first kind encoding procedure, bit b11～b1p、b21～b2p、…、br1～brpCan be encoded to respectively obtain bit b11～b1m(that is, sub-coding list First 1011), b21～b2m(that is, sub-coding unit 1012) ..., br1～brm(that is, sub-coding unit 101r). Bit b1q～b1mFor corresponding to bit b11～b1pError correcting code, bit b2q～b2mFor corresponding to bit b21～b2pError correcting code, by that analogy, wherein q be equal to p+1.Obtaining sub-coding unit After 1011～101r, Equations of The Second Kind encoding procedure can be performed.Such as, in Equations of The Second Kind encoding procedure, than Special b11～br1(that is, first bit in each sub-coding unit 1011～101r), bit b12～br2(i.e., Second bit in each sub-coding unit 1011～101r) ..., bit b1m～brm(that is, each M-th bit in individual sub-coding unit 1011～101r) can be encoded to respectively obtain bit b11～bn1、 b12～bn2、…、b1m～bnm.Bit bs1～bn1For corresponding to bit b11～br1Error correcting code, bit bs2～bn2For corresponding to bit b12～br2Error correcting code, by that analogy, wherein s be equal to r+1.
After being read out by coding unit 1010, correspond to used coded sequence, coding unit 1010 can be decoded.Such as, in this exemplary embodiment, decoding direction be the decoding program of column direction (also It is referred to as Equations of The Second Kind decoding program) can first be performed, and according to the decoded result of Equations of The Second Kind decoding program, decoding Direction is that can continue is performed for the decoding program (also referred to as first kind decoding program) of line direction.Such as, In two class decoding programs, bit bs1～bn1、bs2～bn2、…、bsm～bnmCan be respectively used to bit b11～br1、 b12～br2、…、b1m～brmIt is decoded.Obtaining decoded bit b11～br1、b12～br2、…、b1m～brm Afterwards, first kind decoding program can be performed.Such as, in first kind decoding program, by Equations of The Second Kind solution Coded program decoded bit b1q～b1m、b2q～b2m、…、brq～brmCan be used, respectively, to by Equations of The Second Kind Bit b after decoding process11～b1p、b21～b2p、…、br1～brpIt is decoded obtaining decoded User data.
It is noted that the composition of the coding unit mentioned in above-mentioned exemplary embodiment and coding/decoding are suitable Sequence is an example and is not used to limit the present invention.Such as, in another exemplary embodiment, produced Error correcting code can also be aligned in correspondence user data before or be interspersed in correspondence use In person's data.Or, in an exemplary embodiment, when encoding user data, it is also possible to be first to hold Row Equations of The Second Kind encoding procedure, then the coding result further in accordance with Equations of The Second Kind encoding procedure performs first kind coding Program；Corresponding, when decoding coding unit, it is also possible to be to first carry out first kind decoding program, so After perform Equations of The Second Kind decoding program further according to the decoded result of first kind decoding program.Additionally, the first kind Encoding procedure (or first kind decoding program) and the coding of Equations of The Second Kind encoding procedure (or Equations of The Second Kind decoding program) Direction is different, but first kind encoding procedure (or first kind decoding program) and Equations of The Second Kind encoding procedure (or the Two class decoding programs) identical or different coding/decoding algorithm can be used.Such as, first kind encoding procedure with Corresponding first kind decoding program can be to comprise low-density parity to check correcting code (low density parity Code, is called for short LDPC), (Reed-solomon code is called for short RS for BCH code and Reed Solomon code Code), the various coding/decoding algorithm such as square turbine code (block turbo code, be called for short BTC) is at least One of them；And Equations of The Second Kind encoding procedure and corresponding Equations of The Second Kind decoding program can also be comprise above-mentioned volume/ At least one or other kinds of coding/decoding algorithm of decoding algorithm.
In this exemplary embodiment, memory management circuitry 702 can send a reading job sequence (the most also It is referred to as the first reading job sequence) to reproducible nonvolatile memorizer module 406.This first reading refers to Sequence is made to read data from above-mentioned first area in order to indicate.Receive this first read job sequence it After, reproducible nonvolatile memorizer module 406 can be according to a read voltage level (hereinafter also referred to the One read voltage level) read multiple memory element in this first area with obtain a coding unit (with It is also referred to as down the first coding unit).This first coding unit belongs to block code.Introduction about coding unit It is specified in, therefore does not repeats at this.Then, error checking can be compiled first with correcting circuit 708 Code unit performs a decoding program (the hereinafter also referred to first decoding program) and records the decoded information of correspondence (the hereinafter also referred to first decoded information).
In this exemplary embodiment, the first decoding program is belonging to iterative decoding procedures.Such as, first In decoding program, error checking and correcting circuit 708 can perform iterative decoding computing at least one times, with The reliability information (such as, decoding initial value) updating the first coding unit iteratively improves the first volume Code unit be decoded into power.Iterative decoding computing each time can comprise same or similar in the model of Figure 10 The decoding operation that example embodiment is introduced.In general, according to (the also referred to as mistake ratio of mistake in coding unit Special) number, the first decoding program may success or failure.Such as, through iterative decoding at least one times After computing, if successfully decoded, such as, error checking and correcting circuit 708 judge the first coding unit In mistake be the most corrected, then error checking and correcting circuit 708 can export decoded (or after corrigendum ) the first coding unit.Otherwise, if because in the first coding unit the number of error bit too much and/or this The distribution of a little error bits, just at factors such as the positions that cannot be corrected, causes error checking and correction The number of times of the iterative decoding computing performed by circuit 708 has reached a preset times, then error checking with Correcting circuit 708 can judge to decode unsuccessfully.
It is noted that knowable to the exemplary embodiment of Figure 10, the first kind corresponding to certain a line decodes Program or the Equations of The Second Kind decoding program corresponding to certain string all may success or failures.Performed each time One class decoding program is the most independent, and the Equations of The Second Kind decoding program performed each time is also the most solely Stand.Such as, for the possible success or failure of first kind decoding program of sub-coding unit 1011, and Equations of The Second Kind decoding program for sub-coding unit 1012 is likely to success or failure, and both may be unrelated. Therefore, even if the first coding unit decodes unsuccessfully, but the most still there may be the row, column being successfully decoded Or bit.
The information that these can be successfully decoded by memory management circuitry 702 is recorded as the first decoding letter Breath.Such as, this first decoded information can include a numerical value (the hereinafter also referred to first numerical value).First number It is worth relevant with the decoded result of the first coding unit (the hereinafter also referred to first decoded result).Such as, the first number Value is to determine according to the first decoded result.Such as, the first numerical value is to be positively correlated with (positively Correlated) successfully decoded unit number (the hereinafter also referred to first successfully decoded unit of the first decoding program Number).In this exemplary embodiment, the first successfully decoded unit number refers to successfully be solved in the first coding unit The number of the unit of code.Such as, unit being successfully decoded may refer to one and is successfully decoded Row, the row being successfully decoded or a bit being successfully decoded.Memory management circuitry 702 Can directly using this first successfully decoded unit number as this first numerical value.Such as, memory management circuitry 702 Can be directly by number (the hereinafter also referred to the first row decoding of the row that is successfully decoded in the first coding unit Success unit number), number (the hereinafter also referred to first row decoding of row that is successfully decoded in the first coding unit Success unit number) or the first coding unit in the number of bit that is successfully decoded as this first number Value.Or, memory management circuitry 702 can also be according to the first row successfully decoded unit number and first row Successfully decoded unit number performs a logical operations to determine this first numerical value.Such as, memorizer management electricity The first row successfully decoded unit number can be multiplied by a weight (the hereinafter also referred to first weight) and obtain by road 702 To a parameter (the hereinafter also referred to first parameter) and first row successfully decoded unit number is multiplied by another Weight (the hereinafter also referred to second weight) obtains another parameter (the hereinafter also referred to second parameter)；Memorizer pipe First parameter can be added to determine this first numerical value by reason circuit 702 with the second parameter.Model with Figure 10 As a example by example embodiment, the first weight can be n/ (n+m), and the second weight can be m/ (n+m).So And, the first weight and the second weight can also distinctly set according to the demand in practice, and the present invention is not added with To limit.Additionally, in another exemplary embodiment, memory management circuitry 702 can also solve first Code success unit number input to a look-up table and using the output of this look-up table as the first numerical value.
After judging to decode unsuccessfully for the first coding unit, memory management circuitry 702 can indicate can Manifolding formula non-volatile memory module 406 adjusts read voltage.Such as, will be in order to read first area Read voltage be adjusted to another read voltage level (hereinafter also referred to second from the first read voltage level Read voltage level).Memory management circuitry 702 can send another and read job sequence (hereinafter also referred to the Second reading instruction fetch sequence) to reproducible nonvolatile memorizer module 406.Second reads job sequence uses Above-mentioned first area is read according to the second read voltage level with instruction.Receiving the second reading instruction After sequence, reproducible nonvolatile memorizer module 406 can be come according to the second read voltage level again Memory element in this first area of secondary reading is to obtain another coding unit (the hereinafter also referred to second coding Unit).Second coding unit is belonging to block code equally.Owing to being used for reading the read voltage level of data Change, therefore the bit of the second coding unit partial may be positioned at same position in the first coding unit Bit different.Such as, the bit b in the second coding unit11May be with the ratio in the first coding unit Special b11Different.
Error checking can perform another decoding program to the second coding unit with correcting circuit 708 and (be also referred to as below It is the second decoding program) and record corresponding decoded information (the hereinafter also referred to second decoded information).About How to perform the decoding program for coding unit to be specified in, therefore do not repeat at this.
Even if it is noted that the second coding unit decodes unsuccessfully, but the most still there may be successfully The row, column of decoding or bit.The information record that these can be successfully decoded by memory management circuitry 702 Under be used as the second decoded information.Such as, this second decoded information can include that a numerical value (is also referred to as below For second value).The decoded result (the hereinafter also referred to second decoded result) of second value and the second coding unit Relevant.Such as, second value is to determine according to the second decoded result.Such as, second value is positive Successfully decoded unit number (the hereinafter also referred to second successfully decoded unit number) about the second decoding program.At this In exemplary embodiment, the second successfully decoded unit number refers to the unit being successfully decoded in the second coding unit Number.Such as, memory management circuitry 702 can directly will be successfully decoded in the second coding unit The number (the hereinafter also referred to second row successfully decoded unit number) of row, the second coding unit is successfully decoded The number (hereinafter also referred to secondary series successfully decoded unit number) of row or the second coding unit in by success The number of the bit of decoding is as this second value.Or, memory management circuitry 702 can also basis Second row successfully decoded unit number and secondary series successfully decoded unit number perform a logical operations to determine this Second value.Additionally, the second successfully decoded unit number can also be inputted extremely by memory management circuitry 702 One look-up table and using the output of this look-up table as second value.About how determining that second value can be joined It is admitted to the explanation stated about the first numerical value, therefore does not repeats at this.
After obtaining the first decoded information and the second decoded information, memory management circuitry 702 can basis This first decoded information and this second decoded information estimate another read voltage level (hereinafter also referred to the Three read voltage levels).In this exemplary embodiment, third reading takes voltage quasi position and can be considered as The optimal read voltage level that one region is estimated out.Such as, this optimal read voltage level can To refer to that the historical record according to the past is assessed out, can be used to read out that to be decoded into power the highest The read voltage level of coding unit.Such as, memory management circuitry 702 can compare the first numerical value with Second value and determine that third reading takes voltage quasi position according to comparative result.Such as, if the first numerical value is big In second value, memory management circuitry 702 can determine third reading according to the first read voltage level Take voltage quasi position.Such as, in this exemplary embodiment, if the first numerical value is more than second value, memorizer First read voltage level directly can be set as that third reading takes voltage quasi position by management circuit 702.Or, In another exemplary embodiment, if the first numerical value is more than second value, memory management circuitry 702 also may be used Determine that third reading takes voltage quasi position to perform a logical operations according to the first read voltage level, this Bright it is not any limitation as.Additionally, if the first numerical value is less than second value, memory management circuitry 702 is permissible Determine that third reading takes voltage quasi position according to the second read voltage level.Such as, in this exemplary embodiment, If the first numerical value is less than second value, memory management circuitry 702 can be directly accurate by the second read voltage Position is set as that third reading takes voltage quasi position.Or, in another exemplary embodiment, if the first numerical value is less than Second value, memory management circuitry 702 can also perform a logic according to the second read voltage level Computing and determine that third reading takes voltage quasi position, the present invention is not any limitation as.
Although it is noted that above-mentioned exemplary embodiment is with twice continuous print read operation and decoding behaviour Make to be used as example to illustrate, but, in another exemplary embodiment, above-mentioned exemplary embodiment carries And twi-read operation with decode operation can also be discontinuous.More read operation and decoding behaviour The data that work can be used to for same region is stored process.Such as, at a model of Fig. 9 In example embodiment, multiple read voltage levels V that can be usedread-0～Vread-3One may be recorded in In individual look-up table.According to this look-up table, read voltage level Vread-0Can first be used to read above-mentioned The data in one region.Thereafter, if the coding unit for reading out decodes unsuccessfully, then search according to this Table, read voltage level Vread-1Can be by the data for reading above-mentioned first area that continue.Thereafter, If the coding unit for reading out still decodes failure, then read voltage level Vread-2Can be connect The decoding operation of the continuous data and correspondence being used for reading above-mentioned first area can be performed.Thereafter, if right Still failure, then read voltage level V is decoded in the coding unit read outread-3Can continue by with The decoding operation of the data and correspondence that read above-mentioned first area can be performed.Above-mentioned exemplary embodiment In the first read voltage level of mentioning can be read voltage level V shown in Fig. 9read-0～Vread-2 In any one, the second read voltage level mentioned in above-mentioned exemplary embodiment can be then first The arbitrary read voltage level bestowed after read voltage level.Such as, if the first read voltage level is Read voltage level Vread-0, then the second read voltage level can be read voltage level Vread-1～Vread-3 In any one, by that analogy.Additionally, read voltage level Vread-0～Vread-3The order used also may be used To be adjusted, the present invention is not any limitation as.Such as, in another exemplary embodiment, read voltage level Vread-0～Vread-3Can also be the most sequentially to be used according to magnitude of voltage.
In an exemplary embodiment, same in reproducible nonvolatile memorizer module 406 Region, if the coding that read voltage level described in table of noting all is previously used and is read out Unit all cannot be successfully decoded, and the most above-mentioned determines the 3rd according to multiple used read voltage levels The operation of read voltage level just can be performed.But, in another exemplary embodiment, it is also possible to set For, default more than one attempting the number of times using some read voltage level or change read voltage level Can perform after number of times above-mentioned according to multiple used read voltage levels determine third reading power taking pressure standard The operation of position, the present invention is not any limitation as.Although additionally, above-mentioned exemplary embodiment is all iterative decoding journey Sequence as the first decoding program and the example of the second decoding program, but, in another exemplary embodiment, First decoding program and/or the second decoding program can also be belonging to non-iterative decoding program, and the present invention is not added with To limit.
In an exemplary embodiment, read coding unit using some read voltage level and hold During the decoding program that row is corresponding, the bit value on position that part is successfully decoded can be considered It is correct and is recorded.Such as, if some row or column is decoded successfully, then this row or In row, the bit value of each position can be recorded.In upper decoding program once, it is recorded The bit value come may act as extra decoded information.Such as, in an exemplary embodiment, it is assumed that right Decoding in some coding unit is failed but bit b in decoded result presentation code unit11It is Correct, then bit b11Bit value can be recorded.Read same adjusting read voltage level In pen data and decoding next time that the data that read out are performed, in the coding unit read out Bit b11The bit value that can be directly corrected as previously being recorded.Or, in upper decoding program once, The bit value being recorded can be skipped, thus reduce in the coding unit obtained each time and need to be examined The number of bit.Thereby, in the mistake performing corresponding decoding program according to different read voltage levels Cheng Zhong, in coding unit, the bit of part can little by little be corrected, thus increase and be decoded into power.Additionally, The present invention is not limiting as the kind of the extra decoded information that can hand on, and any can pass to down The decoded information that decoding program once uses can be recorded and at upper decoding program once In be used.
After determining that third reading takes voltage quasi position, memory management circuitry 702 can be according to this third reading Take voltage quasi position to perform to preset behaviour with reproducible nonvolatile memorizer module 406 relevant at least Make.This predetermined registration operation can be used to optimize reproducible nonvolatile memorizer module 406 for data Storage, reading or the management for solid element.
In an exemplary embodiment, error checking and correcting circuit 708 can perform the decoding of hard bit mode Decode with soft bit mode.As a example by SLC type flash memory, in hard bit mode decodes, one Read voltage level can be imparted to a memory element.Whether react on this according to this memory element to read Voltage quasi position and be switched on, reproducible nonvolatile memorizer module 406 can return a bit (also referred to as For checking bit).Thereafter, error checking can be decoded according to this checking bit with correcting circuit 708. In hard bit mode decodes, the checking bit obtained is also referred to as hard bit.Same with SLC type quick flashing As a example by memorizer, in soft bit mode decodes, multiple read voltage levels can be imparted to a storage Unit.React on the conducting state of these a little read voltage levels according to this memory element, duplicative is non-easily The property lost memory module 406 can return multiple checking bit.Thereafter, error checking and correcting circuit 708 Can verify that according to this bit is decoded a bit.In soft bit mode decodes, the checking bit obtained Also referred to as soft bit.In the iterative decoding procedures that hard bit mode decodes, the decoding of a memory element Initial value is can be divided into two numerical value according to a checking bit corresponding to this memory element.Such as, If checking bit is " 1 ", then the decoding initial value of corresponding memory element can be set to "-n "；If checking ratio Spy is " 0 ", then the decoding initial value of corresponding memory element can be set to "-n ".Hard bit mode decoding Iterative decoding procedures is to perform based on these two kinds of numerical value.But, in the iterative solution that soft bit mode decodes In coded program, the decoding initial value of a memory element is then according to testing corresponding to the multiple of this memory element Card bit determines.
In an exemplary embodiment, the multiple read voltage levels in above-mentioned look-up table are all used up complete Before, error checking and the decoding performed by correcting circuit 708 are all belonging to the decoding of hard bit mode.If Multiple read voltage levels in above-mentioned look-up table all be used up finish and still cannot be to from same region The data read out are successfully decoded, then error checking and correcting circuit 708 may be switched to use soft Bit mode decodes.In soft bit mode decodes, memory management circuitry 702 can indicate according to the 3rd Read voltage level reads above-mentioned first area to obtain a decoding unit (the hereinafter also referred to the 3rd decoding Unit).Additionally, memory management circuitry 702 also can indicate and take voltage quasi position according to this third reading and determine Magnitude of voltage is positioned at this third reading and takes the multiple read voltage levels near the magnitude of voltage of voltage quasi position (the most also It is referred to as the 4th read voltage level) and read this first area according to these a little 4th read voltage levels, To obtain multiple soft bits.These a little 4th read voltage levels can comprise or not comprise third reading power taking pressure Level.Each soft bit can provide the extra decoded information of a bit in the 3rd decoding unit. Error checking and correcting circuit 708 can perform corresponding decoding program (also referred to as the to the 3rd decoding unit Three decoding programs).
Figure 11 is according to the schematic diagram reading multiple soft bits shown by one example of the present invention embodiment.
Refer to Figure 11, it is assumed that the 4th read voltage level determined includes read voltage level V1～V5, Then in soft bit mode decodes, read voltage level V1～V5Can be used to read in above-mentioned first area Belong to the memory element of distribution 1110 and 1120.React on read voltage level V1～V5, multiple soft ratios Special b1～b5Can be obtained.Such as, if the critical voltage of some memory element is positioned at voltage range 1101, The soft bit b then read1～b5Can be " 11111 "；If the critical voltage of some memory element is positioned at Voltage range 1102, then the soft bit b read1～b5Can be " 01111 "；If some memory element Critical voltage be positioned at voltage range 1103, then the soft bit b read1～b5Can be " 00111 "；If The critical voltage of some memory element is positioned at voltage range 1104, then the soft bit b read1～b5 Can be " 00011 "；If the critical voltage of some memory element is positioned at voltage range 1105, then read Soft bit b1～b5Can be " 00001 "；If the critical voltage of some memory element is positioned at voltage range 1106, the then soft bit b read1～b5Can be " 00000 ".In soft bit mode decodes, read The soft bit b got1～b5Can be used to the 3rd decoding unit is carried out the iterative decoding of correspondence.Such as, right Should be in each voltage range, memory element belongs to the probability of distribution 1110 and the machine belonging to distribution 1120 Rate can be computed in advance.Log likelihood ratio (Log can be calculated according to the two probability Likelihood Ratio, is called for short LLR).This log likelihood ratio can be used to determine to decode the absolute of initial value The size of value.Such as, the decoding initial value corresponding to each voltage range can be computed also in advance And be stored in a look-up table.The soft bit b obtained1～b5Can be transfused in this look-up table, and Corresponding decoding initial value can be obtained.Thereafter, error checking can be according to being obtained with correcting circuit 708 Decoding initial value perform follow-up decoding.
In other words, decoding relative to hard bit mode, soft bit mode decodes the decoded information (example used As, verify bit) more.Increase based on the decoded information used, being decoded into of soft bit mode decoding Power would generally be decoded into power higher than what hard bit mode decoded.Therefore, have can for the decoding of soft bit mode Decoding can be successfully completed in the case of hard bit mode decodes unsuccessfully.
In an exemplary embodiment, memory management circuitry 702 can take voltage quasi position according to third reading Determine extent of deterioration or the voltage's distribiuting of these a little memory element of multiple memory element in above-mentioned first area State.Such as, in the exemplary embodiment of Fig. 9, for belonging to the memory element of distribution 911 and 912 For, utilize read voltage level Vread-0Read these a little memory element and can read error rate relatively Low data；And after there is performance degradation, come for belonging to the memory element of distribution 911 and 912 Say, utilize read voltage level Vread-3Reading these a little memory element, then can to read error rate relatively low Data.Therefore, taking voltage quasi position according to the third reading determined, memory management circuitry 702 is permissible The current extent of deterioration of these a little memory element or this little memory element can also be obtained by the mode such as table look-up Current voltage's distribiuting state.Such as, read voltage level V in Fig. 9read-0～Vread-3Can be the most right Should be to an extent of deterioration or voltage's distribiuting state.It is noted that in an exemplary embodiment, institute State extent of deterioration relevant with the behaviour in service of memory element or current operation environment.Such as, if memory element Reading times, memory element write number of times, memory element erase number of times increase, then memory element Extent of deterioration may synchronize increase.Such as, if data are deposited time interval in the memory unit and increased Add, then the extent of deterioration of memory element may synchronize to increase.Such as, if current duplicative is non-volatile Temperature or the humidity of the operating environment of property memory module 406 are the highest, then the extent of deterioration of memory element is also May synchronize to increase.Additionally, described extent of deterioration is likely to meeting and the data stored in the memory unit Correctness/error rate relevant.Such as, the extent of deterioration of memory element is the highest, then be stored in memory element In the lowest or storage data in the memory unit the error rate of the correctness of data the highest.
In an exemplary embodiment, memory management circuitry 702 can take voltage quasi position according to third reading Determine the pre-set programs voltage corresponding to above-mentioned first area.Such as, if duplicative is non-volatile Memory module 406 be use an incremental step pulse erase (Incremental Step Pulse Program, It being called for short ISPP) model carrys out sequencing memory element, then and memory management circuitry 702 can take according to third reading Voltage quasi position indicates reproducible nonvolatile memorizer module 406 to adjust this incremental step pulse model In an initial program voltage.This initial program voltage be in this incremental step pulse model at first by The programming voltage of the memory element bestowed to above-mentioned first area.Additionally, any with adjust that this is initial Programming voltage about and/or the sequencing parameter of similar effect can be reached or parameter of erasing can also be by Adjust.
It is noted that the present invention is not by can be according to presetting that third reading takes that voltage quasi position performs Operation is defined in above-mentioned.Such as, in another exemplary embodiment, any can be according to the property of memory element Can decline, extent of deterioration or voltage's distribiuting state and the corresponding parameter adjusted or memorizer set can React on third reading to take voltage quasi position and be suitably adapted, thus improve non-volatile for duplicative The operating capability of memory module 406.Such as, in an exemplary embodiment, according to third reading power taking pressure Level, the solid element belonging to above-mentioned first area can also be marked as damage etc..Additionally, one In exemplary embodiment, take voltage quasi position, reproducible nonvolatile memorizer module 406 according to third reading Any management being conducive to reproducible nonvolatile memorizer module 406 such as service life information also Can be obtained.
It should be noted that, although above-mentioned exemplary embodiment is all to store a bit with a memory element to make Illustrate for example, but, in another exemplary embodiment, the operation of above-mentioned reading coding unit, The operation of above-mentioned decoding coding unit and the operation of estimation read voltage level are readily adaptable for use in one and deposit Storage unit can store the use situation of multiple bit.Such as, the read voltage level estimated also may be used Can be the data stored in order to read operation memory element under MLC pattern or TLC pattern.
Figure 12 is according to the read voltage level estimating and measuring method shown by one example of the present invention embodiment Flow chart.
Refer to Figure 12, in step S1201, according to the first read voltage level, described duplicative First area in non-volatile memory module can be read to obtain the first coding unit, wherein said First coding unit belongs to block code.In step S1202, for the first of described first coding unit Decoding program can be performed and the first decoded information can be recorded.In step S1203, according to second Read voltage level, described first area can be read to obtain the second coding unit, and wherein said second Coding unit belongs to described block code.In step S1204, for the second of described second coding unit Decoding program can be performed and the second decoded information can be recorded.In step S1205, according to described First decoded information and described second decoded information, third reading takes voltage quasi position and can be estimated and obtained. In step S1206, take voltage quasi position according to described third reading, non-volatile with described duplicative deposit Relevant at least one predetermined registration operation of memory modules can be performed.
But, in Figure 12, each step has described in detail as above, just repeats no more at this.It should be noted that In Figure 12, each step can be implemented as multiple procedure code or circuit, and the present invention is not any limitation as.Additionally, The method of Figure 12 example above embodiment of can arranging in pairs or groups uses, it is also possible to being used alone, the present invention is the most in addition Limit.
In sum, utilizing different read voltage levels to read memorizer and to attempt being obtained Decoding data after, the decoded information corresponding to different coding unit can be recorded.Thereafter, These a little decoded informations i.e. can be used as estimating the foundation of a suitable read voltage level, and at least One predetermined registration operation can be performed accordingly.Thereby, the duplicative for using block code is non-volatile The operating capability of property memory module can be elevated.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it, Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.

Claims (36)

1. a read voltage level estimating and measuring method, it is characterised in that deposit for duplicative is non-volatile Memory modules, described read voltage level estimating and measuring method includes:
In described reproducible nonvolatile memorizer module is read according to the first read voltage level One region, to obtain the first coding unit, wherein said first coding unit belongs to block code；
Described first coding unit is performed the first decoding program and records the first decoded information；
Described first area is read according to the second read voltage level, to obtain the second coding unit, its Described in the second coding unit belong to described block code；
Described second coding unit is performed the second decoding program and records the second decoded information；And
Estimate according to described first decoded information and described second decoded information and obtain third reading power taking pressure Level.
Read voltage level estimating and measuring method the most according to claim 1, it is characterised in that described district Block code is made up of many sub-coding units, and the first bit in this little coding unit is by multiple coding journeys Sequence determines.
Read voltage level estimating and measuring method the most according to claim 2, it is characterised in that those are compiled Coded program has different coding directions.
Read voltage level estimating and measuring method the most according to claim 1, it is characterised in that described One decoded information includes that the first numerical value, described second decoded information include second value,
Wherein estimate according to described first decoded information and described second decoded information and obtain the described 3rd The step of read voltage level includes:
With described second value and according to comparative result, described first numerical value of comparison determines that described third reading takes Voltage quasi position.
Read voltage level estimating and measuring method the most according to claim 4, it is characterised in that described One numerical value is relevant with the first decoded result of described first decoding program, described second value and described second Second decoded result of decoding program is relevant.
Read voltage level estimating and measuring method the most according to claim 5, it is characterised in that described One numerical value is the first successfully decoded unit number being positively correlated with described first decoding program, described second value It it is the second successfully decoded unit number being positively correlated with described second decoding program.
Read voltage level estimating and measuring method the most according to claim 6, it is characterised in that also include:
The first row successfully decoded unit number and first row successfully decoded list is obtained according to described first decoded result Unit's number；
Institute is determined according to described the first row successfully decoded unit number and described first row successfully decoded unit number State the first numerical value；
The second row successfully decoded unit number and secondary series successfully decoded list is obtained according to described second decoded result Unit's number；And
Institute is determined according to described second row successfully decoded unit number and described secondary series successfully decoded unit number State second value.
Read voltage level estimating and measuring method the most according to claim 1, it is characterised in that according to institute State the first decoded information and described second decoded information to estimate and obtain described third reading and take voltage quasi position Step includes:
One of them of described first read voltage level and described second read voltage level is determined as institute State third reading and take voltage quasi position.
Read voltage level estimating and measuring method the most according to claim 1, it is characterised in that also include:
Judge that described first decoding program is the most failed,
The step wherein reading described first area according to described second read voltage level is to judge institute Perform after stating the first decoding program failure.
Read voltage level estimating and measuring method the most according to claim 1, it is characterised in that also wrap Include:
Take voltage quasi position according to described third reading to perform and described reproducible nonvolatile memorizer module Relevant predetermined registration operation,
Wherein said predetermined registration operation includes at least one of following operation:
Read described first area to obtain corresponding to the multiple soft bit of the 3rd decoding unit and according to those Soft bit described 3rd decoding unit is performed iterative decoding；
Determine extent of deterioration or the voltage of those memory element of multiple memory element in described first area Distribution；And
Determine the pre-set programs voltage corresponding to described first area.
11. read voltage level estimating and measuring methods according to claim 1, it is characterised in that also wrap Include:
Take voltage quasi position according to described third reading and read described first area, to obtain the 3rd coding unit； And
Described 3rd coding unit is performed the 3rd decoding program.
12. read voltage level estimating and measuring methods according to claim 1, it is characterised in that described First decoding program and described second decoding program are all the decoding of hard bit mode.
13. 1 kinds of memory storage apparatus, it is characterised in that including:
Connect interface unit, be electrically connected to host computer system；
Reproducible nonvolatile memorizer module；And
Memorizer control circuit unit, is electrically connected to described connection interface unit non-with described duplicative Volatile,
Wherein said memorizer control circuit unit in order to send the first reading job sequence, wherein said One reads job sequence, and in order to indicate, to read described duplicative according to the first read voltage level non-volatile First area in property memory module, to obtain the first coding unit, wherein said first coding unit Belong to block code,
Wherein said memorizer control circuit unit is also in order to perform the first decoding to described first coding unit Program and record the first decoded information,
Wherein said memorizer control circuit unit is also in order to send the second reading job sequence, wherein said Second reads job sequence reads described first area in order to indicate according to the second read voltage level, with Obtaining the second coding unit, wherein said second coding unit belongs to described block code,
Wherein said memorizer control circuit unit is also in order to perform the second decoding to described second coding unit Program and record the second decoded information,
Wherein said memorizer control circuit unit is also in order to according to described first decoded information and described second Decoded information is estimated and is obtained third reading and takes voltage quasi position.
14. memory storage apparatus according to claim 13, it is characterised in that described block code Being made up of many sub-coding units, the first bit in this little coding unit is by multiple encoding procedures certainly Fixed.
15. memory storage apparatus according to claim 14, it is characterised in that those encode journey Sequence has different coding directions.
16. memory storage apparatus according to claim 13, it is characterised in that described first solves Code information includes that the first numerical value, described second decoded information include second value,
Wherein said memorizer control circuit unit is according to described first decoded information and described second decoding letter Breath is estimated and is obtained described third reading and takes the operation of voltage quasi position and include:
With described second value and according to comparative result, described first numerical value of comparison determines that described third reading takes Voltage quasi position.
17. memory storage apparatus according to claim 16, it is characterised in that described first number It is worth relevant with the first decoded result of described first decoding program, described second value and described second decoding Second decoded result of program is relevant.
18. memory storage apparatus according to claim 17, it is characterised in that described first number Value is the first successfully decoded unit number being positively correlated with described first decoding program, and described second value is just It is relevant to the second successfully decoded unit number of described second decoding program.
19. memory storage apparatus according to claim 18, it is characterised in that described memorizer Control circuit unit is also in order to obtain the first row successfully decoded unit number and the according to described first decoded result String successfully decoded unit number,
Wherein said memorizer control circuit unit also in order to according to described the first row successfully decoded unit number with Described first row successfully decoded unit number determines described first numerical value,
Wherein said memorizer control circuit unit is also in order to obtain the second row according to described second decoded result Successfully decoded unit number and secondary series successfully decoded unit number,
Wherein said memorizer control circuit unit also in order to according to described second row successfully decoded unit number with Described secondary series successfully decoded unit number determines described second value.
20. memory storage apparatus according to claim 13, it is characterised in that described memorizer Control circuit unit is estimated according to described first decoded information and described second decoded information and obtains described Third reading takes the operation of voltage quasi position and includes:
One of them of described first read voltage level and described second read voltage level is determined as institute State third reading and take voltage quasi position.
21. memory storage apparatus according to claim 13, it is characterised in that described memorizer Control circuit unit also in order to judge the whether failure of described first decoding program,
It is to sentence that wherein said memorizer control circuit unit sends the described second operation reading job sequence Perform after fixed described first decoding program failure.
22. memory storage apparatus according to claim 13, it is characterised in that described memorizer Control circuit unit also in order to according to described third reading take voltage quasi position perform non-with described duplicative easily The predetermined registration operation that the property lost memory module is relevant,
Wherein said predetermined registration operation includes at least one of following operation:
Instruction reads described first area to obtain the multiple soft bit corresponding to the 3rd decoding unit basis Those soft bits described 3rd decoding unit is performed iterative decoding；
Determine extent of deterioration or the voltage of those memory element of multiple memory element in described first area Distribution；And
Determine the pre-set programs voltage corresponding to described first area.
23. memory storage apparatus according to claim 13, it is characterised in that described memorizer Control circuit unit also takes voltage quasi position according to described third reading and reads described first area in order to indicating, To obtain the 3rd coding unit,
Wherein said memorizer control circuit unit is also in order to perform the 3rd decoding to described 3rd coding unit Program.
24. memory storage apparatus according to claim 13, it is characterised in that described first solves Coded program and described second decoding program are all the decoding of hard bit mode.
25. 1 kinds of memorizer control circuit unit, it is characterised in that be used for controlling duplicative non-volatile Property memory module, described memorizer control circuit unit includes:
HPI, is electrically connected to host computer system；
Memory interface, is electrically connected to described reproducible nonvolatile memorizer module；
Error checking and correcting circuit；And
Memory management circuitry, is electrically connected to described HPI, described memory interface and described mistake Flase drop is looked into and correcting circuit,
Wherein said memory management circuitry is in order to send the first reading job sequence, and wherein said first reads In order to indicate, instruction fetch sequence reads according to the first read voltage level that described duplicative is non-volatile to be deposited First area in memory modules, to obtain the first coding unit, wherein said first coding unit belongs to Block code,
Wherein said error checking and correcting circuit in order to perform the first decoding journey to described first coding unit Sequence, and described memory management circuitry is also in order to record the first decoded information,
Wherein said memory management circuitry also in order to send the second reading job sequence, wherein said second Read job sequence and read described first area in order to indicate according to the second read voltage level, to obtain Second coding unit, wherein said second coding unit belongs to described block code,
Wherein said error checking and correcting circuit are also in order to perform the second decoding to described second coding unit Program, and described memory management circuitry is also in order to record the second decoded information,
Wherein said memory management circuitry is also in order to according to described first decoded information and described second decoding Information is estimated and is obtained third reading and takes voltage quasi position.
26. memorizer control circuit unit according to claim 25, it is characterised in that described district Block code is made up of many sub-coding units, and the first bit in this little coding unit is by multiple coding journeys Sequence determines.
27. memorizer control circuit unit according to claim 26, it is characterised in that those are compiled Coded program has different coding directions.
28. memorizer control circuit unit according to claim 25, it is characterised in that described One decoded information includes that the first numerical value, described second decoded information include second value,
Wherein said memory management circuitry is come with described second decoded information according to described first decoded information Estimate and obtain described third reading and take the operation of voltage quasi position and include:
With described second value and according to comparative result, described first numerical value of comparison determines that described third reading takes Voltage quasi position.
29. memorizer control circuit unit according to claim 28, it is characterised in that described One numerical value is relevant with the first decoded result of described first decoding program, described second value and described second Second decoded result of decoding program is relevant.
30. memorizer control circuit unit according to claim 29, it is characterised in that described One numerical value is the first successfully decoded unit number being positively correlated with described first decoding program, described second value It it is the second successfully decoded unit number being positively correlated with described second decoding program.
31. memorizer control circuit unit according to claim 30, it is characterised in that described in deposit Reservoir management circuit is also in order to obtain the first row successfully decoded unit number and the according to described first decoded result String successfully decoded unit number,
Wherein said memory management circuitry also in order to according to described the first row successfully decoded unit number with described First row successfully decoded unit number determines described first numerical value,
Wherein said memory management circuitry is also in order to obtain the second row decoding according to described second decoded result Success unit number and secondary series successfully decoded unit number,
Wherein said memory management circuitry also in order to according to described second row successfully decoded unit number with described Secondary series successfully decoded unit number determines described second value.
32. memorizer control circuit unit according to claim 25, it is characterised in that described in deposit Reservoir management circuit is estimated according to described first decoded information and described second decoded information and obtains described Third reading takes the operation of voltage quasi position and includes:
One of them of described first read voltage level and described second read voltage level is determined as institute State third reading and take voltage quasi position.
33. memorizer control circuit unit according to claim 25, it is characterised in that described in deposit Reservoir manages circuit also in order to judge that described first decoding program is the most failed,
It is to judge institute that wherein said memory management circuitry sends the described second operation reading job sequence Perform after stating the first decoding program failure.
34. memorizer control circuit unit according to claim 25, it is characterised in that described in deposit Reservoir management circuit also in order to according to described third reading take voltage quasi position perform non-with described duplicative easily The predetermined registration operation that the property lost memory module is relevant,
Wherein said predetermined registration operation includes at least one of following operation:
Instruction reads described first area to obtain the multiple soft bit corresponding to the 3rd decoding unit and institute State error checking with correcting circuit also in order to described 3rd decoding unit is performed repeatedly according to those soft bits Generation decoding；
Determine extent of deterioration or the voltage of those memory element of multiple memory element in described first area Distribution；And
Determine the pre-set programs voltage corresponding to described first area.
35. memorizer control circuit unit according to claim 25, it is characterised in that described in deposit Reservoir management circuit also takes voltage quasi position according to described third reading and reads described first area in order to indicating, To obtain the 3rd coding unit,
Wherein said error checking and correcting circuit are also in order to perform the 3rd decoding to described 3rd coding unit Program.
36. memorizer control circuit unit according to claim 25, it is characterised in that described One decoding program and described second decoding program are all the decoding of hard bit mode.
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