CN110364207A

CN110364207A - Coding/decoding method and store controller

Info

Publication number: CN110364207A
Application number: CN201810319972.5A
Authority: CN
Inventors: 萧又华
Original assignee: Shenzhen Da Xin Electronic Technology Co Ltd
Current assignee: Shenzhen Da Xin Electronic Technology Co Ltd
Priority date: 2018-04-11
Filing date: 2018-04-11
Publication date: 2019-10-22
Anticipated expiration: 2038-04-11
Also published as: CN110364207B

Abstract

The present invention provides a kind of coding/decoding method and store controller for being suitable for reproducible nonvolatile memorizer module.The method includes selecting the target word-line in the multiple word-line, wherein preset data has been programmed into multiple target memory born of the same parents of the target word-line；Multiple predetermined bit values are identified according to the preset data；It is utilized respectively X different reading voltage groups and reads the multiple target memory born of the same parents, to obtain X reading bit value group for respectively corresponding the X reading voltage group, and X shift numbers summation group is obtained via the X reading bit value group and the multiple predetermined bit value；And determine that an optimization reads the N-1 optimization reading voltage of voltage group according to the X shift numbers summation group.

Description

Coding/decoding method and store controller

Technical field

The present invention relates to a kind of coding/decoding methods, more particularly to one kind to be suitable for being configured with type nonvolatile The coding/decoding method and store controller of the storage device of module.

Background technique

In general, when reading data to reproducible nonvolatile memorizer module, if the page reads the feelings of failure There is no system will use default reading voltage group or best reading voltage group used before to read data to condition.Until The case where reading fails, system (stocking system) just can read voltage group or used optimum voltage without using default, And accordingly voltage group is read in adjustment.

In other words, the best reading voltage class value of reproducible nonvolatile memorizer module can't be fixed. However, it is to expend resource that traditionally adjustment, which reads voltage group to obtain the best practice for reading voltage group to read data,.It lifts Example for, the first traditional optimized process of reading voltage can adjust always corresponding different critical voltage's distribiuting it is multiple not With read voltage size (adjustment one read voltage group in one threshold distribution of correspondence have a common boundary a reading voltage, and And fix remaining in the reading voltage group and read voltage) data to fail are read to read the above-mentioned generation page, to attempt to obtain Obtain best reading data result and using the reading voltage group of the best reading data result of correspondence as corresponding to store The optimization for stating the physical unit of data reads voltage group.With TLC type fast storage (memory cell stores 3 bit values) For, seven reading voltages are shared in a reading voltage group corresponding to different voltages section.Using conventional method, six need to be fixed A reading voltage, and change a reading voltage.If each reading voltage need to adjust X times (and via read obtain as a result, with Compare all results to find out the best), then it is (2 to obtain reading times used in best reading voltage³- 1) × X= 7 × X times.In addition, above-mentioned traditional practice also needs the data for preparing to have verified that.In other words, the first conventional practice can need It is (pre- to store with storage space to expend a large amount of computing resource (data after voltage and the corresponding reading of verifying are read in adjustment) If the space of data), thereby reduce the efficiency of decoding operate.

In addition, second of conventional practice is to be utilized respectively the multiple tune being preset in memory module hardware specification Whole reading voltage group is come to the reading data are attempted, to look for optimal reading data result.Wherein, electricity is read in each adjustment Multiple reading voltages in pressure group can not be set by the controller by storage device, and the number of voltage group is read in the adjustment Amount is also limited.In other words, using second of conventional practice, it perhaps can find one group of adjustment therein and read voltage group to allow Reading the read data of voltage group by this can be correct (successfully decoded).But the adjustment found is read Voltage group can not find the best reading voltage group for meeting current critical voltage distribution such as the first conventional practice.This Outside, since the quantity and precision of adjustment reading voltage group are lower, also will appear all adjustment reading voltage groups cannot all make The read correct situation of reading data.

That is, although adjustment voltage group that second of conventional practice can use small number to make compared with the first tradition Method can make data streams read correctly read voltage group more quickly to find, but the failure probability of the method also can be compared to The first conventional practice is big, and the number of error bits of read data also can be higher, and then increases the negative of decoding operate Load.

Therefore, how in the case where not needing to prepare verify data, quickly and effectively reading voltage is carried out most Goodization to improve the defect of conventional practice, and then promotes the reading and corresponding solution of reproducible nonvolatile memorizer module Code efficiency is one of the project of those skilled in the art's research.

Summary of the invention

The present invention provides a kind of coding/decoding method and store controller, can utilize the present count stored by target word-line According to, it quickly and effectively obtains and accurately corresponds to the optimization of the target word-line and read voltage group, and then it can be via most Goodization read voltage group multiple optimizations read voltage come properly read from the target word-line data and effectively Rate it is decoded operation.

One embodiment of the invention, which provides, is suitable for the storage device configured with reproducible nonvolatile memorizer module A kind of coding/decoding method, wherein the reproducible nonvolatile memorizer module have multiple word-lines, wherein the multiple Each word-line of word-line includes multiple memory cells, wherein each of the multiple memory cell memory cell is to by journey Sequence corresponds to the bit value of one of different multiple Ge Lei codes (Grey Code), and the multiple Ge Lei to store The sum of code is N, and N is the first predetermined positive greater than 2.The described method includes: selecting the target in the multiple word-line Word-line, wherein preset data has been programmed into multiple target memory born of the same parents of the target word-line；According to described default Data identify multiple predetermined bit values stored by the multiple target memory born of the same parents；It is utilized respectively X different reading voltage Group reads the multiple target memory born of the same parents, to obtain X reading bit value group for respectively corresponding the X reading voltage group, and And X shift numbers summation group is obtained via the X reading bit value group and the multiple predetermined bit value, wherein X is one second predetermined positive, and the X reading voltage group is arranged with one first predetermined order, and the X reading voltage The voltage difference that adjacent two are read between voltage group in group is one first predetermined voltage difference, wherein each described X reading Take voltage group that there is the N-1 reading voltage according to the arrangement of one second predetermined order, and each described X shift numbers is total There is the N-1 shift numbers summation arranged according to second predetermined order with group, wherein in the X reading bit value group The bit value group that reads for i-th correspond to i-th of reading voltage group in the X reading voltage group, the X shift numbers are total Described X i-th of the reading voltage group read in voltage group is corresponded to i-th of shift numbers summation group in group, and described J-th of shift numbers summation in i-th of shift numbers summation group corresponds to described i-th j-th of the reading read in voltage group Voltage；And determine that an optimization reads the N-1 optimization reading electricity of voltage group according to the X shift numbers summation group Pressure.

One embodiment of the invention is provided to be filled for controlling the storage configured with reproducible nonvolatile memorizer module A kind of store controller set.The store controller includes: connecting interface circuit, memory interface control circuit, reads electricity Pressure pipe manages circuit unit and processor.Connecting interface circuit is electrically connected to host system.Memory interface control electricity Road is electrically connected to the reproducible nonvolatile memorizer module, wherein the type nonvolatile Module has multiple word-lines, wherein each word-line of the multiple word-line includes multiple memory cells, wherein described more Each of a memory cell memory cell stores its of corresponding different multiple Ge Lei codes (Grey Code) to be programmed One of bit value, and the sum of the multiple Ge Lei code is N, and N is the first predetermined positive greater than 2.The processing Device selects the target word-line in the multiple word-line, and indicates that the reading voltage management circuitry unit is corresponded to institute The reading voltage for stating target word-line optimizes operation, wherein a preset data has been programmed into the more of the target word-line In a target memory born of the same parents, wherein optimizing in operation in the reading voltage, the reading voltage management circuitry unit is to root Multiple predetermined bit values stored by the multiple target memory born of the same parents are identified according to the preset data；The reading voltage management Circuit unit also reads the multiple target memory born of the same parents to be utilized respectively X different reading voltage groups, right respectively to obtain Answer it is described X reading voltage group X reading bit value group, and via the X reading bit value group with it is described more A predetermined bit value obtains X shift numbers summation group, and wherein X is one second predetermined positive, the X reading voltage group It is arranged with one first predetermined order, and the described X voltage differences read between two reading voltage groups adjacent in voltage group Value is one first predetermined voltage difference, and wherein each described X is read voltage group with according to the arrangement of one second predetermined order N-1 reading voltage, and each described X shift numbers summation group has the N- arranged according to second predetermined order 1 shift numbers summation, wherein described X i-th of the reading bit value group read in bit value group corresponds to the X reading electricity I-th of reading voltage group in pressure group, i-th of shift numbers summation group in the X shift numbers summation group correspond to the X A i-th of reading voltage group read in voltage group, and j-th of shift numbers in i-th of shift numbers summation group Summation corresponds to N-1 j-th of the reading voltage read in voltage of i-th of reading voltage group；And the reading voltage Management circuit unit is also to determine that an optimization reads N-1 of voltage group most according to the X shift numbers summation group Goodization reads voltage.

Based on above-mentioned, coding/decoding method and store controller provided by the embodiment of the present invention, using target word-line Stored preset data states the reading voltage optimization operation that target word-line executes the corresponding target word-line to Suo. It is optimized in operation in the reading voltage, store controller is according to the preset data and via the multiple and different reading of utilization Voltage group reads target word-line multiple reading bit groups obtained, to calculate multiple shift numbers summation groups, with Determine that the optimization of the corresponding target word-line reads the multiple best of voltage group according to the multiple shift numbers summation group Change and reads voltage.In this way, which the optimal reading to read the target word-line can be looked for efficiently and quickly Voltage group, and then enhance the therefrom correctness of data streams read and enhance the efficiency of the decoding operate entirety for reading.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows

Detailed description of the invention

Fig. 1 is the block schematic diagram of host system shown by an embodiment according to the present invention and storage device.

Fig. 2 is the flow chart of coding/decoding method shown by an embodiment according to the present invention.

Fig. 3 is two different the reading voltage groups and voltage difference therein according to shown by one embodiment of the invention Schematic diagram.

Fig. 4 is the schematic diagram that shift numbers summation is calculated shown by an embodiment according to the present invention.

Fig. 5 is the signal according to shown by one embodiment of the invention to the statistical form of record-shifted number summation Figure.

[symbol description]

10: host system

20: storage device

110,211: processor

120: mainframe memory

130: data transmission interface circuit

210: store controller

212: data management circuit

213: memory interface control circuit

214: error checking and correcting circuit

215: reading voltage management circuitry unit

2151: shift numbers counting circuit

2152: reading voltage optimization circuits

216: buffer storage

217: electric power management circuit

220: reproducible nonvolatile memorizer module

230: connecting interface circuit

S21, S23, S25, S27: the process step of coding/decoding method

V_offset: predetermined voltage difference

V (1), V (2), V (X): voltage group is read

V(1)₁~V (1)₇、V(2)₁~V (2)₇、V(i)₁~V (i)₇: read voltage

C(1)_G1G2、C(1)_G2G3、C(1)_G3G4、C(1)_G4G5、C(1)_G5G6、C(1)_G6G7、C(1)_G7G8、C(1)_G2G1、C(1)_G3G2、 C(1)_G4G3、C(1)_G5G4、C(1)_G6G5、C(1)_G7G6、C(1)_G8G7: shift numbers

S(1)₁~S (1)₇、S(2)₁~S2)₇、S(X)₁~S (X)₇: shift numbers summation

S (1)~S (X): shift numbers summation group

510: statistical form

G1~G8: target memory born of the same parents group/storing state/Ge Lei code

L: the bit value of lower physical page

M: the bit value of middle physical page

U: the bit value of upper physical page

Specific embodiment

In the present embodiment, storage device includes reproducible nonvolatile memorizer module (rewritable non- Volatile memory module) and storage controller (also referred to as, store controller or storage control circuit).In addition, Storage device is used together with host system, so that host system can write data into storage device or from storage device Read data.

Fig. 1 is please referred to, host system (Host System) 10 includes processor (Processor) 110, mainframe memory (Host Memory) 120 and data transmission interface circuit (Data Transfer Interface Circuit) 130.In this reality It applies in example, data transmission interface circuit 130 is electrically connected and (also referred to as, is electrically connected) to processor 110 and mainframe memory 120. In another embodiment, system bus is utilized between processor 110, mainframe memory 120 and data transmission interface circuit 130 (System Bus) is electrically connected to each other.

Storage device 20 includes store controller (Storage Controller) 210, duplicative non-volatile memories Device module (Rewritable Non-Volatile Memory Module) 220 and connecting interface circuit (Connection Interface Circuit)230.Wherein, store controller 210 includes processor 211, data management circuit (Data Transfer Management Circuit) 212 and memory interface control circuit (Memory Interface Control Circuit)213。

In the present embodiment, host system 10 is connect by data transmission interface circuit 130 and the connection of storage device 20 Mouth circuit 230 is electrically connected to storage device 20 to carry out the accessing operation of data.For example, host system 10 can be passed via data Data storage is read data to storage device 20 or from storage device 20 by defeated interface circuit 130.

In the present embodiment, processor 110, mainframe memory 120 and data transmission interface circuit 130 may be provided at host On the motherboard of system 10.The number of data transmission interface circuit 130 can be one or more.Pass through data transmission interface circuit 130, motherboard can be electrically connected to storage device 20 via wired or wireless way.Storage device 20 can be for example USB flash disk, deposit Card storage, solid state hard disk (Solid State Drive, SSD) or radio memory storage device.Radio memory storage device can E.g. close range wireless communication (Near Field Communication, NFC) memory storage apparatus, radio facsimile (WiFi) memory storage apparatus, bluetooth (Bluetooth) memory storage apparatus or low-power consumption bluetooth memory storage apparatus The memory storage apparatus based on various wireless communication technique such as (for example, iBeacon).In addition, motherboard can also lead to It crosses system bus and is electrically connected to global positioning system (Global Positioning System, GPS) module, network interface The various I/O device such as card, radio transmitting device, keyboard, screen, loudspeaker.

In the present embodiment, data transmission interface circuit 130 and connecting interface circuit 230 are to be compatible to high-speed peripheral part The interface electricity of connecting interface (Peripheral Component Interconnect Express, PCI Express) standard Road.It also, is to utilize flash non-volatile memory interface between data transmission interface circuit 130 and connecting interface circuit 230 Standard (Non-Volatile Memory express, NVMe) communications protocol carries out the transmission of data.

However, it is necessary to be appreciated that, the invention is not limited thereto, data transmission interface circuit 130 and connecting interface circuit 230 It is also possible to meet parallel advanced attachment (Parallel Advanced Technology Attachment, PATA) standard, electricity Gas and Electronic Engineering Association (Institute of Electrical and Electronic Engineers, IEEE) 1394 Standard, serial advanced attachment (Serial Advanced Technology Attachment, SATA) standard, general serial are total Line (Universal Serial Bus, USB) standard, SD interface standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, eMMC interface standard, general fast storage (Universal Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.In addition, in another embodiment, connecting interface circuit 230 can be with Store controller 210 is encapsulated in a chip or connecting interface circuit 230 is to be laid in one to include store controller 210 Chip outside.

In the present embodiment, mainframe memory 120 is configured to temporarily store instruction performed by processor 110 or data.For example, In this exemplary embodiment, mainframe memory 120 can be dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM) etc..However, it is necessary to It is appreciated that, the invention is not limited thereto, and mainframe memory 120 is also possible to other suitable memories.

Store controller 210 refers to execute multiple logic gates with hardware pattern or firmware pattern actual fabrication or control It enables and carries out in reproducible nonvolatile memorizer module 220 according to the instruction of host system 10 write-in of data, read The operation such as take and erase.

In more detail, the processor 211 in store controller 210 is the hardware for having operational capability, to control The integrated operation of store controller 210.Specifically, processor 211 has multiple control instructions, and grasps in storage device 20 When making, the operations such as these control instructions can be performed to carry out the write-in of data, read and erase.

It is noted that in the present embodiment, processor 110 and processor 211 are, for example, central processing unit The place of (Central Processing Unit, CPU), microprocessor (micro-processor) or other programmables Manage unit (Microprocessor), digital signal processor (Digital Signal Processor, DSP), programmable Controller, Application Specific Integrated Circuit (Application Specific Integrated Circuits, ASIC), can program Change logic device (Programmable Logic Device, PLD) or other similar circuit element, the present invention is not limited thereto.

In one embodiment, store controller 210 also has read-only memory (not shown) and random access memory (not It shows).In particular, this read-only memory has boot code (boot code), and when store controller 210 is enabled, place Reason device 211 can first carry out the control instruction that this boot code will be stored in reproducible nonvolatile memorizer module 220 and carry Enter into the random access memory of store controller 210.Later, processor 211 can operate these control instructions to be counted According to write-in, the operation such as read and erase.In another embodiment, the control instruction of processor 211 can also be with procedure code pattern It is stored in the specific region of reproducible nonvolatile memorizer module 220, for example, reproducible nonvolatile memorizer module It is exclusively used in 220 in the physical storage unit of storage system data.

In the present embodiment, as described above, store controller 210 further includes data management circuit 212 and memory interface Control circuit 213.It should be noted that operation performed by each component of store controller 210 also can be considered 210 institute of store controller The operation of execution.

Wherein, data management circuit 212 is electrically connected to processor 211, memory interface control circuit 213 connects with connection Mouth circuit 230.Data management circuit 212 carries out the transmission of data to receive the instruction of processor 211.For example, via even Interface circuit 230 reads data from host system 10 (e.g., mainframe memory 120), and by read data via depositing Memory interface control circuit 213 is written into reproducible nonvolatile memorizer module 220 (e.g., according to from host system 10 write instruction carries out write operation).In another example non-volatile from duplicative via memory interface control circuit 213 Property memory module 220 one or more physical units in read data (data are readable to be derived from one or more physical units One or more memory cells), and read data are written via connecting interface circuit 230 to 10 (e.g., host of host system Memory 120) in (e.g., be read according to the reading instruction from host system 10).In another embodiment, number It can also be integrated into processor 211 according to management circuit 212.

Instruction of the memory interface control circuit 213 to receive processor 211, cooperation data management circuit 212 come into Row grasps write-in (also referred to as, sequencing, Programming) operation, the reading of reproducible nonvolatile memorizer module 220 Make or operation of erasing.

For example, write instruction sequence can be performed in processor 211, to indicate that memory interface control circuit 213 will count According to write-in into reproducible nonvolatile memorizer module 220；Processor 211 is executable to read instruction sequence, is deposited with instruction Corresponding one or more objects for reading instruction of memory interface control circuit 213 from reproducible nonvolatile memorizer module 220 It manages and reads data in unit (also referred to as, target physical unit)；The executable instruction sequence of erasing of processor 211, to indicate memory Interface control circuit 213 carries out operation of erasing to reproducible nonvolatile memorizer module 220.Write instruction sequence is read Instruction sequence and instruction sequence of erasing can be distinctly including one or more procedure codes or instruction codes and to indicate to duplicative Non-volatile memory module 220 executes corresponding write-in, the operation such as reads and erase.In one embodiment, processor 211 Other kinds of instruction sequence can also be assigned to memory interface control circuit 213, to duplicative non-volatile memories Device module 220 executes corresponding operation.

In addition, being intended to be written to the data of reproducible nonvolatile memorizer module 220 can control via memory interface Circuit 213 is converted to the 220 receptible format of institute of reproducible nonvolatile memorizer module.Specifically, if processor 211 Reproducible nonvolatile memorizer module 220 is accessed, processor 211 can transmit corresponding instruction sequence to memory interface Control circuit 213 is to indicate that memory interface control circuit 213 executes corresponding operation.For example, these instruction sequences may include The instruction of erasing for data that the write instruction sequence of instruction write-in data, instruction read the reading instruction sequence of data, instruction is erased Sequence and to indicate various storage operations (for example, change the default multiple default reading voltage values for reading voltage group with Be read, or execute garbage reclamation program etc.) corresponding instruction sequence.These instruction sequences may include one or Multiple signals, or the data in bus.These signals or data may include instruction code or procedure code.For example, referring in reading It enables in sequence, will include the information such as identification code, the storage address of reading.

Reproducible nonvolatile memorizer module 220 is electrically connected to (the memory interface control of store controller 210 Circuit 213) and the data that are written to store host system 10.Reproducible nonvolatile memorizer module 220 can be with It is single-order memory cell (Single Level Cell, SLC) NAND type flash memory module (that is, can be stored in a memory cell The flash memory module of 1 bit), multistage memory cell (Multi Level Cell, MLC) NAND type flash memory module (that is, flash memory module that 2 bits can be stored in a memory cell), three rank memory cells (Triple Level Cell, TLC) NAND type flash memory module (that is, flash memory module that 3 bits can be stored in a memory cell), quadravalence note Born of the same parents (Quadruple Level Cell, QLC) NAND type flash memory module is recalled (that is, 4 ratios can be stored in a memory cell Special flash memory module), three dimensional NAND type flash memory module (3D NAND flash memory module) or hang down Other flash memory modules such as straight NAND type flash memory module (Vertical NAND flash memory module) Or other memory modules with the same characteristics.Memory cell in reproducible nonvolatile memorizer module 220 is with battle array The mode of column is arranged.

In the present embodiment, reproducible nonvolatile memorizer module 220 has multiple word-lines, wherein the multiple Each word-line of word-line includes multiple memory cells.Multiple memory cells on same word-line can form one or more objects It manages programmed cell (physical page).In addition, multiple physical procedures units constitute physical unit (physical blocks or an object Manage erased cell).In the present embodiment, with three rank memory cells (Triple Level Cell, TLC) NAND type fast storage Module does example to illustrate, that is, in following embodiments, can store the memory cell of 3 bit values as one for one Physical procedures unit (that is, in each programming operations, it can be to a physical procedures unit then physical procedures Unit applies programming voltage with programming data), wherein each memory cell can be divided into can respectively store a bit Lower physical page (Lower Physical Page), middle physical page (Middle Physical Page) and the upper physics of value The page (Upper Physical Page).

It in the present embodiment, is using memory cell as the minimum unit that (sequencing) data are written.Physical unit is to erase Minimum unit, that is, each physical unit contains the memory cell of minimal amount being erased together.Each physical unit can have Multiple memory cells.

It should be noted that in the present embodiment, to record a physical unit information system data using the object One or more memory cells in reason unit record, or using in a system area to record the specific of all system datas One or more memory cells of physical unit record.In the present embodiment, the system data of one physical unit of correspondence includes Erase time numerical value (Program erase cycle, PEC), data resting period stamp (Data of the physical unit Retention Timestamp, DRT), the information such as reading times value (Read counter value).In more detail, whenever Processor 211 erase to a physical unit when operating, and after operation of erasing described in the completion, processor 211 can be to current right Should time numerical value of erasing of physical unit add 1 (time numerical value of e.g., erasing can erase operation and add up since 0 with each). That is, time numerical value of erasing can reflect the summation for the number of the physical unit corresponding to it being erased.The data resting period Stamp is to the resting period for the data for indicating to be stored in corresponding physical unit.The size (numerical value difference) of time stab can For indicating the sequencing of time.The present invention does not limit the long form of the time stab.Each pair of physical unit When executing write operation, the data resting period stamp that processor 211 will be updated the physical unit is that the physical unit is held The time of row said write operation.That is, the data resting period stamp of a corresponding physical unit is to indicate the physical unit Last time is performed the time (e.g., completing the local zone time of last time write operation) of write operation.Said write operation E.g. programming data is to one or more memory cells of the physical unit, or e.g. programming data is to the physics list The physical address of other kenels of member.Then, processor 211 can calculate in physical unit via data resting period stamp Data have housed the time how long apart from previous write-in.The reading times value is to count corresponding physical unit quilt The number of reading, and the reading times value can be emptied when corresponding physical unit is erased.

In the examples below, it is example using a physical blocks as a physical unit.However, in another implementation In example, a physical unit may also mean that any number of memory cell composition, depending on the demand in practice.Further, it is necessary to It is appreciated that, when processor 211 carries out the memory cell (or physical unit) in reproducible nonvolatile memorizer module 220 When grouping is operated with executing corresponding management, these memory cells (or physical unit) are to be logically grouped, and its physical location Do not change.

For example, in the present embodiment, processor 211 can be according to the reproducible nonvolatile memorizer module 220 The statistical values of multiple physical units divide the multiple physical unit to multiple physical unit groups.The statistical value includes aforementioned One of information such as erase time numerical value, data resting period stamp (also referred to as, depositing value long), reading times value or its group It closes.The multiple physical units for being divided to same physical unit group can have the physical characteristic being closer to.Processor 211 can to draw The physical unit to the same physical unit group is divided to carry out the reading of data (e.g., using phase via same group of reading voltage group With reading voltage group assign reading instruction sequence, to be read out to the physical unit for belonging to same physical unit group behaviour Make).

In other embodiments, processor 211 can be according to multiple words of the reproducible nonvolatile memorizer module 220 The statistical value of first line divide the multiple word-line to multiple word-line groups (the statistics available each word-line of processor 211 it is above-mentioned Statistical value), and the multiple word-lines for being divided to same word-line group can have the physical characteristic being closer to, and then such as above-mentioned It is read as embodiment by same group of reading voltage (e.g., corresponding optimization reads voltage).It should be noted that in order to can be more The reading voltage for subtly carrying out corresponding to each word-line for each word-line optimizes operation (rather than for each physics Unit), embodiment below is to optimize operation and reading voltage therein most to illustrate to read voltage for each word-line Goodization method.So, for the embodiment of multiple physical unit groups, processor 211 can select one from each physical unit group The word-line of physical unit optimizes operation to be read out voltage, or a physical unit is selected from each physical unit group Operation is optimized to be read out voltage.

Store controller 210 can configure multiple logic units to reproducible nonvolatile memorizer module 220.Host system System 10 is the logic unit by being configured to access the user's data being stored in multiple physical units.Here, each Logic unit can be to be made of one or more logical addresses.For example, logic unit can be logical blocks (Logical Block), logical page (LPAGE) (Logical Page) or logic sector (Logical Sector).One logic unit can be Map to one or more physical units, wherein physical unit can be one or more physical address, one or more physics fan, one or Multiple physical procedures units or one or more physical erase units.In the present embodiment, logic unit is logical blocks, and And logical subunit is logical page (LPAGE).Each logic unit has multiple logical subunits.

In addition, store controller 210, which can establish logic, turns physical address mapping table (Logical To Physical Address mapping table) with physics turn logical address mapping table (Physical To Logical address Mapping table), to record logic unit (e.g., the logic area for being allocated to reproducible nonvolatile memorizer module 220 Block, logical page (LPAGE) or logic sector) with physical unit (e.g., physical erase unit, physical procedures unit, physical sector) between Mapping relations.In other words, store controller 210 can be turned physical address mapping table by logic and be reflected to search a logic unit The physical unit penetrated, and store controller 210 can be turned logical address mapping table by physics and be reflected to search a physical unit The logic unit penetrated.However, the above-mentioned technological concept in relation to logic unit and physical unit mapping is those skilled in the art's Conventional techniques are repeated no more in this.

In the present embodiment, error checking and correcting circuit 214 are electrically connected to processor 211 and to execute mistake Erroneous detection is looked into and correction program is to ensure the correctness of data.Specifically, it is write when processor 211 is received from host system 10 When entering to instruct, error checking can generate corresponding error correcting code with correcting circuit 214 for the data of this corresponding write instruction (error correcting code, ECC) and/or error checking code (error detecting code, EDC), and handle The data of this corresponding write instruction can be written with corresponding error correcting code and/or error checking code to duplicative for device 211 In non-volatile memory module 220.Later, when processor 211 is read from reproducible nonvolatile memorizer module 220 The corresponding error correcting code of this data and/or error checking code, and error checking and correcting circuit can be read when data simultaneously 214 can execute error checking and correction program to read data according to this error correcting code and/or error checking code.This Outside, after error checking and correction program, if read data are successfully decoded, error checking can be returned with correcting circuit 214 Erroneous bit value is to processor 211.

In one embodiment, store controller 210 further includes buffer storage 216 and electric power management circuit 217.Buffering is deposited Reservoir is electrically connected to processor 211 and is configured to temporarily store data from host system 10 and instruction, from can answer The data or other system datas to managing storage 20 of formula non-volatile memory module 220 are write, to allow processor 211 can rapidly access the data, instruction or system data from buffer storage 216.Electric power management circuit 217 is electrically It is connected to processor 211 and the power supply to control storage device 20.

In the present embodiment, voltage management circuitry unit 215 is read to include shift numbers counting circuit 2151 and read electric Press optimization circuits 2152.It is described read voltage management circuitry unit 215 to execute to the reading voltage of multiple word-lines into Row management.More specifically, processor 211 can select reproducible nonvolatile memorizer module at specific time point One of word-line (also referred to as, target word-line) of the 220 multiple word-lines for belonging to multiple physical units, and indicate It reads voltage management circuitry unit 215 and optimizes operation to be read out voltage to this target word-line.For example, processor 211 can be at 20 leisure of (1) storage device (that is, storage device 20 be idle more than a predetermined time threshold value)；(2) storage device When opening electricity；Or (3) when being more than a number of error bits threshold value from the number of error bits of the read data of a word-line, from institute Have and a target word-line is selected to be read out voltage optimization operation in word-line.Wherein, processor 211 can be according to all characters One of statistical value of line group and number of error bits or combinations thereof, come select the poor word-line group of physical state (for example, Number of erasing is more, reading times are more, deposits the word-line group that the time is longer or number of error bits is more long) in a word-line As target word-line.In addition, the error bit that processor 211 can also be returned according to error checking and correcting circuit 214 Number, carrys out selection target word-line.Specifically, when being more than a wrong ratio from the number of error bits of the read data of a word-line When special number threshold value, wherein the word-line is set to the target word-line.It should be noted that the target word-line storage selected There are data, that is, be programmed data.In addition, if the reading voltage optimization operation for a target word-line is complete At reading voltage management circuitry unit 215 can record the reading voltage group of the corresponding target word member line.

In one embodiment, processor 211 can also select target word-line at random to be read out voltage and optimize operation. In another embodiment, processor 211 directly can also be read out voltage to each word-line and optimize operation.In addition, logical It crosses reading voltage and optimizes operation, the efficiency of decoding operate can be improved.

Multiple attached drawings can be cooperated below to be described in detail and read how voltage management circuitry unit 215 is read out voltage most The details and shift numbers counting circuit 2151 of goodization operation and the function of reading voltage optimization circuits 2152.

Fig. 2 is the flow chart of coding/decoding method shown by an embodiment according to the present invention.Referring to Fig. 1 and Fig. 2, In the step s 21, processor 211 selects the target word-line in the multiple word-line, and wherein preset data has been programmed Into multiple target memory born of the same parents of the target word-line.

Assuming that processor 211 is at present read out one of multiple word-line groups (also referred to as, target word-line group) Voltage optimizes operation.Processor 211 first therefrom can select voltage to be read out to optimize the target word-line operated.Target Word-line can be selected from multiple word-lines of target word-line group according to specific alternative condition.The specific alternative condition packet Include the statistical value of (1) target word-line close to the statistical value of all word-lines in the word-line group belonging to it average value； (2) number of error bits of target word-line is the reckling of all word-lines in the word-line group belonging to it；Or (3) randomly select One word-line is as target word-line.The target word-line stores preset data.

In the present embodiment, as described above, target word-line stores preset data.Specifically, each word-line Multiple memory cells the bit of one of corresponding different multiple Ge Lei codes (Grey Code) is stored to be programmed Value, and the sum of the Ge Lei code is N, and N is one first predetermined positive greater than 2.In other words, target word-line is multiple Preset data stored by memory cell can have the bit value for respectively corresponding different Ge Lei codes (also referred to as, storing state).

In step S23, voltage management circuitry unit 215 (or shift numbers counting circuit 2151) is read according to described pre- If data identify multiple predetermined bit values stored by the multiple target memory born of the same parents.Specifically, the preset data tool There are multiple predetermined bit values.The multiple predetermined bit value may include all of reproducible nonvolatile memorizer module 220 Different multiple storing states (also referred to as, Ge Lei code, Grey Code) that each memory cell of memory cell can have.Following elder generation Cooperate Fig. 3 to illustrate the details of the multiple Ge Lei code.

Fig. 3 is two different the reading voltage groups and voltage difference therein according to shown by one embodiment of the invention Schematic diagram.Referring to figure 3., since the present embodiment is with three rank memory cell NAND type flash memory modules to do example to illustrate, Wherein N is equal to 8 (that is, 2³).There are three physical pages for each memory cell tool of three rank memory cell NAND type flash memory modules Bit data is stored respectively, and each memory cell includes the lower physical page (Lower that can respectively store a bit value Physical Page, L), middle physical page (Middle Physical Page, M) and upper physical page (Upper Physical Page, U).Assuming that storing the critical voltage distribution of the multiple target memory born of the same parents of preset data (Threshold Voltage Distribution) as illustrated in FIG. 3, and processor 211 can read voltage group using default Default reading voltage V (1) in V (1)₁~V (1)₇Accurately to judge (bit) shape stored by the multiple target memory born of the same parents State (also referred to as, bit value, bit value), that is, determine multiple predetermined bit values of the preset data stored by the memory cell.Institute It states the different predetermined bit values stored by the multiple memory cell determined and is divided into N kind Ge Lei code (storing state).Often Grid voltage in one target memory born of the same parents can be according to default reading voltage V (1)₁~V (1)₇And 8 kinds of Ge Lei codes are divided into, such as " L: 1M:1U:1”、“L:1M:1U:0”、“L:1M:0U:0”、“L:1M:0U:1”、“L:0M:0U:1”、“L:0M:0U:0”、“L:0M: (" L: " indicates the bit value of lower physical page to 8 kinds of Ge Lei codes of 1U:0 " and " L:0M:1U:1 "；Physical page in " M: " expression Bit value；The bit value of physical page in " U: " expression).8 kinds of Ge Lei codes be also referred to as " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " and " 011 ", 8 kinds of bit value combinations, wherein the elder generation of the bit value in each bit value combinations Afterwards sequence be according under, in, the sequence of upper physical page.That is, via default reading voltage group V (1) is applied respectively The default reading voltage V (1) of different voltages value₁~V (1)₇To a memory cell of target word-line, processor 211 can basis Judge whether the channel of the memory cell is connected and determine respectively the bit value stored by the memory cell (also referred to as, bit data or Read bit value) corresponding different multiple Ge Lei codes (" 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " or " 011 ") one of (that is, the type for identifying the Ge Lei code stored by each target memory born of the same parents).For example, reading voltage V (1)₁Ge Lei code " 111 " and Ge Lei code " 110 " can be distinguished (to read voltage V (1)₁Left be corresponding Ge Lei code " 111 " memory The critical voltage of born of the same parents is distributed；It reads voltage V (1)₁Right be corresponding Ge Lei code " 110 " memory cell critical voltage distribution). It should be noted that the multiple Ge Lei codes that can have of memory cell in reproducible nonvolatile memorizer module 220 number ( In this example, for 8), the number of each the multiple reading voltage for reading voltage group is that the number of the multiple Ge Lei code subtracts One (being 7, that is, N-1=8-1=7 in this example).

It should be noted that according to the type of reproducible nonvolatile memorizer module 220, N may be greater than 2 it is predetermined just Integer (also referred to as, the first predetermined positive).For example, if reproducible nonvolatile memorizer module 220 is MLC, N=4；If Reproducible nonvolatile memorizer module 220 is SLC, then N=2；If reproducible nonvolatile memorizer module 220 is QLC, then N=16.

It is noted that in the present embodiment, the critical voltage distributions of multiple memory cells of target word-line compared to The phenomenon that preset critical voltage distribution may shift.Due to the offset of critical voltage distribution, correspond to originally default The default reading voltage group of critical voltage has been no longer appropriate for having the word-line for having deviated critical voltage distribution to read.Place In addition reason device 211 need to find out the multiple reading voltages for more preferably corresponding to target word-line, so that the multiple reading voltage can be each From the intersection close to corresponding two adjacent critical voltages distribution, so make the multiple reading combinations of voltages found at The optimization that voltage group is read as target word-line reads voltage group.In this way, read voltage group via using to optimize It reads the preset data the multiple reading bit value obtained being stored in target memory and is close to the predetermined bit Value.

Fig. 2 please be return, after completing step S23, reading voltage management circuitry unit 215 (or shift numbers calculate electricity Road 2151) it can be seen that all storage shapes that the multiple predetermined bit value being stored in the multiple target memory born of the same parents is included State.In other words, the multiple predetermined bit value of the preset data stored by the multiple target memory born of the same parents can be one or more A " 111 ", one or more " 110 ", one or more " 100 ", one or more " 101 ", one or more " 001 ", one or more " 000 ", one or more " 010 " and one or more " 011 ".The predetermined bit value of the preset data can be preparatory by processor 211 It is set as fixed bit value, and processor 211 is read before voltage optimizes operation in execution just by this preset data It is first written into multiple target memory born of the same parents of target word-line and (e.g., is stored using physical unit belonging to target word-line When user's data, preset data is first written to target word-line).In other words, processor 211 (or read voltage management circuitry Unit 215) it can be not necessary to via read operation, and it is default in the multiple target memory born of the same parents that storage (sequencing) is known in advance The multiple predetermined bit value of data, and it is also known that can be right according to Ge Lei code belonging to stored predetermined bit value It is grouped multiple target memory born of the same parents groups that the multiple target memory born of the same parents are corresponding different storing states (Ge Lei code) with answering.For example, Manufacturer can preset used in preset data the multiple preparatory bit value, and by record to reading voltage management In circuit unit 215.In one embodiment, the predetermined bit value (and corresponding target word-line) can be predetermined (and record) In the firmware or software to run processor 211.In another embodiment, the preset data can also be to be stored in institute User's data in multiple target memory born of the same parents are stated, and this user's data is to be decoded into the data of function, is located with allowing Managing device 211 (or reading voltage management circuitry unit 215) (can be decoded using user's data after successfully decoded with when reading Before) user's data be compared, and then find out optimization and read voltage group

Then, in step s 25, reading voltage management circuitry unit 215 (or shift numbers counting circuit 2151) can divide X reading voltage group that Li Yong be not different reads the multiple target memory born of the same parents, respectively corresponds the X reading voltage to obtain X reading bit value group of group, and obtained via the X reading bit value group with the multiple predetermined bit value X shift numbers summation group, wherein X is the second predetermined positive.More specifically, the X reading voltage group is pre- with first Fixed sequence arranges, and it is first pre- that described X, which is read the voltage difference that adjacent in voltage group two read between voltage group, Constant voltage is poor, and wherein each described X is read the N-1 reading electricity that voltage group has foundation one second predetermined order arrangement Pressure, and each described X shift numbers summation group has the N-1 shift numbers arranged according to second predetermined order total With.In addition, described X i-th of the reading bit value group read in bit value group corresponds to i-th in the X reading voltage group A reading voltage group, i-th of shift numbers summation group in the X shift numbers summation group correspond to the X reading voltage I-th of reading voltage group in group, and j-th of shift numbers summation in i-th of shift numbers summation group corresponds to institute State N-1 j-th of the reading voltage read in voltage of i-th of reading voltage group.Illustrate the X reading below by way of Fig. 3 Take the details of voltage group.

Referring to FIG. 3, as an example it is assumed that N=8, first read voltage group V (1) be in the X reading voltage group according to According to the first tactic first reading voltage group (e.g., preset and read voltage group), and the second reading voltage group V (2) is Second reading voltage group of the X reading voltage group, is arranged wherein the first reading voltage group V (1) has according to the second sequence N-1 reading voltage V (1) of column₁、V(1)₂、V(1)₃、V(1)₄、V(1)₅、V(1)₆、V(1)₇, and second reads voltage group V (2) have according to second tactic a reading voltage V (2) of 7 (that is, N-1=8-1=7)₁、V(2)₂、V(2)₃、V(2)₄、V (2)₅、V(2)₆、V(2)₇.This two adjacent voltage difference read between voltage group is the first predetermined voltage difference (V_offset)。 For example, second reads first reading voltage V (2) of voltage group₁The first reading electricity for reading voltage group with corresponding first It presses V (1)₁Between voltage difference be the first predetermined voltage difference (V_offset), that is, it reads voltage V (2)₁Voltage value subtract reading Voltage V (1)₁Voltage value difference be equal to V_offset.In other words, for two adjacent readings in the X reading voltage group Voltage group is taken, wherein the voltage difference between the identical reading voltage that puts in order is all the first fixed predetermined voltage difference V_offset。

In the present embodiment, it is utilized respectively the different X reading voltage groups above-mentioned and reads those target memories born of the same parents, In operation to obtain X reading bit value group for respectively corresponding the X reading voltage group, the reading voltage management circuitry Described X i-th of the reading voltage group read in voltage group may be selected in unit 215 (or shift numbers counting circuit 2151), First predetermined order described in the numerical basis of middle i is 1 to X.Then, (or the offset numbers of the reading voltage management circuitry unit 215 Mesh counting circuit 2151) it is utilized respectively the multiple target note of N-1 reading voltage reading that described i-th is read in voltage group Recall born of the same parents, to obtain the multiple reading bit values for being divided into the multiple Ge Lei code of corresponding i-th of reading voltage group, Described in multiple bit values that read be to read for described i-th of reading i-th of voltage group of the described X correspondence read in bit value group Take bit value group, wherein it is described i-th read voltage group in it is described N-1 reading voltage in j-th of reading voltage to Distinguish j-th of Ge Lei code in corresponding N number of Ge Lei code critical voltage be distributed with the jth in corresponding N number of Ge Lei code+ The critical voltage distribution of 1 Ge Lei code, wherein j is 1 to N-1 according to second predetermined order.Via using X reading voltage Group reads the multiple target memory born of the same parents to obtain corresponding reading bit group (with corresponding the multiple target memory born of the same parents therein Multiple reading bits) after, read voltage management circuitry unit 215 (or shift numbers counting circuit 2151) can be according to the X It is a to read bit group to identify the multiple reading bit values for the multiple target memory born of the same parents for corresponding to the X reading voltage group.

In the present embodiment, come above-mentioned via the X reading bit value group and the multiple predetermined bit value In the operation for obtaining X shift numbers summation group, the reading voltage management circuitry unit 215 (or shift numbers counting circuit 2151) the following steps (1)~(4) are executed.

Step (1): the reading voltage management circuitry unit 215 (or shift numbers counting circuit 2151) is according to described more (e.g., the multiple target memory born of the same parents are divided to by a predetermined bit value respectively corresponds N number of target memory born of the same parents group of N number of Ge Lei code G1~G8), wherein N number of Ge Lei code sorts according to a third predetermined order (e.g., 1 to 8).

Specifically, according to the multiple predetermined bit value, the reading voltage management circuitry unit 215 (or offset numbers Mesh counting circuit 2151) whole target memory born of the same parents can be divided into stored predetermined bit value be corresponding Ge Lei code " 111 " Target memory born of the same parents organize target memory born of the same parents group G2 that G1, stored predetermined bit value are corresponding Ge Lei codes " 110 ", stored Predetermined bit value is that the target memory born of the same parents of corresponding Ge Lei code " 100 " organize G3, stored predetermined bit value is corresponding Ge Lei code It is the target memory born of the same parents of " 101 " organize G4, stored predetermined bit value is corresponding Ge Lei code " 001 " target memory born of the same parents group G5, right The target memory born of the same parents that the target memory born of the same parents of Ying Gelei code " 000 " organize G6, stored predetermined bit value is corresponding Ge Lei code " 010 " Group G7 and stored predetermined bit value are that the target memory born of the same parents of corresponding Ge Lei code " 011 " organize G8.

Step (2): the reading voltage management circuitry unit 215 (or shift numbers counting circuit 2151) is directed to the X I-th of shift numbers summation group of corresponding i-th of reading voltage group, selects the X reading ratio in a shift numbers summation group I-th of reading bit value group in paricular value group, wherein the first predetermined order described in the numerical basis of i is 1 to X, wherein described i-th A reading bit value group is to calculate i-th of shift numbers summation group in the X shift numbers summation group.

Specifically, in order to which each the shift numbers summation group for obtaining the X shift numbers summation group e.g. corresponds to I-th of shift numbers summation group of i-th of reading voltage group.The reading voltage management circuitry unit 215 (or shift numbers meter Calculate circuit 2151) i-th of reading bit value group can be accordingly selected, and identified according to i-th of reading bit value group The multiple target memory born of the same parents read multiple reading bit values that voltage group reads and obtains by i-th.

Step (3): the reading voltage management circuitry unit 215 (or shift numbers counting circuit 2151) is for described the J-th of shift numbers summation of j-th of reading voltage of i-th of reading voltage group is corresponded in i shift numbers summation group, Identify be divided in N number of target memory born of the same parents group j-th of target memory born of the same parents group multiple first object memory cells and Multiple second target memory born of the same parents of+1 target memory born of the same parents of jth group in N number of target memory born of the same parents group are divided to, wherein institute State the j-th target memory born of the same parents of j-th of the reading voltage to distinguish j-th of Ge Lei code in corresponding N number of Ge Lei code The critical voltage of group is distributed and+1 target memory born of the same parents' group of the jth of+1 Ge Lei code of jth in corresponding N number of Ge Lei code Critical voltage distribution.

Specifically, in order to obtain each of j-th of the reading voltage shift numbers of i-th of reading voltage group The value of summation, that is, j-th of shift numbers summation of j-th of reading voltage of corresponding i-th of reading voltage group.The reading It takes voltage management circuitry unit 215 (or shift numbers counting circuit 2151) that can identify to be distinguished via j-th of reading voltage Two target memory born of the same parents group and the target memory born of the same parents therein of two Ge Lei codes.

As an example it is assumed that N=8, i=1, j=2, that is, for the 1st (i=corresponding in the 1st shift numbers summation group 1) the 2nd reading voltage V (1) of voltage group V (1) is read₂The 2nd (j=2) shift numbers summation S (1)₂.The reading electricity Pressure pipe reason circuit unit 215 (or shift numbers counting circuit 2151) first identification should can be read voltage V (1)₂The mesh distinguished Mark multiple first in memory cell group G2 (that is, the 2nd target memory born of the same parents group being divided in 8 target memories born of the same parents' group) Target memory born of the same parents and target memory born of the same parents organize G3 (that is, the 3rd (j+1=3) mesh being divided in 8 target memories born of the same parents' group Mark memory cell group) in multiple second target memory born of the same parents.

Then, the reading voltage management circuitry unit 215 (or shift numbers counting circuit 2151) can execute step (4): the reading voltage management circuitry unit 215 (or shift numbers counting circuit 2151) is according to i-th of reading bit Value group identifies that multiple the first of the multiple first object memory cell of j-th of target memory born of the same parents group read bit value, and And multiple the second of the multiple second target memory born of the same parents of identification+1 target memory born of the same parents of jth group read bit value.

For example, above-mentioned example is connected, the reading voltage management circuitry unit 215 (or shift numbers calculate electricity Road 2151) it can identify that target memory born of the same parents organize multiple reading bit values (also referred to as, the first reading of multiple first object memory cells in G2 Take bit value) with target memory born of the same parents organize G3 in multiple second target memory born of the same parents multiple reading bit values (also referred to as, second read Bit value).

Then, step (5): reading voltage management circuitry unit 215 (or the shift numbers counting circuit 2151) basis The multiple first reading bit value belongs to the more of+1 Ge Lei code of the jth to identify in the multiple first reading bit value The number that a third reads bit value is one first shift numbers, and reads bit value according to the multiple second to identify State that belong to the number that multiple the four of j-th of Ge Lei code reads bit values in multiple second readings bit values be one second inclined Move number.

Specifically, ideally, target memory born of the same parents organize the multiple the first of the multiple first object memory cell of G2 The storing state for reading bit value should come under the 2nd Ge Lei code " 110 " in N number of Ge Lei code (that is, the multiple the The default storage state of one target memory born of the same parents/default bit value that reads should be " 110 ").If the multiple first reads bit value In, the storing state that multiple thirds read bit values is the 3rd Ge Lei code " 100 " belonged in N number of Ge Lei code, then this The number (storing the number that these thirds read the first object memory cell of bit value) that a little thirds read bit value is identified For the first shift numbers, to indicate to occur in the multiple first object memory cell the first offset (that is, storing state is from pre- If storing state toward " right side " offset) target memory born of the same parents number.As illustrated in FIG. 4, the 2nd of corresponding 1st reading voltage group A the first shift numbers for reading voltage again can be with " C (1)_G2G3" indicate, wherein " (1) " is to indicate corresponding 1st reading electricity Pressure group, " G2G3 " is to indicate that the default storage state offset for organizing G2 from corresponding target memory born of the same parents organizes G3 to target memory born of the same parents are corresponded to Storing state.In addition, being appreciated that corresponding reading voltage is in the reading voltage group to distinguish mesh again from " G2G3 " It marks storing state belonging to memory cell group G2 and target memory born of the same parents organizes the 2nd reading voltage of storing state belonging to G3, and The sequence of " G2 " and " G3 " may also indicate that the direction of offset is from G2 toward G3 in " G2G3 ", that is, partially by first from left to right The direction of shifting.

Similarly, ideally, target memory born of the same parents organize the multiple second reading of the multiple second target memory born of the same parents of G3 Take the storing state of bit value that should come under the 3rd Ge Lei code " 100 " in N number of Ge Lei code (that is, the multiple second The default storage state of target memory born of the same parents/default bit value that reads should be " 100 ").If the multiple second reads in bit value, It is multiple four read bit values storing states be the 2nd Ge Lei code " 110 " belonged in N number of Ge Lei code, then these The number (number for storing the second target memory born of the same parents of these the 4th reading bit values) of 4th reading bit value is identified as Second shift numbers, to indicate to occur in the multiple second target memory born of the same parents the second offset (that is, storing state is from default Storing state toward " left side " offset) target memory born of the same parents number.As illustrated in FIG. 4, the 2nd of corresponding 1st reading voltage group The second shift numbers for reading voltage again can be with " C (1)_G3G2" indicate, wherein " (1) " is to indicate corresponding 1st reading voltage Group, " G3G2 " is to indicate the default storage state offset for organizing G3 from corresponding target memory born of the same parents to corresponding target memory born of the same parents group G2's Storing state.In addition, being appreciated that corresponding reading voltage is in the reading voltage group to distinguish target again from " G3G2 " Storing state belonging to memory cell group G3 and target memory born of the same parents organize the 2nd reading voltage of storing state belonging to G2, and institute The sequence for stating in " G3G2 " " G3 " and " G2 " may also indicate that the direction of offset is from G3 toward G2, that is, the second offset turned left by the right side Direction.

Step (6): the reading voltage management circuitry unit 215 (or shift numbers counting circuit 2151) calculates described the The summation of one shift numbers and second shift numbers, using the summation as i-th of shift numbers summation group J-th of shift numbers summation in the N-1 shift numbers summation.

Above-mentioned example is connected, the reading voltage management circuitry unit 215 (or shift numbers counting circuit 2151) adds Total corresponding reading voltage V (1)₂The first shift numbers C (1)_G2G3With the second shift numbers C (1)_G3G2, obtained and value is made For the 2nd shift numbers summation S (1) in the N-1 shift numbers summation of the 1st shift numbers summation group₂。

The rest may be inferred, and the reading voltage management circuitry unit 215 (or shift numbers counting circuit 2151) can be via institute 1st reading voltage V (1) of the correspondence of acquisition the 1st reading voltage group₁The first shift numbers C (1)_G1G2Partially with second It moves number C (1)_G2G1, the 1st in the N-1 shift numbers summation to calculate the 1st shift numbers summation group Shift numbers summation S (1)₁；Via the 3rd reading voltage V (1) of the correspondence obtained 3rd reading voltage group₃? One shift numbers C (1)_G3G4With the second shift numbers C (1)_G4G3, to calculate the N- of the 1st shift numbers summation group The 3rd shift numbers summation S (1) in 1 shift numbers summation₃；Via the correspondence obtained 1st reading voltage group The 4th reading voltage V (1)₄The first shift numbers C (1)_G4G5With the second shift numbers C (1)_G5G4, to calculate the described 1st The 4th shift numbers summation S (1) in the N-1 shift numbers summation of a shift numbers summation group₄；Via being obtained Correspondence it is described 1st reading voltage group the 5th reading voltage V (1)₅The first shift numbers C (1)_G5G6With the second offset numbers Mesh C (1)_G6G5, the 5th offset in the N-1 shift numbers summation to calculate the 1st shift numbers summation group Number summation S (1)₅；Via the 6th reading voltage V (1) of the correspondence obtained 1st reading voltage group₆First partially It moves number C (1)_G6G7With the second shift numbers C (1)_G7G6, to calculate the N-1 of the 1st shift numbers summation group The 1st shift numbers summation S (1) in shift numbers summation₆；Via the correspondence obtained 1st reading voltage group 7th reading voltage V (1)₇The first shift numbers C (1)_G7G8With the second shift numbers C (1)_G8G7, to calculate described 1st The 7th shift numbers summation S (1) in the N-1 shift numbers summation of shift numbers summation group₇.In this way, just obtain Obtained the whole N-1 shift numbers summation of the 1st shift numbers summation group.Then, the X shift numbers are total It can also obtain, repeat no more in this according to above-mentioned steps with group.

The direction of first offset (also referred to as, forward migration) is positive voltage direction (e.g., turning right " → "), and second is inclined The direction for moving (also referred to as, negative offset) is negative voltage direction (e.g., turning left " ← ").

Fig. 5 is the signal according to shown by one embodiment of the invention to the statistical form of record-shifted number summation Figure.Referring to figure 5., in the present embodiment, described in processor 211 can record in the way of such as one statistical form 510 of record The X shift numbers summation group of multiple target memory born of the same parents.Wherein, according to the second predetermined order, the X reading voltage group I-th reading voltage group the 1st reading voltage V (i)₁All the 1st of the corresponding X shift numbers summation group is inclined It moves number summation S (1)₁~S (X)₁；2nd reading voltage V (i)₂All 2 of the corresponding X shift numbers summation group A shift numbers summation S (1)₂~S (X)₂；3rd reading voltage V (i)₃Correspond to all of the X shift numbers summation group 3rd shift numbers summation S (1)₃~S (X)₃；4th reading voltage V (i)₄The institute of the corresponding X shift numbers summation group The 4th shift numbers summation S (1) having₄~S (X)₄；5th reading voltage V (i)₅The corresponding X shift numbers summation group All the 5th shift numbers summation S (1)₅~S (X)₅；6th reading voltage V (i)₆The corresponding X shift numbers are total With all the 6th shift numbers summation S (1) of group₆~S (X)₆；7th reading voltage V (i)₇The corresponding X offset numbers All the 7th shift numbers summation S (1) of mesh summation group₇~S (X)₇。

It please return Fig. 2, after completing step S25, in step s 27, the reading voltage management circuitry unit 215 (or Read voltage optimization circuits 2152) it can determine that an optimization reads voltage group according to the X shift numbers summation group N-1 optimization reads voltage, and wherein N is the first predetermined positive greater than 2.

Specifically, according to the X shift numbers summation group obtained, the reading voltage management circuitry unit 215 X in all X shift numbers summation groups j-th of shift numbers of (or reading voltage optimization circuits 2152) identification Summation, using the reckling in the X j-th of shift numbers summations as j-th of shift numbers summation of a target；And determine Reading voltage corresponding to j-th of shift numbers summation of the target is that the N-1 for optimizing reading voltage group is a most Goodization reads j-th of optimization in voltage and reads voltage.

For example, reading voltages are optimized in order to look for the N-1 (N=8) for optimizing reading voltage group In the 1st (j=1) optimization read voltage, the readings voltage management circuitry unit 215 (or read voltage optimize it is electric Road 2152) all 1st shift numbers summation Ss (1) of the identification in all X shift numbers summation groups₁~S (X)₁, and will 1st shift numbers summation S (1)₁~S (X)₁Reckling therein is used as " the 1st shift numbers summation of target ".Assuming that the 1st Shift numbers summation S (1)₁~S (X)₁Middle reckling is the 1st shift numbers summation of the 3rd (i=3) shift numbers summation group S(3)₁, then the 1st shift numbers summation of target " can be judged as the 3rd shift numbers summation group the 1st shift numbers it is total With S (3)₁.In addition, the reading voltage management circuitry unit 215 (or reading voltage optimization circuits 2152) can determine this " mesh Mark the 1st shift numbers summation S (3)₁" corresponding to reading voltage V (3)₁For the N-1 for optimizing reading voltage group A the 1st optimization read in voltage that optimize reads voltage.The rest may be inferred, the reading voltage management circuitry unit 215 (or reading voltage optimization circuits 2152) can look for the optimization according to the X shift numbers summation group and read electricity All optimizations of pressure group read voltage (the 1st~the 7th optimization reads voltage).

In one embodiment, above-mentioned if the quantity of the reckling in the X j-th of shift numbers summations is greater than 1 The reckling in the X j-th of shift numbers summations is wrapped as the step of j-th of shift numbers summation of the target Include: (1) selects any one j-th of shift numbers total from all recklings in the X j-th of shift numbers summations With as j-th of shift numbers summation of the target；Or (2) is from all minimums in the X j-th of shift numbers summation Select to be arranged in intermediate j-th of shift numbers summation as the target jth according to first predetermined order in person A shift numbers summation.For example, if the 1st shift numbers summation S (1)₁~S (X)₁Middle reckling is S (1)₁、S(2)₁With S(3)₁, then the reading voltage management circuitry unit 215 (or reading voltage optimization circuits 2152) can randomly choose the 1st Shift numbers summation S (1)₁、S(2)₁、S(3)₁In one be used as the 1st shift numbers summation of target (above-mentioned (1))；Or institute It states and reads voltage management circuitry unit 215 (or reading voltage optimization circuits 2152) optional 1st shift numbers summation S (1)₁、S(2)₁、S(3)₁In intermediate, that is, the 1st shift numbers summation S (2)₁As the 1st shift numbers summation of target (above-mentioned (2)).

In conclusion coding/decoding method and store controller provided by the embodiment of the present invention, using target word-line Stored preset data, the reading voltage for executing the corresponding target word-line to the target word-line optimize operation. It is optimized in operation in the reading voltage, store controller is according to the preset data and via the multiple and different reading of utilization Voltage group reads target word-line multiple reading bit groups obtained, to calculate multiple shift numbers summation groups, with Determine that the optimization of the corresponding target word-line reads the multiple best of voltage group according to the multiple shift numbers summation group Change and reads voltage.In this way, which the optimal reading to read the target word-line can be looked for efficiently and quickly Voltage group, and then enhance the therefrom correctness of data streams read and enhance the effect of the decoding operate entirety for read operation Rate.

Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention Range is subject to the range defined depending on claim.

Claims

1. a kind of coding/decoding method, which is characterized in that filled suitable for the storage configured with reproducible nonvolatile memorizer module It sets, wherein the reproducible nonvolatile memorizer module has multiple word-lines, wherein the multiple word-line is each A word-line includes multiple memory cells, wherein each of the multiple memory cell memory cell is to be programmed with storage pair Answer the bit value of one of different multiple Ge Lei codes, and the sum of the multiple Ge Lei code is N, N is the greater than 2 One predetermined positive, which comprises

The target word-line in the multiple word-line is selected, wherein preset data has been programmed into the target word-line In multiple target memory born of the same parents；

Multiple predetermined bit values stored by the multiple target memory born of the same parents are identified according to the preset data；

It is utilized respectively X different reading voltage groups and reads the multiple target memory born of the same parents, respectively correspond the X reading to obtain X reading bit value group of voltage group is taken, and via the X reading bit value group and the multiple predetermined bit value X shift numbers summation group is obtained, wherein X is the second predetermined positive, and the X reading voltage group be with the first predetermined order Arrangement, and it is the first predetermined voltage that described X, which is read the voltage difference that adjacent in voltage group two read between voltage group, Difference, wherein each described X is read the N-1 reading voltage that voltage group has foundation the second predetermined order arrangement, and every One X shift numbers summation group has the N-1 shift numbers summation arranged according to second predetermined order,

Wherein described X i-th of the reading bit value group read in bit value group corresponds to i-th in the X reading voltage group A reading voltage group, i-th of shift numbers summation group in the X shift numbers summation group correspond to the X reading voltage I-th of reading voltage group in group, and j-th of shift numbers summation in i-th of shift numbers summation group corresponds to institute State N-1 j-th of the reading voltage read in voltage of i-th of reading voltage group；And

Determine that optimizing N-1 optimization for reading voltage group reads voltage according to the X shift numbers summation group.

2. coding/decoding method as described in claim 1, wherein above-mentioned be utilized respectively different X reading voltage group reading institutes Multiple target memory born of the same parents are stated, include: the step of X reading bit value group for respectively corresponding the X reading voltage group to obtain

Described X i-th of the reading voltage group read in voltage group is selected, wherein the first predetermined order described in the numerical basis of i It is 1 to X；And

It is utilized respectively the N-1 reading voltage that described i-th is read in voltage group and reads the multiple target memory born of the same parents, to obtain The multiple reading bit values for being divided into the multiple Ge Lei code of corresponding i-th of reading voltage group, wherein the multiple Read i-th of reading bit value that bit value is the described X correspondence read in bit value group i-th of reading voltage group Group, wherein described N-1 j-th of the reading voltage read in voltage in i-th of reading voltage group is to distinguish correspondence The critical voltage of j-th of Ge Lei code in N number of Ge Lei code is distributed and+1 Ge Lei of jth in corresponding N number of Ge Lei code The critical voltage distribution of code, wherein j is 1 to N-1 according to second predetermined order.

3. coding/decoding method as claimed in claim 2, wherein it is above-mentioned via the X reading bit value group with it is the multiple Predetermined bit value includes: the step of X shift numbers summation group to obtain

The multiple target memory born of the same parents are divided to the N number of mesh for respectively corresponding N number of Ge Lei code according to the multiple predetermined bit value Memory cell group is marked, wherein N number of Ge Lei code sorts according to third predetermined order；

For i-th of shift numbers summation group of i-th of reading voltage group corresponding in the X shift numbers summation group, selection It is described X read bit value group in i-th of readings bit value group, wherein the first predetermined order described in the numerical basis of i for 1 to X, wherein reading i-th shift numbers summation of the bit value group to calculate in the X shift numbers summation group for described i-th Group；

For the jth for j-th of reading voltage for corresponding to i-th of reading voltage group in i-th of shift numbers summation group A shift numbers summation identifies multiple the first of j-th of the target memory born of the same parents group being divided in N number of target memory born of the same parents group Multiple second mesh of target memory born of the same parents and+1 target memory born of the same parents of jth being divided in N number of target memory born of the same parents group group Memory cell is marked, wherein reading voltage for described j-th to distinguish described in j-th of Ge Lei code in corresponding N number of Ge Lei code The critical voltage distribution of j-th target memory born of the same parents group and the jth of+1 Ge Lei code of jth in corresponding N number of Ge Lei code+ The critical voltage distribution of 1 target memory born of the same parents group；

According to i-th of reading bit value group, the multiple first object memory of j-th of target memory born of the same parents group is identified Multiple the first of born of the same parents read bit value, and identify the multiple second target memory of+1 target memory born of the same parents of jth group Multiple the second of born of the same parents read bit value；

It is identified according to the multiple first reading bit value in the multiple first reading bit value and belongs to+1 Pueraria lobota of the jth The number that multiple thirds of thunder code read bit value is the first shift numbers, and according to the multiple second read bit value come Identify that belonging to multiple the four of j-th of Ge Lei code in the multiple second reading bit value to read the number of bit values is the Two shift numbers；And

The summation for calculating first shift numbers Yu second shift numbers, partially using the summation as described i-th Move j-th of shift numbers summation in the N-1 shift numbers summation of number summation group.

4. coding/decoding method as claimed in claim 3, wherein it is above-mentioned determined according to the X shift numbers summation group it is described most Goodization read voltage group N-1 optimization reading voltage the step of include:

X j-th of shift numbers summations in all X shift numbers summation groups are identified, by the X j-th of offset numbers Reckling in mesh summation is as j-th of shift numbers summation of target；And

Determine that reading voltage corresponding to j-th of shift numbers summation of the target is that described optimize reads the described of voltage group N-1 optimizes j-th of the optimization read in voltage and reads voltage.

5. coding/decoding method as claimed in claim 4, wherein if the reckling in the X j-th of shift numbers summations Quantity be greater than 1, the above-mentioned reckling using in the X j-th of shift numbers summation deviates for j-th as the target The step of number summation includes:

Any one j-th of shift numbers summation is selected to make from all recklings in the X j-th of shift numbers summations For j-th of shift numbers summation of the target；Or

It is arranged in from all recklings in the X j-th of shift numbers summations according to first predetermined order selection Intermediate j-th of shift numbers summation is as j-th of shift numbers summation of the target.

6. a kind of store controller, which is characterized in that be configured with depositing for reproducible nonvolatile memorizer module for controlling Storage device, the store controller include:

Connecting interface circuit, is electrically connected to host system；

Memory interface control circuit is electrically connected to the reproducible nonvolatile memorizer module, wherein described Reproducible nonvolatile memorizer module has multiple word-lines, wherein each word-line of the multiple word-line includes Multiple memory cells, wherein each of the multiple memory cell memory cell stored to be programmed it is corresponding different multiple The bit value of one of Ge Lei code, and the sum of the multiple Ge Lei code is N, and N is predetermined just whole for first greater than 2 Number；

Read voltage management circuitry unit；And

Processor is electrically connected to the connecting interface circuit, the memory interface control circuit and the reading voltage pipe Circuit unit is managed,

Wherein the processor selects the target word-line in the multiple word-line, and indicates the reading voltage management electricity The reading voltage that road unit correspond to the target word-line optimizes operation, and wherein preset data has been programmed into described In multiple target memory born of the same parents of target word-line, wherein optimized in operation in the reading voltage,

The reading voltage management circuitry unit is to identify that the multiple target memory born of the same parents are stored up according to the preset data The multiple predetermined bit values deposited；

The voltage management circuitry unit that reads also reads the multiple target to be utilized respectively X different reading voltage groups Memory cell to obtain X reading bit value group for respectively corresponding the X reading voltage group, and is read via more described X Bit value group and the multiple predetermined bit value is taken to obtain X shift numbers summation group, wherein X is the second predetermined positive, The X reading voltage group is arranged with the first predetermined order, and described X is read two reading voltages adjacent in voltage group Voltage difference between group is the first predetermined voltage difference, and wherein each described X reading voltage group has predetermined according to second Tactic N-1 reading voltage, and each described X shift numbers summation group is suitable with making a reservation for according to described second N-1 shift numbers summation of sequence arrangement,

The reading voltage management circuitry unit also reads electricity to determine to optimize according to the X shift numbers summation group N-1 optimization of pressure group reads voltage.

7. store controller as claimed in claim 6, wherein being utilized respectively different X reading voltage group readings above-mentioned The multiple target memory born of the same parents are taken, to obtain the operation for X reading bit value group for respectively corresponding the X reading voltage group In,

The i-th reading voltage group read in X reading voltage group described in voltage management circuitry Unit selection, wherein i First predetermined order described in numerical basis is 1 to X；And

The voltage management circuitry unit that reads is utilized respectively the described i-th N-1 reading voltage reading read in voltage group The multiple target memory born of the same parents are divided into the more of the multiple Ge Lei code with corresponding i-th of reading voltage group of acquisition A reading bit value, wherein the multiple bit value that reads is i-th of the reading of the described X correspondence read in bit value group I-th of reading bit value group of voltage group, wherein reading the described N-1 jth read in voltage in voltage group for described i-th It is a read voltage to distinguish the critical voltage of j-th of Ge Lei code in corresponding N number of Ge Lei code be distributed with it is corresponding described N number of The critical voltage of+1 Ge Lei code of jth in Ge Lei code is distributed, and wherein j is 1 to N-1 according to second predetermined order.

8. store controller as claimed in claim 7, wherein it is above-mentioned via the X reading bit value group with it is described In operation of multiple predetermined bit values to obtain X shift numbers summation group,

The multiple target memory born of the same parents are divided to by the reading voltage management circuitry unit according to the multiple predetermined bit value N number of target memory born of the same parents group of N number of Ge Lei code is respectively corresponded, wherein N number of Ge Lei code sorts according to third predetermined order；

The voltage management circuitry unit that reads is for i-th of reading voltage group corresponding in the X shift numbers summation group I-th of shift numbers summation group selects described X i-th of the reading bit value group read in bit value group, wherein the numerical value of i It is 1 to X according to first predetermined order, wherein i-th of reading bit value group is total to calculate the X shift numbers With i-th of shift numbers summation group in group；

The reading voltage management circuitry unit is electric for i-th of reading is corresponded in i-th of shift numbers summation group J-th of shift numbers summation of j-th of reading voltage of pressure group, identifies the jth being divided in N number of target memory born of the same parents group Multiple first object memory cells of a target memory born of the same parents group and be divided in N number of target memory born of the same parents group jth+1 Multiple second target memory born of the same parents of target memory born of the same parents group, wherein j-th of the reading voltage is to distinguish corresponding N number of Ge Lei Code in j-th of Ge Lei code j-th of target memory born of the same parents group critical voltage be distributed in corresponding N number of Ge Lei code The critical voltage distribution of+1 target memory born of the same parents group of the jth of+1 Ge Lei code of jth；

The reading voltage management circuitry unit identifies j-th of target memory born of the same parents according to i-th of reading bit value group Multiple the first of the multiple first object memory cell of group read bit value, and identify+1 target memory born of the same parents of the jth Multiple the second of the multiple second target memory born of the same parents of group read bit value；

The reading voltage management circuitry unit identifies that the multiple first reads according to the multiple first reading bit value The multiple thirds for belonging to+1 Ge Lei code of the jth in bit value read the number of bit value as the first shift numbers, and root It is identified according to the multiple second reading bit value in the multiple second reading bit value and belongs to the more of j-th of Ge Lei code A 4th number for reading bit value is the second shift numbers；And

The summation for reading voltage management circuitry unit and calculating first shift numbers Yu second shift numbers, will The summation is total as j-th of shift numbers in the N-1 shift numbers summation of i-th of shift numbers summation group With.

9. store controller as claimed in claim 8, wherein it is above-mentioned according to the X shift numbers summation group to determine It states and optimizes in the operation that N-1 that reads voltage group optimizes reading voltage,

X j-th of shift numbers that the identification of voltage management circuitry unit is read in all X shift numbers summation groups are total With using the reckling in the X j-th of shift numbers summation as j-th of shift numbers summation of target；And

The reading voltage management circuitry unit determines that reading voltage corresponding to j-th of shift numbers summation of the target is institute It states and optimizes described N-1 that reads voltage group j-th of optimization reading voltage optimized in reading voltage.

10. store controller as claimed in claim 9, wherein if the minimum in the X j-th of shift numbers summations The quantity of person is greater than 1, in the above-mentioned reckling using in the X j-th of shift numbers summations as j-th of the target In the operation of shift numbers summation,

It is described to read the selection times from all recklings in the X j-th of shift numbers summations of voltage management circuitry unit J-th of shift numbers summation of anticipating is as j-th of shift numbers summation of the target；Or

It is described to read voltage management circuitry unit from all recklings in the X j-th of shift numbers summations according to institute It states the first predetermined order and selects to be arranged in intermediate j-th of shift numbers summation as j-th of shift numbers of the target Summation.