CN110364207B

CN110364207B - Decoding method and storage controller

Info

Publication number: CN110364207B
Application number: CN201810319972.5A
Authority: CN
Inventors: 萧又华
Original assignee: Shenzhen Daxin Electronic Technology Co ltd
Current assignee: Shenzhen Daxin Electronic Technology Co ltd
Priority date: 2018-04-11
Filing date: 2018-04-11
Publication date: 2022-01-11
Anticipated expiration: 2038-04-11
Also published as: CN110364207A

Abstract

The invention provides a decoding method suitable for a rewritable nonvolatile memory module and a storage controller. The method includes selecting a target word line of the plurality of word lines, wherein preset data has been programmed into a plurality of target memory cells of the target word line; identifying a plurality of preset bit values according to the preset data; reading the plurality of target memory cells with different X read voltage sets respectively to obtain X read bit value sets respectively corresponding to the X read voltage sets, and obtaining X offset number sum sets by comparing the X read bit value sets with the preset bit values; and determining N-1 optimized read voltages of an optimized set of read voltages according to the X offset number sum set.

Description

Decoding method and storage controller

Technical Field

The present invention relates to a decoding method, and more particularly, to a decoding method and a storage controller for a storage device configured with a rewritable nonvolatile memory module.

Background

Generally, when reading data from the rewritable nonvolatile memory module, if a page read failure does not occur, the system reads the data using a predetermined read voltage set or a previously used optimal read voltage set. Until a read failure occurs, the system (storage system) does not use the preset read voltage set or the used optimal voltage and adjusts the read voltage set accordingly.

In other words, the optimum read voltage set value of the rewritable nonvolatile memory module is not fixed. However, adjusting the set of read voltages to obtain the optimal set of read voltages for reading data is resource consuming. For example, a first conventional read voltage optimization procedure always adjusts the magnitudes of a plurality of different read voltages corresponding to different threshold voltage distributions (adjusts a read voltage at the boundary of a corresponding one of a set of read voltages, and fixes the remaining read voltages in the set of read voltages) to read the data with page read failure, so as to try to obtain the best data read result and use the set of read voltages corresponding to the best data read result as the optimized set of read voltages corresponding to the physical unit for storing the data. For example, in a TLC flash memory (one cell stores 3 bits), seven read voltages in a read voltage group correspond to different voltage segments. With the conventional method, six read voltages are fixed and one read voltage is changed. If each read voltage needs to be adjusted X times (and the result obtained via the read,to compare all the results to find the best one), the number of reads used to obtain the best read voltage is (2)³-1) × X ═ 7 × X times. In addition, the above conventional practice also requires preparation of already verified data. In other words, the first conventional method consumes a lot of computing resources (adjusting the read voltage and verifying the corresponding read data) and storage space (space for storing the predetermined data), thereby reducing the decoding efficiency.

In addition, the second conventional approach is to use a plurality of adjusted read voltage sets preset on the hardware specification of the memory module to attempt to read the data, so as to find the best data reading result. Wherein the plurality of read voltages in each of the adjusted read voltage groups cannot be set by a controller of the memory device, and the number of the adjusted read voltage groups is limited. In other words, using the second conventional approach, one set of adjusted read voltages may be found to make the data read by the set of read voltages correct (decoding successful). However, the found adjusted read voltage set is not capable of finding the optimal read voltage set according to the current threshold voltage distribution as in the first conventional method. In addition, since the number and the precision of the adjusted read voltage sets are low, all the adjusted read voltage sets cannot read the read data correctly.

That is, although the second conventional method can utilize a smaller number of adjustment voltage sets to find the correct read voltage set for the read data more quickly than the first conventional method, the failure probability of the method is greater than that of the first conventional method, and the number of error bits of the read data is higher, thereby increasing the burden of decoding operation.

Therefore, it is one of the subjects studied by the skilled in the art how to optimize the read voltage quickly and efficiently without preparing verification data to improve the defects of the conventional method and further improve the read and corresponding decoding efficiency of the rewritable nonvolatile memory module.

Disclosure of Invention

The invention provides a decoding method and a storage controller, which can quickly and efficiently obtain an optimized read voltage set corresponding to a target word line accurately by using preset data stored in the target word line, and further can correctly read data from the target word line through a plurality of optimized read voltages of the optimized read voltage set and efficiently perform decoding operation.

An embodiment of the present invention provides a decoding method for a memory device configured with a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of word lines, each of the word lines includes a plurality of memory cells, each of the memory cells is programmed to store a bit value corresponding to one of a plurality of different gray codes (Grey codes), and the total number of the plurality of gray codes is N, where N is a first predetermined positive integer greater than 2. The method comprises the following steps: selecting a target word line of the plurality of word lines, wherein preset data is programmed into a plurality of target memory cells of the target word line; identifying a plurality of preset bit values stored in the target memory cells according to the preset data; reading the plurality of target memory cells with different X read voltage sets respectively to obtain X read bit value sets respectively corresponding to the X read voltage sets, and obtaining X offset number sum sets by comparing the X read bit value sets with the preset bit values, wherein X is a second predetermined positive integer, the X read voltage sets are arranged in a first predetermined order, and a voltage difference value between two adjacent read voltage sets in the X read voltage sets is a first predetermined voltage difference, wherein each of the X read voltage sets has N-1 read voltages arranged according to a second predetermined order, and each of the X offset number sum sets has N-1 offset number sums arranged according to the second predetermined order, wherein an ith read bit value set in the X read bit value sets corresponds to an ith read voltage set in the X read voltage sets Groups, an ith one of the X offset number sum groups corresponding to an ith one of the X read voltage groups, and a jth one of the ith offset number sum groups corresponding to a jth one of the ith read voltage groups; and determining N-1 optimized read voltages of an optimized set of read voltages according to the X offset number sum set.

An embodiment of the present invention provides a storage controller for controlling a storage device configured with a rewritable non-volatile memory module. The storage controller includes: the device comprises a connection interface circuit, a memory interface control circuit, a reading voltage management circuit unit and a processor. The connection interface circuit is used for electrically connecting to a host system. The memory interface control circuit is electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of word lines, each of the word lines includes a plurality of memory cells, each of the memory cells is programmed to store a bit value corresponding to one of a plurality of different gray codes (Grey codes), and the total number of the plurality of gray codes is N, where N is a first predetermined positive integer greater than 2. The processor selects a target word line of the plurality of word lines and instructs the read voltage management circuit unit to perform a read voltage optimization operation corresponding to the target word line, wherein a predetermined data is programmed into a plurality of target memory cells of the target word line, and in the read voltage optimization operation, the read voltage management circuit unit is configured to identify a plurality of predetermined bit values stored in the plurality of target memory cells according to the predetermined data; the read voltage management circuit unit is further configured to read the plurality of target memory cells respectively using different X read voltage sets to obtain X read bit value sets respectively corresponding to the X read voltage sets, and obtain X offset number sum sets by comparing the X read bit value sets with the preset bit values, wherein X is a second predetermined positive integer, the X read voltage sets are arranged in a first predetermined order, and a voltage difference between two adjacent read voltage sets in the X read voltage sets is a first predetermined voltage difference, wherein each of the X read voltage sets has N-1 read voltages arranged according to a second predetermined order, and each of the X offset number sum sets has N-1 offset number sums arranged according to the second predetermined order, wherein an ith one of the X read bit value groups corresponds to an ith one of the X read voltage groups, an ith one of the X offset number sum groups corresponds to an ith one of the X read voltage groups, and a jth one of the ith offset number sum groups corresponds to a jth one of the N-1 read voltages of the ith read voltage group; and the read voltage management circuit unit is further used for determining N-1 optimized read voltages of an optimized read voltage group according to the X offset number sum group.

Based on the above, the decoding method and the storage controller provided by the embodiments of the invention can utilize the preset data stored in the target word line to perform the read voltage optimization operation corresponding to the target word line on the target word line. In the read voltage optimization operation, the memory controller calculates a plurality of offset number banks based on the preset data and a plurality of read bit banks obtained by reading the target word line using a plurality of different read voltage banks to determine a plurality of optimized read voltages corresponding to the optimized read voltage bank of the target word line based on the plurality of offset number banks. In this way, the optimum read voltage set for reading the target word line can be efficiently and quickly found, thereby improving the accuracy of the data read therefrom and improving the overall efficiency of the decoding operation for reading.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below

Drawings

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.

Fig. 2 is a flowchart illustrating a decoding method according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating two different sets of read voltages and voltage differences therebetween according to an embodiment of the invention.

FIG. 4 is a diagram illustrating the calculation of the sum of the offset numbers according to an embodiment of the invention.

FIG. 5 is a block diagram illustrating a statistical table for recording the sum of offset numbers according to an embodiment of the present invention.

[ notation ] to show

10: host system

20: storage device

110. 211: processor with a memory having a plurality of memory cells

120: host memory

130: data transmission interface circuit

210: storage controller

212: data management circuit

213: memory interface control circuit

214: error checking and correcting circuit

215: read voltage management circuit unit

2151: offset number calculation circuit

2152: read voltage optimization circuit

216: buffer memory

217: power management circuit

220: rewritable nonvolatile memory module

230: connection interface circuit

S21, S23, S25, S27: flow steps of a decoding method

V_offset: predetermined voltage difference

V (1), V (2), V (X): read voltage set

V(1)₁～V(1)₇、V(2)₁～V(2)₇、V(i)₁～V(i)₇: read voltage

C(1)_G1G2、C(1)_G2G3、C(1)_G3G4、C(1)_G4G5、C(1)_G5G6、C(1)_G6G7、C(1)_G7G8、C(1)_G2G1、C(1)_G3G2、C(1)_G4G3、C(1)_G5G4、C(1)_G6G5、C(1)_G7G6、C(1)_G8G7: number of offsets

S(1)₁～S(1)₇、S(2)₁～S2)₇、S(X)₁～S(X)₇: sum of offset numbers

S (1) to S (X): offset number sum group

510: statistical table

G1-G8: target memory cell set/storage status/Gray code

L: bit value of lower physical page

M: bit value of medium physical page

U: bit value of upper physical page

Detailed Description

In the embodiment, the memory device includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a memory device controller (also referred to as a memory controller or a memory control circuit). Further, the storage device is used with a host system so that the host system can write data to or read data from the storage device.

Referring to fig. 1, a Host System (Host System)10 includes a Processor (Processor)110, a Host Memory (Host Memory)120, and a Data Transfer Interface Circuit (Data Interface Circuit) 130. In the present embodiment, the data transmission interface circuit 130 is electrically connected (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 are electrically connected to each other by a System Bus (System Bus).

The Memory device 20 includes a Storage Controller (Storage Controller)210, a Rewritable Non-Volatile Memory Module (Rewritable Non-Volatile Memory Module)220, and a Connection Interface Circuit (Connection Interface Circuit) 230. The Memory controller 210 includes a processor 211, a Data transmission Management Circuit (Data transmission Management Circuit)212, and a Memory Interface Control Circuit (Memory Interface Control Circuit) 213.

In the present embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform the data access operation. For example, the host system 10 can store data to the memory device 20 or read data from the memory device 20 via the data transmission interface circuit 130.

In the present embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 may be disposed on a motherboard of the host system 10. The number of the data transmission interface circuits 130 may be one or more. The motherboard can be electrically connected to the memory device 20 through the data transmission interface circuit 130 in a wired or wireless manner. The storage device 20 may be, for example, a usb disk, a memory card, a Solid State Drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), which are based on various wireless Communication technologies. In addition, the motherboard can also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like through a System bus.

In the present embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the PCI Express (Peripheral Component Interconnect Express) standard. The data transmission interface circuit 130 and the connection interface circuit 230 transmit data by using a Non-Volatile Memory interface (NVMe) protocol.

However, it should be understood that the present invention is not limited thereto, and the data transmission interface circuit 130 and the connection interface circuit 230 may also be in compliance with Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Serial Advanced Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed (UHS-eMI) interface standard, Ultra High Speed (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi-Chip Package (Multi-Chip Package) interface standard, Multi-Media Storage Card (Multi Media) interface, Flash Memory standard (MMC) interface, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In addition, in another embodiment, the connection interface circuit 230 may be packaged with the storage controller 210 in one chip, or the connection interface circuit 230 is disposed outside a chip including the storage controller 210.

In the present embodiment, the host memory 120 is used for temporarily storing instructions or data executed by the processor 110. For example, in the present exemplary embodiment, the host Memory 120 may be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), and the like. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may be other suitable memories.

The storage controller 210 is used for executing a plurality of logic gates or control commands actually manufactured in a hardware type or a firmware type and performing operations such as writing, reading and erasing of data in the rewritable nonvolatile memory module 220 according to commands of the host system 10.

In more detail, the processor 211 in the storage controller 210 is a hardware with computing capability, which is used to control the overall operation of the storage controller 210. Specifically, the processor 211 has a plurality of control instructions, and the control instructions are executed to perform data writing, reading, and erasing operations when the memory device 20 is in operation.

It should be noted that, in the embodiment, the Processor 110 and the Processor 211 are, for example, a Central Processing Unit (CPU), a Microprocessor (micro-Processor), or other Programmable Processing Unit (Microprocessor), a Digital Signal Processor (DSP), a Programmable controller, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar circuit elements, and the invention is not limited thereto.

In one embodiment, the storage controller 210 further has a read-only memory (not shown) and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory controller 210 is enabled, the processor 211 executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 220 into the ram of the memory controller 210. Then, the processor 211 operates the control commands to perform data writing, reading, and erasing operations. In another embodiment, the control instructions of the processor 211 can also be stored in the form of program codes in a specific area of the rewritable nonvolatile memory module 220, for example, in a physical storage unit of the rewritable nonvolatile memory module 220 dedicated for storing system data.

In the present embodiment, as described above, the storage controller 210 further includes the data management circuit 212 and the storage interface control circuit 213. It should be noted that the operations performed by the components of the storage controller 210 may also be regarded as operations performed by the storage controller 210.

The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used for receiving an instruction from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable nonvolatile memory module 220 (data can be read from one or more memory cells in one or more physical units) via the memory interface control circuit 213, and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read command from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

The memory interface control circuit 213 is used for receiving an instruction from the processor 211 and performing a writing (also called Programming) operation, a reading operation or an erasing operation on the rewritable nonvolatile memory module 220 in cooperation with the data management circuit 212.

For example, the processor 211 can execute a write command sequence to instruct the memory interface control circuit 213 to write data into the rewritable nonvolatile memory module 220; the processor 211 can execute a read instruction sequence to instruct the memory interface control circuit 213 to read data from one or more physical units (also referred to as target physical units) of the corresponding read instruction of the rewritable nonvolatile memory module 220; the processor 211 can execute an erase command sequence to instruct the memory interface control circuit 213 to perform an erase operation on the rewritable nonvolatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 220 to perform corresponding operations of writing, reading, and erasing. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable nonvolatile memory module 220.

In addition, the data to be written into the rewritable nonvolatile memory module 220 is converted into a format accepted by the rewritable nonvolatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable nonvolatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the command sequences may include a write command sequence for indicating writing data, a read command sequence for indicating reading data, an erase command sequence for indicating erasing data, and corresponding command sequences for indicating various memory operations (e.g., changing a plurality of preset read voltage values of a preset read voltage set for performing a read operation, or performing a garbage collection procedure, etc.). The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

The rewritable nonvolatile memory module 220 is electrically connected to the storage controller 210 (the memory interface control circuit 213) and is used for storing data written by the host system 10. The rewritable nonvolatile memory module 220 may be a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), a four-Level (QLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 4 bits in one memory Cell), a three-dimensional (3D) NAND flash memory module, a Vertical NAND flash memory module, or other flash memory modules having the same characteristics. The memory cells in the rewritable nonvolatile memory module 220 are arranged in an array.

In the embodiment, the rewritable nonvolatile memory module 220 has a plurality of word lines, wherein each word line of the plurality of word lines includes a plurality of memory cells. A plurality of memory cells on the same word line constitute one or more physical programming units (physical pages). In addition, a plurality of physical programming units can be combined into one physical unit (physical block or physical erasing unit). In the present embodiment, a Triple Level Cell (TLC) NAND flash memory module is taken as an example, i.e., in the following embodiments, a memory Cell capable of storing 3 bit values is used as a Physical programming unit (i.e., in each programming operation, a programming voltage is applied to a Physical programming unit and then a Physical programming unit to program data), wherein each memory Cell can be divided into a Lower Physical Page (Lower Physical Page), a Middle Physical Page (Middle Physical Page), and an Upper Physical Page (Upper Physical Page) capable of storing one bit value respectively.

In this embodiment, the memory cell is used as the minimum unit for writing (programming) data. The physical cells are the smallest unit of erase, i.e., each physical cell contains one of the smallest number of memory cells that are erased. Each physical unit has a plurality of memory cells.

It should be noted that, in the present embodiment, the system data for recording information of a physical unit can be recorded by using one or more memory cells in the physical unit, or by using one or more memory cells of a specific physical unit for recording all system data in one system area. In this embodiment, the system Data corresponding to a physical unit includes information such as a Program Erase Cycle (PEC), a Data Retention Timestamp (DRT), and a Read counter value (Read counter value) of the physical unit. In more detail, each time the processor 211 performs an erase operation on a physical unit, after the erase operation is completed, the processor 211 adds 1 to the current erase count value corresponding to the physical unit (e.g., the erase count value is accumulated from 0 with each erase operation). That is, the erase count value may reflect the sum of the erased counts of the corresponding physical cells. The data storage time stamp is used for indicating the storage time of the data stored in the corresponding physical unit. The size of the time stamp (difference in value) can be used to indicate the chronological order. The present invention does not limit the detailed format of the time stamp. When each pair of the physical units performs a write operation, the processor 211 updates the data storage time stamp of the physical unit to the time of the physical unit performing the write operation. That is, the data deposit time stamp corresponding to a physical unit is used to indicate the time when the physical unit was last written (e.g., the local time when the last write operation was completed). The write operation may be, for example, programming data to one or more memory cells of the physical unit, or may be, for example, programming data to other types of physical addresses of the physical unit. Processor 211 may then calculate, via the data deposit timestamp, how long the data in the physical unit has been deposited from the previous write. The reading times value is used for counting the times of reading the corresponding physical unit, and the reading times value is cleared when the corresponding physical unit is erased.

In the following embodiments, a physical block is taken as an example of a physical unit. However, in other embodiments, a physical unit may refer to any number of memory cell combinations, depending on the practical requirements. Moreover, it should be understood that when the processor 211 groups the memory cells (or physical units) in the rewritable nonvolatile memory module 220 to perform corresponding management operations, the memory cells (or physical units) are logically grouped, and their actual locations are not changed.

For example, in the embodiment, the processor 211 may divide the plurality of physical units into a plurality of physical unit groups according to the statistical values of the plurality of physical units of the rewritable nonvolatile memory module 220. The statistical value includes one or a combination of the above information such as erase count value, data storage time stamp (also called as persistent value), and read count value. A plurality of physical units divided into the same physical unit group may have closer physical characteristics. The processor 211 may perform data reading on the physical units divided into the same physical unit group through the same group of reading voltages (e.g., issue a reading command sequence using the same group of reading voltages to perform a reading operation on the physical units belonging to the same physical unit group).

In other embodiments, the processor 211 may divide the word lines into word line groups according to statistics of the word lines of the rewritable nonvolatile memory module 220 (the processor 211 may count the statistics of each word line), and the word lines divided into the same word line group may have closer physical characteristics, and thus may be read by the same set of read voltages (e.g., corresponding optimized read voltages) as in the above embodiments. It should be noted that, in order to perform the read voltage optimization operation corresponding to each word line more finely for each word line (rather than for each physical unit), the following embodiments describe the read voltage optimization operation and the read voltage optimization method thereof for each word line. However, for embodiments with multiple physical cell groups, the processor 211 may select a word line of one physical cell from each physical cell group for the read voltage optimization operation, or select a physical cell from each physical cell group for the read voltage optimization operation.

The storage controller 210 configures a plurality of logic units to the rewritable nonvolatile memory module 220. The host system 10 accesses the user data stored in the plurality of physical units through the configured logical unit. Here, each logical unit may be composed of one or more logical addresses. For example, a Logical unit may be a Logical Block (Logical Block), a Logical Page (Logical Page), or a Logical Sector (Logical Sector). A logical unit may be mapped to one or more physical units, where a physical unit may be one or more physical addresses, one or more physical sectors, one or more physical programming units, or one or more physical erasing units. In this embodiment, the logic units are logic blocks, and the logic sub-units are logic pages. Each logic unit has a plurality of logic sub-units.

In addition, the storage controller 210 establishes a Logical To Physical address mapping table (Logical To Physical address mapping table) and a Physical To Logical address mapping table (Physical To Logical address mapping table) To record a mapping relationship between a Logical unit (e.g., a Logical block, a Logical page, or a Logical sector) and a Physical unit (e.g., a Physical erase unit, a Physical program unit, a Physical sector) configured To the rewritable nonvolatile memory module 220. In other words, the storage controller 210 may find a physical unit mapped by a logical unit through the logical-to-physical address mapping table, and the storage controller 210 may find a logical unit mapped by a physical unit through the physical-to-logical address mapping table. However, the technical concepts related to the mapping of logical units and physical units are conventional in the art and will not be described herein.

In the present embodiment, the error checking and correcting circuit 214 is electrically connected to the processor 211 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the ECC and ECC circuit 214 generates an Error Correction Code (ECC) and/or an EDC (EDC) for data corresponding to the write command, and the processor 211 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 220. Thereafter, when the processor 211 reads data from the rewritable nonvolatile memory module 220, the corresponding error correction code and/or error check code is simultaneously read, and the error checking and correcting circuit 214 performs an error checking and correcting process on the read data according to the error correction code and/or error check code. In addition, after the error checking and correcting process, if the read data is successfully decoded, the error checking and correcting circuit 214 may return an error bit value to the processor 211.

In one embodiment, the storage controller 210 further comprises a buffer memory 216 and a power management circuit 217. The buffer memory is electrically connected to the processor 211 and is used for temporarily storing data and instructions from the host system 10, data from the rewritable nonvolatile memory module 220, or other system data for managing the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216. The power management circuit 217 is electrically connected to the processor 211 and is used for controlling the power of the memory device 20.

In the present embodiment, the reading voltage management circuit unit 215 includes an offset number calculation circuit 2151 and a reading voltage optimization circuit 2152. The read voltage management circuit unit 215 is used to manage the read voltages of a plurality of word lines. More specifically, the processor 211 selects one word line (also referred to as a target word line) of the plurality of word lines belonging to the plurality of physical units of the rewritable nonvolatile memory module 220 at a specific time point, and instructs the read voltage management circuit unit 215 to perform the read voltage optimization operation on the target word line. For example, processor 211 may be in (1) the absence of storage device 20 (i.e., storage device 20 is absent for more than a predetermined time threshold); (2) when the storage device is powered on; or (3) when the error bit number of the data read from a word line exceeds an error bit number threshold, selecting a target word line from all the word lines to perform the read voltage optimization operation. The processor 211 selects a word line in the word line group with a poor physical state (e.g., the word line group with a large erase count, a large read count, a long retention time, or a large number of error bits) as a target word line according to one or a combination of the statistical values and the number of error bits of all the word line groups. In addition, the processor 211 may also select the target word line according to the number of error bits returned by the error checking and correcting circuit 214. Specifically, when the bit error rate of data read from a word line exceeds a bit error rate threshold, the word line is set as the target word line. It should be noted that the selected target word line stores data, i.e., programmed data. In addition, if the read voltage optimization operation for a target word line is completed, the read voltage management circuit unit 215 can record the read voltage set corresponding to the target word line.

In one embodiment, the processor 211 may also randomly select a target word line for the read voltage optimization operation. In another embodiment, the processor 211 may also perform the read voltage optimization operation directly on each word line. In addition, by the read voltage optimization operation, the efficiency of the decoding operation can be improved.

The details of how the read voltage management circuit unit 215 performs the read voltage optimization operation and the functions of the offset number calculation circuit 2151 and the read voltage optimization circuit 2152 are described in detail below with reference to several drawings.

Fig. 2 is a flowchart illustrating a decoding method according to an embodiment of the present invention. Referring to fig. 1 and fig. 2, in step S21, the processor 211 selects a target word line of the word lines, wherein predetermined data is programmed into target memory cells of the target word line.

Assume that processor 211 is currently performing a read voltage optimization operation on one of the word line groups (also referred to as a target word line group). The processor 211 selects a target word line to be read voltage optimized. The target word line is selected from a plurality of word lines in the target word line group according to a specific selection condition. The specific selection condition includes (1) that a statistic of the target word line is close to an average of the statistics of all word lines in the word line group to which the target word line belongs; (2) the error bit number of the target word line is the minimum of all word lines in the word line group to which the target word line belongs; or (3) randomly selecting a word line as the target word line. The target word line stores preset data.

In the present embodiment, as mentioned above, the target word line stores the predetermined data. Specifically, the memory cells of each word line are programmed to store bit values corresponding to one of a plurality of different gray codes (Gray codes), and the total number of the gray codes is N, where N is a first predetermined positive integer greater than 2. In other words, the predetermined data stored in the memory cells of the target word line can have bit values corresponding to different gray codes (also called storage states).

In step S23, the read voltage management circuit unit 215 (or the offset count calculation circuit 2151) identifies a plurality of predetermined bit values stored in the target memory cells according to the predetermined data. Specifically, the preset data has a plurality of preset bit values. The predetermined bit values may include different storage states (also called Gray Code) that each of the memory cells of the rewritable nonvolatile memory module 220 can have. The following describes details of the golay codes with reference to fig. 3.

FIG. 3 is a diagram illustrating two different sets of read voltages and voltage differences therebetween according to an embodiment of the invention. Referring to FIG. 3, since the present embodiment is illustrated with a three-level memory cell NAND type flash memory module as an example, where N is equal to 8 (i.e., 2)³). Each memory cell of the three-level memory cell NAND type flash memory module has three Physical pages for respectively storing bit data, and each memory cell includes a Lower Physical Page (L), a Middle Physical Page (M) and an Upper Physical Page (U) which can respectively store one bit value. Assuming that the Threshold Voltage Distribution (Threshold Voltage Distribution) of the target memory cells storing the predetermined data is as shown in FIG. 3, the processor 211 can utilize the predetermined read Voltage V (1) of the set of predetermined read voltages V (1)₁～V(1)₇To accurately determine the stored bit state (also called bit value) of the target memory cells, i.e. determine the preset bit values of the preset data stored in the memory cells. The different predetermined bit values stored in the determined memory cells are divided into N Gray codes (storage states). The gate voltage in each target memory cell can be based on a predetermined read voltage V (1)₁～V(1)₇The code is 8 Gray codes such as "L: 1M:1U: 1", "L: 1M:1U: 0", "L: 1M:0U: 1", "L: 0M:0U: 0", "L: 0M:1U: 0" and "L: 0M:1U: 1" ("L:" indicates the bit value of the lower physical page; "M:" indicates the bit value of the middle physical page; "U:" indicates the upper physical page; "U:" indicates the bit value of the middle physical page; "U:" indicates the upper physical page: "indicates the lower physical page:" indicates the bit value of the lower physical pageBit value of a face). The 8 gray codes can also be represented as "111", "110", "100", "101", "001", "000", "010" and "011", 8 bit value combinations, wherein the sequential ordering of the bit values in each bit value combination is according to the order of the lower, middle and upper physical pages. That is, by applying the preset read voltages V (1) of different voltage values of the preset read voltage group V (1), respectively₁～V(1)₇To a memory cell of the target word line, the processor 211 determines whether the bit value (also called bit data or read bit value) stored in the memory cell corresponds to one of the plurality of different gray codes ("111", "110", "100", "101", "001", "000", "010" or "011") (i.e., identifies the type of the gray code stored in each target memory cell) according to whether the channel of the memory cell is turned on. For example, the read voltage V (1)₁Can distinguish Gray code '111' from Gray code '110' (reading voltage V (1)₁To the left is the threshold voltage distribution of the memory cell corresponding to the Gray code "111"; read voltage V (1)₁To the right of (1), is the threshold voltage distribution of the memory cell corresponding to the Gray code "110"). It should be noted that the memory cells of the rewritable nonvolatile memory module 220 may have a number of the plurality of gray codes (in this example, 8), and the number of the plurality of read voltages of each read voltage set is equal to the number of the plurality of gray codes minus one (in this example, 7, i.e., N-1-8-1-7).

It should be noted that N can be a predetermined positive integer (also referred to as a first predetermined positive integer) greater than 2 according to the type of the rewritable nonvolatile memory module 220. For example, if the rewritable nonvolatile memory module 220 is an MLC, N is 4; if the rewritable nonvolatile memory module 220 is SLC, N is 2; if the rewritable nonvolatile memory module 220 is QLC, N is 16.

It should be noted that, in the embodiment, the threshold voltage distributions of the memory cells of the target word line may be shifted from the predetermined threshold voltage distributions. Due to the shift of the threshold voltage distribution, the set of predetermined read voltages corresponding to the predetermined threshold voltages is no longer suitable for reading the word lines having the shifted threshold voltage distribution. The processor 211 needs to find a plurality of read voltages corresponding to the target word line, so that the read voltages can be close to the boundary of two adjacent threshold voltage distributions, and the found read voltages are combined into a read voltage set as an optimized read voltage set of the target word line. In this way, the plurality of read bit values obtained by reading the predetermined data stored in the target memory using the optimized read voltage set may approach the predetermined bit values.

Referring back to FIG. 2, after step S23 is completed, the reading voltage management circuit unit 215 (or the offset count calculation circuit 2151) can obtain all storage states included in the predetermined bit values stored in the target memory cells. In other words, the predetermined bit values of the predetermined data stored in the target memory cells may be one or more "111", one or more "110", one or more "100", one or more "101", one or more "001", one or more "000", one or more "010", and one or more "011". The predetermined bit value of the predetermined data may be preset by the processor 211 to be a fixed bit value, and the processor 211 writes the predetermined data into the target memory cells of the target word line before performing the read voltage optimization (e.g., writes the predetermined data into the target word line when the physical unit to which the target word line belongs is used to store the user data). In other words, the processor 211 (or the read voltage management circuit unit 215) may not need to perform a read operation, but may know the preset bit values of the preset data stored (programmed) in the target memory cells in advance, and may also know to correspondingly group the target memory cells into a plurality of target memory cell groups corresponding to different storage states (gray codes) according to the gray codes to which the stored preset bit values belong. For example, the manufacturer may preset the plurality of pre-bit values of the used preset data and record them into the read voltage management circuit unit 215. In one embodiment, the predetermined bit values (and corresponding target word lines) may be predetermined (and recorded) in firmware or software running processor 211. In another embodiment, the predetermined data may also be the user data stored in the target memory cells, and the user data is decoded successfully, so that the processor 211 (or the read voltage management circuit unit 215) can use the decoded user data to compare with the user data during reading (before decoding) to find the optimized read voltage set

Next, in step S25, the reading voltage management circuit unit 215 (or the offset number calculation circuit 2151) can read the plurality of target memory cells respectively using different X reading voltage sets to obtain X reading bit value sets respectively corresponding to the X reading voltage sets, and obtain X offset number sum sets by comparing the X reading bit value sets with the preset bit values, where X is a second predetermined positive integer. More specifically, the X read voltage groups are arranged in a first predetermined order, and a voltage difference value between two adjacent read voltage groups of the X read voltage groups is a first predetermined voltage difference, wherein each of the X read voltage groups has N-1 read voltages arranged according to a second predetermined order, and each of the X offset number sum groups has N-1 offset number sums arranged according to the second predetermined order. Further, an ith one of the X read bit value groups corresponds to an ith one of the X read voltage groups, an ith one of the X offset number sum groups corresponds to an ith one of the X read voltage groups, and a jth one of the ith offset number sum groups corresponds to a jth one of the N-1 read voltages of the ith read voltage group. Details of the X read voltage sets are illustrated below by fig. 3.

Referring to fig. 3, for example, assuming that N is 8, the first read voltage group V (1) is a first read voltage group (e.g., a predetermined read voltage group) of the X read voltage groups arranged according to a first sequence, and the second read voltage group V (2) is the X read voltage groupsWherein the first read voltage group V (1) has N-1 read voltages V (1) arranged according to a second order₁、V(1)₂、V(1)₃、V(1)₄、V(1)₅、V(1)₆、V(1)₇And the second read voltage group V (2) has 7 (i.e., N-1-8-1-7) read voltages V (2) arranged according to the second order₁、V(2)₂、V(2)₃、V(2)₄、V(2)₅、V(2)₆、V(2)₇. The voltage difference between the two adjacent read voltage sets is a first predetermined voltage difference (V)_offset). For example, the first read voltage V (2) of the second read voltage group₁A first read voltage V (1) corresponding to the first read voltage group₁The voltage difference between them is a first predetermined voltage difference (V)_offset) I.e. the read voltage V (2)₁Minus the read voltage V (1)₁Is equal to V_offset. In other words, for two adjacent read voltage groups of the X read voltage groups, the voltage differences between the read voltages arranged in the same order are all the first predetermined voltage differences V_offset。

In the present embodiment, in the above-mentioned operation of reading the target memory cells by using the different X read voltage sets respectively to obtain the X read bit value sets respectively corresponding to the X read voltage sets, the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) can select the ith read voltage set from the X read voltage sets, wherein the value of i is 1 to X according to the first predetermined sequence. Then, the reading voltage management circuit unit 215 (or the offset number calculation circuit 2151) respectively reads the target memory cells by using N-1 reading voltages in the ith reading voltage set, to obtain a plurality of read bit values of the Golay code corresponding to the ith read voltage group, wherein the plurality of read bit values is an ith read bit value set of the X read bit value sets that corresponds to the ith read voltage set, wherein a jth one of the N-1 read voltages in the ith read voltage group is used to distinguish a threshold voltage distribution corresponding to a jth one of the N Gray codes from a threshold voltage distribution corresponding to a j +1 th one of the N Gray codes, wherein j is 1 to N-1 according to the second predetermined sequence. After obtaining the corresponding set of read bits (and the plurality of read bits corresponding to the plurality of target memory cells therein) by reading the plurality of target memory cells using the X sets of read voltages, the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) may identify a plurality of read bit values of the plurality of target memory cells corresponding to the X sets of read voltages according to the X sets of read bits.

In the present embodiment, in the above-described operation of obtaining X offset number sum groups by comparing the X read bit value groups with the plurality of preset bit values, the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) performs the following steps (1) to (4).

Step (1): the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) divides the target memory cells into N target memory cell groups (e.g., G1-G8) respectively corresponding to N Gray codes according to the predetermined bit values, wherein the N Gray codes are sorted according to a third predetermined order (e.g., 1-8).

In particular, according to the plurality of preset bit values, the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) may divide all the target memory cells into a target memory cell group G1 with a stored preset bit value corresponding to the gray code "111", a target memory cell group G2 with a stored preset bit value corresponding to the gray code "110", a target memory cell group G3 with a stored preset bit value corresponding to the gray code "100", a target memory cell group G4 with a stored preset bit value corresponding to the gray code "101", a target memory cell group G5 with a stored preset bit value corresponding to the gray code "001", a target memory cell group G6 with a stored preset bit value corresponding to the gray code "000", a target memory cell group G7 with a stored preset bit value corresponding to the gray code "010", and a target memory cell group G8 with a stored preset bit value corresponding to the gray code "011".

Step (2): the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) selects an ith read bit value group of the X read bit value groups for an ith offset number sum group of the X offset number sum groups corresponding to an ith read voltage group, where the value of i is 1 to X in the first predetermined order, where the ith read bit value group is used to calculate the ith offset number sum group of the X offset number sum groups.

Specifically, to obtain each of the X offset number sum groups, e.g., an ith offset number sum group corresponding to an ith read voltage group. The reading voltage management circuit unit 215 (or the offset number calculation circuit 2151) correspondingly selects the ith reading bit value set, and identifies a plurality of reading bit values obtained by reading the target memory cells by the ith reading voltage set according to the ith reading bit value set.

And (3): the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) identifies, for a jth offset number sum corresponding to a jth read voltage of the ith read voltage group in the ith offset number sum group, a plurality of first target memory cells divided into a jth target memory cell group of the N target memory cell groups and a plurality of second target memory cells divided into a (j + 1) th target memory cell group of the N target memory cell groups, wherein the jth read voltage is used to distinguish a threshold voltage distribution of the jth target memory cell group corresponding to a jth gray code of the N gray codes from a threshold voltage distribution of the (j + 1) th target memory cell group corresponding to a j +1 th gray code of the N gray codes.

Specifically, in order to obtain a value of each offset number sum in the jth read voltage of the ith read voltage group, that is, the jth offset number sum of the jth read voltage corresponding to the ith read voltage group. The read voltage management circuit unit 215 (or the offset count calculation circuit 2151) identifies two target memory cell groups and target memory cells of two Golay codes distinguished by a jth read voltage.

For example, assume that N is 8, i is 1, and j is 2, i.e., for the 2 nd read voltage V (1) of the 1 st offset number sum group corresponding to the 1 st (i is 1) read voltage group V (1)₂2 nd (j ═ 2) offset number sum S (1)₂. The read voltage management circuit unit 215 (or the offset number calculation circuit 2151) first identifies the voltage V (1) to be read₂A first plurality of target cells in the divided target cell group G2 (i.e., divided into the 2 nd target cell group of the 8 target cell groups) and a second plurality of target cells in the target cell group G3 (i.e., divided into the 3 rd (j +1 ═ 3) target cell group of the 8 target cell groups).

Then, the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) performs step (4): the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) identifies a first read bit value of the first target memory cells of the jth target memory cell set and a second read bit value of the second target memory cells of the (j + 1) th target memory cell set according to the ith read bit value set.

For example, following the above example, the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) identifies a plurality of read bit values (also referred to as first read bit values) of a plurality of first target memory cells in the target memory cell group G2 and a plurality of read bit values (also referred to as second read bit values) of a plurality of second target memory cells in the target memory cell group G3.

Subsequently, step (5): the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) identifies, according to the first read bit values, that a number of third read bit values belonging to the j +1 th golay code among the first read bit values is a first offset number, and identifies, according to the second read bit values, that a number of fourth read bit values belonging to the j-th golay code among the second read bit values is a second offset number.

Specifically, ideally, the storage states of the first read bit values of the first target memory cells of the target memory cell group G2 should all belong to the 2 nd Gray code "110" of the N Gray codes (i.e., the predetermined storage state/predetermined read bit value of the first target memory cells should be "110"). If the storage status of the third read bit values in the first read bit values belongs to the 3 rd gray code "100" of the N gray codes, the number of the third read bit values (the number of the first target memory cells storing the third read bit values) is identified as a first offset number, which is used to indicate the number of target memory cells in the first target memory cells in which a first offset (i.e., the offset of the storage status from the predetermined storage status to the "right") occurs. As shown in FIG. 4, the first offset number for the 2 nd read voltage corresponding to the 1 st read voltage group can again be "C (1)_G2G3"indicates, wherein" (1) "indicates that the corresponding 1 st read voltage group," G2G3 "indicates the shift from the default storage state of the corresponding target cell group G2 to the storage state of the corresponding target cell group G3. In addition, it can be understood from "G2G 3" that the corresponding read voltage is the 2 nd read voltage in the read voltage group for distinguishing the storage state of the target cell group G2 from the storage state of the target cell group G3, and the sequence of "G2" and "G3" in the "G2G 3" can also indicate that the direction of the offset is from G2 to G3, i.e., the first offset direction from left to right.

Similarly, ideally, the storage statuses of the second read bit values of the second target memory cells of the target memory cell group G3 should all belong to the 3 rd Gray code "100" of the N Gray codes (i.e., the default storage status/default read bit value of the second target memory cells should be "100"). If the storage status of a plurality of fourth read bit values in the plurality of second read bit values belongs to the 2 nd Gray code of the N Gray codes of 110, the number of the fourth read bit valuesThe destination (the number of the second target memory cells storing the fourth read bit values) is identified as a second offset number, which is used to indicate the number of target memory cells in the second target memory cells having a second offset (i.e. the storage state is shifted from the predetermined storage state to the left). As shown in FIG. 4, the second offset number for the 2 nd read voltage corresponding to the 1 st read voltage group can again be "C (1)_G3G2"indicates, wherein" (1) "indicates that the corresponding 1 st set of read voltages," G3G2 "indicates a shift from the default storage state of the corresponding target set of memory cells G3 to the storage state of the corresponding target set of memory cells G2. In addition, it can be understood from "G3G 2" that the corresponding read voltage is the 2 nd read voltage in the read voltage group for distinguishing the storage state of the target cell group G3 from the storage state of the target cell group G2, and the sequence of "G3" and "G2" in the "G3G 2" can also indicate that the direction of the offset is from G3 to G2, i.e., the second offset direction from right to left.

And (6): the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) calculates a sum of the first offset number and the second offset number to be a jth offset number sum among the N-1 offset number sums of the ith offset number sum group.

Continuing with the above example, the read voltage management circuit unit 215 (or offset number calculation circuit 2151) sums up the corresponding read voltages V (1)₂First offset number C (1)_G2G3With a second offset number C (1)_G3G2The obtained sum value is used as the 2 nd offset number summation S (1) in the N-1 offset number summations of the 1 st offset number summation group₂。

By analogy, the read voltage management circuit unit 215 (or the offset number calculation circuit 2151) can obtain the 1 st read voltage V (1) corresponding to the 1 st read voltage group via the obtained 1 st read voltage V (1)₁First offset number C (1)_G1G2With a second offset number C (1)_G2G1To calculate the 1 st offset number total of the N-1 offset number total of the 1 st offset number total groupAnd S (1)₁(ii) a Via the obtained 3 rd read voltage V (1) corresponding to the 3 rd read voltage group₃First offset number C (1)_G3G4With a second offset number C (1)_G4G3To calculate a 3 rd offset number summation S (1) of said N-1 offset number summations of said 1 st offset number summation group₃(ii) a Via the obtained 4 th read voltage V (1) corresponding to the 1 st read voltage group₄First offset number C (1)_G4G5With a second offset number C (1)_G5G4To calculate a 4 th offset number sum S (1) of said N-1 offset number sums of said 1 st offset number sum group₄(ii) a Via the obtained 5 th read voltage V (1) corresponding to the 1 st read voltage group₅First offset number C (1)_G5G6With a second offset number C (1)_G6G5To calculate a 5 th offset number sum S (1) of said N-1 offset number sums of said 1 st offset number sum group₅(ii) a Via the obtained 6 th read voltage V (1) corresponding to the 1 st read voltage group₆First offset number C (1)_G6G7With a second offset number C (1)_G7G6To calculate the 1 st offset number summation S (1) of said N-1 offset number summations of said 1 st offset number summation group₆(ii) a Via the obtained 7 th read voltage V (1) corresponding to the 1 st read voltage group₇First offset number C (1)_G7G8With a second offset number C (1)_G8G7To calculate the 7 th offset number summation S (1) of the N-1 offset number summations of the 1 st offset number summation group₇. In this way, all of the N-1 offset number summations of the 1 st offset number summation group are obtained. Then, the X total offset numbers can be obtained according to the above steps, and are not described herein again.

The direction of the first offset (also referred to as positive offset) is a positive voltage direction (e.g., to the right "→"), and the direction of the second offset (also referred to as negative offset) is a negative voltage direction (e.g., to the left "←").

FIG. 5 is a block diagram of an embodiment of the present inventionA schematic diagram of a statistical table recording the sum of the offset numbers. Referring to FIG. 5, in the present embodiment, the processor 211 records the X total offset number sets of the target memory cells in the same manner as a statistical table 510. Wherein, according to a second predetermined sequence, the 1 st read voltage V (i) of the ith read voltage group of the X read voltage groups₁All 1 st offset number sums S (1) corresponding to the X offset number sum groups₁～S(X)₁(ii) a 2 nd read voltage V (i)₂All 2 nd offset number sums S (1) corresponding to the X offset number sum groups₂～S(X)₂(ii) a Read voltage No. 3V (i)₃All 3 rd offset number sums S (1) corresponding to the X offset number sum groups₃～S(X)₃(ii) a 4 th read voltage V (i)₄All 4 th offset number sums S (1) corresponding to the X offset number sum groups₄～S(X)₄(ii) a Read voltage No. 5V (i)₅All the 5 th offset number sums S (1) corresponding to the X offset number sum groups₅～S(X)₅(ii) a 6 th read Voltage V (i)₆All the 6 th offset number sums S (1) corresponding to the X offset number sum groups₆～S(X)₆(ii) a 7 th read Voltage V (i)₇All 7 th offset number sums S (1) corresponding to the X offset number sum groups₇～S(X)₇。

Referring back to FIG. 2, after completing step S25, in step S27, the read voltage management circuit unit 215 (or the read voltage optimizer circuit 2152) determines N-1 optimized read voltages of an optimized set of read voltages according to the X offset number sum set, where N is a first predetermined positive integer greater than 2.

Specifically, according to the obtained X offset number sum groups, the read voltage management circuit unit 215 (or the read voltage optimization circuit 2152) identifies X jth offset number sums among all X offset number sum groups, taking the minimum of the X jth offset number sums as a target jth offset number sum; and determining a read voltage corresponding to the target jth offset number sum as a jth optimized read voltage of the N-1 optimized read voltages of the optimized read voltage group.

For example, to find the 1 st (j ═ 1) optimal read voltage of the N-1 (N ═ 8) optimal read voltages of the optimal set of read voltages, the read voltage management circuit unit 215 (or read voltage optimization circuit 2152) identifies all the 1 st offset number sums S (1) in all the X offset number sum groups₁～S(X)₁And summing the 1 st offset number S (1)₁～S(X)₁The smallest of these is taken as the "target 1 st offset number sum". Suppose that the 1 st offset number sum S (1)₁～S(X)₁The smallest of them is the 1 st offset number sum S (3) of the 3 rd (i ═ 3) offset number sum group₁Then the target 1 st offset sum is determined as the 1 st offset sum S (3) of the 3 rd offset sum group₁. In addition, the read voltage management circuit unit 215 (or the read voltage optimization circuit 2152) determines the "target 1 st offset sum S (3)₁"corresponding read voltage V (3)₁Is the 1 st optimized read voltage of the N-1 optimized read voltages of the optimized set of read voltages. By analogy, the read voltage management circuit unit 215 (or the read voltage optimization circuit 2152) can find all the optimized read voltages (the 1 st to 7 th optimized read voltages) of the optimized set of read voltages according to the X offset number sum sets.

In an embodiment, if the number of the minimum of the X jth offset number sums is greater than 1, the step of setting the minimum of the X jth offset number sums as the target jth offset number sum includes: (1) selecting any jth offset number sum from all the smallest of the X jth offset number sums as the target jth offset number sum; selecting a jth offset number sum arranged in the middle as the X jth offset number sums according to the first predetermined order from all the smallest of the jth offset number sumsThe target jth offset number sum. For example, if the 1 st offset sum S (1)₁～S(X)₁The smallest of them is S (1)₁、S(2)₁And S (3)₁Then the read voltage management circuit unit 215 (or the read voltage optimization circuit 2152) can randomly select the 1 st offset sum S (1)₁、S(2)₁、S(3)₁As a target 1 st offset number sum (the above (1)); or the read voltage management circuit unit 215 (or the read voltage optimization circuit 2152) can select the 1 st offset number sum S (1)₁、S(2)₁、S(3)₁The middle of (1), i.e., the 1 st offset number sum S (2)₁As a target 1 st offset number sum (above (2)).

In summary, the decoding method and the storage controller provided by the embodiments of the invention can perform the read voltage optimization operation corresponding to the target word line on the target word line by using the preset data stored in the target word line. In the read voltage optimization operation, the memory controller calculates a plurality of offset number banks based on the preset data and a plurality of read bit banks obtained by reading the target word line using a plurality of different read voltage banks to determine a plurality of optimized read voltages corresponding to the optimized read voltage bank of the target word line based on the plurality of offset number banks. In this way, the optimum read voltage set for reading the target word line can be efficiently and quickly found, thereby improving the accuracy of the data read therefrom and improving the overall efficiency of the decoding operation for the read operation.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A decoding method for a memory device configured with a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of word lines, each of the word lines includes a plurality of memory cells, wherein each of the memory cells is programmed to store a bit value corresponding to one of a plurality of different gray codes, and a total number of the plurality of gray codes is N, where N is a first predetermined positive integer greater than 2, the method comprising:

selecting a target word line of the plurality of word lines, wherein preset data is programmed into a plurality of target memory cells of the target word line;

identifying a plurality of preset bit values stored in the target memory cells according to the preset data;

reading the plurality of target memory cells with different X read voltage sets respectively to obtain X read bit value sets respectively corresponding to the X read voltage sets, and obtaining X offset number sum sets by comparing the X read bit value sets with the preset bit values, wherein X is a second predetermined positive integer, the X read voltage sets are arranged in a first predetermined order, and a voltage difference between two adjacent ones of the X read voltage sets is a first predetermined voltage difference, wherein each of the X read voltage sets has N-1 read voltages arranged according to a second predetermined order, and each of the X offset number sum sets has N-1 offset number sums arranged according to the second predetermined order,

wherein an ith one of the X read bit value groups corresponds to an ith one of the X read voltage groups, an ith one of the X offset number sum groups corresponds to an ith one of the X read voltage groups, and a jth one of the ith offset number sum groups corresponds to a jth one of the N-1 read voltages of the ith read voltage group; and

determining N-1 optimized read voltages of the set of optimized read voltages according to the X set of offset sums,

wherein the step of determining N-1 optimal read voltages of the set of optimal read voltages according to the X total offset numbers comprises: identifying X jth offset number sums in all X offset number sum groups, taking the smallest of the X jth offset number sums as a target jth offset number sum; and determining a read voltage corresponding to the target jth offset number sum as a jth optimized read voltage of the N-1 optimized read voltages of the optimized read voltage group.

2. The decoding method as described in claim 1, wherein the step of reading the plurality of target memory cells with different sets of the X read voltages respectively to obtain sets of X read bit values respectively corresponding to the sets of the X read voltages comprises:

selecting an ith read voltage group from the X read voltage groups, wherein the value of i is from 1 to X according to the first predetermined sequence; and

reading the target memory cells by using N-1 reading voltages in the ith reading voltage group respectively to obtain a plurality of reading bit values corresponding to the ith reading voltage group and distinguished as the plurality of Golay codes, wherein the plurality of reading bit values are the ith reading bit value group corresponding to the ith reading voltage group in the X reading bit value groups, a jth reading voltage in the N-1 reading voltages in the ith reading voltage group is used for distinguishing a threshold voltage distribution corresponding to the jth Golay code in the N Golay codes from a threshold voltage distribution corresponding to the j +1 Golay code in the N Golay codes, and j is from 1 to N-1 according to the second predetermined sequence.

3. The decoding method of claim 2, wherein the step of obtaining X total sets of offset numbers by comparing the X sets of read bit values with the plurality of preset bit values comprises:

dividing the target memory cells into N target memory cell groups respectively corresponding to N Gray codes according to the preset bit values, wherein the N Gray codes are sorted according to a third preset sequence 1-N;

selecting an ith one of the X read bit value groups for an ith one of the X offset number sum groups corresponding to the ith read voltage group, wherein the value of i is 1 to X in the first predetermined order, wherein the ith read bit value group is used to calculate the ith one of the X offset number sum groups;

identifying a plurality of first target memory cells divided into a jth target memory cell set of the N target memory cell sets and a plurality of second target memory cells divided into a (j + 1) th target memory cell set of the N target memory cell sets for a jth offset number sum of a jth read voltage corresponding to the ith read voltage set in the ith offset number sum set, wherein the jth read voltage is used to distinguish a threshold voltage distribution of the jth target memory cell set corresponding to a jth one of the N gray codes from a threshold voltage distribution of the (j + 1) th target memory cell set corresponding to a (j + 1) th one of the N gray codes;

identifying a plurality of first read bit values of the first target memory cells of the jth target memory cell set and a plurality of second read bit values of the second target memory cells of the (j + 1) th target memory cell set according to the ith read bit value set;

identifying a number of third read bit values belonging to the j +1 th Golay code of the plurality of first read bit values as a first offset number according to the plurality of first read bit values, and identifying a number of fourth read bit values belonging to the j-th Golay code of the plurality of second read bit values as a second offset number according to the plurality of second read bit values; and

calculating a sum of the first offset number and the second offset number to serve the sum as a jth offset number sum of the N-1 offset number sums for the ith offset number sum group.

4. The decoding method of claim 3, wherein if the number of the smallest of the X jth offset number sums is greater than 1, the step of setting the smallest of the X jth offset number sums as the target jth offset number sum comprises:

selecting any jth offset number sum from all the smallest of the X jth offset number sums as the target jth offset number sum; or

Selecting a jth offset number sum arranged in the middle as the target jth offset number sum according to the first predetermined order from all the smallest of the jth offset number sums of the X.

5. A storage controller for controlling a storage device configured with a rewritable non-volatile memory module, the storage controller comprising:

the connection interface circuit is used for electrically connecting to a host system;

a memory interface control circuit electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of word lines, each of the word lines includes a plurality of memory cells, each of the memory cells is programmed to store a bit value corresponding to one of a plurality of different gray codes, and the total number of the plurality of gray codes is N, where N is a first predetermined positive integer greater than 2;

a read voltage management circuit unit; and

a processor electrically connected to the connection interface circuit, the memory interface control circuit and the read voltage management circuit unit,

wherein the processor selects a target word line of the plurality of word lines and instructs the read voltage management circuit unit to perform a read voltage optimization operation corresponding to the target word line, wherein preset data has been programmed into a plurality of target memory cells of the target word line,

the read voltage management circuit unit is used for identifying a plurality of preset bit values stored in the target memory cells according to the preset data;

the read voltage management circuit unit is further configured to read the plurality of target memory cells with different X read voltage sets respectively to obtain X read bit value sets respectively corresponding to the X read voltage sets, and obtain X offset number sum sets by comparing the X read bit value sets with the preset bit values, wherein X is a second predetermined positive integer, the X read voltage sets are arranged in a first predetermined order, and a voltage difference value between two adjacent ones of the X read voltage sets is a first predetermined voltage difference, wherein each of the X read voltage sets has N-1 read voltages arranged according to a second predetermined order, and each of the X offset number sum sets has N-1 offset number sums arranged according to the second predetermined order,

the read voltage management circuit unit is further configured to determine N-1 optimized read voltages of an optimized set of read voltages according to the X offset number sum group,

wherein in the above-described operation of deciding the N-1 optimized read voltages of the optimized read voltage group according to the X offset number sum groups, the read voltage management circuit unit identifies X jth offset number sums among all X offset number sum groups, and takes the minimum of the X jth offset number sums as a target jth offset number sum; and the reading voltage management circuit unit judges that the reading voltage corresponding to the target jth offset number sum is the jth optimized reading voltage in the N-1 optimized reading voltages of the optimized reading voltage group.

6. The storage controller of claim 5, wherein in said reading said plurality of target memory cells with different sets of said X read voltages to obtain sets of X read bit values corresponding to said sets of X read voltages,

the reading voltage management circuit unit selects an ith reading voltage group in the X reading voltage groups, wherein the numerical value of i is 1 to X according to the first preset sequence; and

the reading voltage management circuit unit respectively reads the target memory cells by using N-1 reading voltages in the ith reading voltage group to obtain a plurality of reading bit values corresponding to the ith reading voltage group and divided into the plurality of Golay codes, wherein the plurality of reading bit values are the ith reading bit value group corresponding to the ith reading voltage group in the X reading bit value groups, the jth reading voltage in the N-1 reading voltages in the ith reading voltage group is used for dividing the threshold voltage distribution corresponding to the jth Golay code in the N Golay codes and the threshold voltage distribution corresponding to the j +1 Golay code in the N Golay codes, and j is 1 to N-1 according to the second predetermined sequence.

7. The storage controller of claim 6, wherein in said operation of obtaining a total set of X offset numbers by comparing said set of X read bit values to said plurality of preset bit values,

the reading voltage management circuit unit divides the target memory cells into N target memory cell groups respectively corresponding to N Gray codes according to the preset bit values, wherein the N Gray codes are sorted according to a third preset sequence 1-N;

the read voltage management circuit unit selects an ith read bit value group of the X read bit value groups for an ith offset number sum group of the X offset number sum groups corresponding to an ith read voltage group, wherein the value of i is 1 to X in the first predetermined order, wherein the ith read bit value group is used to calculate the ith offset number sum group of the X offset number sum groups;

the read voltage management circuit unit identifies a plurality of first target memory cells divided into a jth target memory cell group of the N target memory cell groups and a plurality of second target memory cells divided into a (j + 1) th target memory cell group of the N target memory cell groups for a jth offset number sum of a jth read voltage corresponding to the ith read voltage group in the ith offset number sum group, wherein the jth read voltage is used for distinguishing a threshold voltage distribution of the jth target memory cell group corresponding to a jth gray code of the N gray codes from a threshold voltage distribution of the (j + 1) th target memory cell group corresponding to a j +1 th gray code of the N gray codes;

the read voltage management circuit unit identifies a plurality of first read bit values of the first target memory cells of the jth target memory cell set and a plurality of second read bit values of the second target memory cells of the (j + 1) th target memory cell set according to the ith read bit value set;

the read voltage management circuit unit identifies a number of third read bit values belonging to the j +1 th Golay code in the first read bit values as a first offset number according to the first read bit values, and identifies a number of fourth read bit values belonging to the j Gray code in the second read bit values as a second offset number according to the second read bit values; and

the read voltage management circuit unit calculates a sum of the first offset number and the second offset number to be a jth offset number sum among the N-1 offset number sums of the ith offset number sum group.

8. The storage controller of claim 7, wherein if the number of said smallest of said X jth offset number sums is greater than 1, in said operation of taking said smallest of said X jth offset number sums as said target jth offset number sum,

the read voltage management circuit unit selects any one jth offset number sum from all the smallest of the X jth offset number sums as the target jth offset number sum; or

The read voltage management circuit unit selects one jth offset number sum arranged in the middle as the target jth offset number sum according to the first predetermined order from all the smallest of the X jth offset number sums.