CN112099727B - Data writing method, memory control circuit unit and memory storage device - Google Patents

Data writing method, memory control circuit unit and memory storage device Download PDF

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Publication number
CN112099727B
CN112099727B CN201910526180.XA CN201910526180A CN112099727B CN 112099727 B CN112099727 B CN 112099727B CN 201910526180 A CN201910526180 A CN 201910526180A CN 112099727 B CN112099727 B CN 112099727B
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data
sub
memory
physical
physically
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CN112099727A (en
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叶志刚
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065—Replication mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention provides a data writing method, a memory control circuit unit and a memory storage device. The method comprises the following steps: writing the first data and the second data into the first entity erasing unit. Copying the first data from the first physically erased cell to the second physically erased cell; and copying the second data from the first entity-erased cells to third entity-erased cells, wherein the memory sub-module to which the second entity-erased cells belong is different from the memory sub-module to which the third entity-erased cells belong.

Description

Data writing method, memory control circuit unit and memory storage device
Technical Field
The invention relates to a data writing method, a memory control circuit unit and a memory storage device.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
Generally, a rewritable non-volatile memory module may include a plurality of memory sub-modules. Each memory sub-module has a plurality of wordlines, and the memory cells on each wordline may form a plurality of physical pages for storing data. The plurality of physical pages formed by the memory cells on the same word line may also be referred to as a physical page group.
Generally, to write to multiple memory sub-modules simultaneously, the buffer memory requires more space to store data from the host system. For example, if the rewritable non-volatile memory module supports simultaneous (or parallel) writing to three memory sub-modules, the buffer memory needs to have a space of size of three physical page groups. When data from the host system fills the space of the size of the three physical page groups in the buffer memory, the memory management circuitry will simultaneously write data from the host system from the buffer memory into the three memory sub-modules. And assuming that the data is to be read, the memory management circuitry may read the data from the three memory sub-modules simultaneously (or in parallel). However, this approach requires a large amount of buffer memory space for the reason that multiple memory sub-modules are written simultaneously.
Disclosure of Invention
The invention provides a data writing method, a memory control circuit unit and a memory storage device, which can reduce the space required by a buffer memory and can keep the technical effect of reading data in a plurality of memory sub-modules in parallel.
The invention provides a data writing method, which is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of memory sub-modules, each memory sub-module in the plurality of memory sub-modules comprises a plurality of entity erasing units, and the data writing method comprises the following steps: obtaining a plurality of data from a host system and temporarily storing the data in a buffer memory; writing a first data and a second data of the plurality of data temporarily stored in the buffer memory into a first solid erasing unit in the plurality of memory sub-modules; copying the first data from the first physically erased cell to a second physically erased cell; and copying the second data from the first physically-erased cell to a third physically-erased cell, wherein the memory sub-module to which the second physically-erased cell belongs is different from the memory sub-module to which the third physically-erased cell belongs.
In an embodiment of the invention, the plurality of memory sub-modules are respectively connected to a memory control circuit unit through a plurality of channels, and the memory control circuit unit reads the plurality of memory sub-modules in parallel through the plurality of channels.
In an embodiment of the invention, in the step of writing the first data and the second data of the plurality of data temporarily stored in the buffer memory into the first physically erased cells in the plurality of memory sub-modules, the writing of the first data and the writing of the second data are completed in the same write operation.
In an embodiment of the invention, the plurality of data are arranged according to a sequence in the host system, the first data includes a first subdata and a second subdata, and the second data includes a third subdata and a fourth subdata. Wherein copying the first data from the first physically erased cell to the second physically erased cell comprises: and sequentially writing the first subdata and the second subdata into a first entity page and a second entity page in the second entity erasing unit respectively. Wherein copying the second data from the first physically erased cell to the third physically erased cell comprises: and sequentially writing the third subdata and the fourth subdata into a third physical page and a fourth physical page in the third physical erasing unit respectively. Wherein the first sub-data and the second sub-data are consecutive, the second sub-data and the third sub-data are consecutive, and the third sub-data and the fourth sub-data are consecutive in the sequence of the plurality of data.
In an embodiment of the invention, the plurality of data are arranged in the host system according to an order, the first data includes a fifth sub-data and a sixth sub-data, and the second data includes a seventh sub-data and an eighth sub-data. Wherein copying the first data from the first physically erased cell to the second physically erased cell comprises: and sequentially writing the fifth sub-data and the sixth sub-data into a fifth physical page and a sixth physical page in the second physical erasing unit, respectively. Wherein copying the second data from the first physically erased cell to the third physically erased cell comprises: and sequentially writing the seventh sub-data and the eighth sub-data into a seventh physical page and an eighth physical page in the third physical erasing unit, respectively. In the sequence of the plurality of data, the fifth sub-data and the seventh sub-data are consecutive, the sixth sub-data and the seventh sub-data are consecutive, and the sixth sub-data and the eighth sub-data are consecutive.
In an embodiment of the present invention, the method further includes: marking a first physical page set in the first physical erase unit for storing the first data and the second data by using a first bit value; marking a second physical page set for storing the first data in the second physical erasing unit by using a second bit value; and marking a third entity page group used for storing the second data in the third entity erasing unit by using the second bit value.
In one embodiment of the present invention, the step of copying the first data from the first physically erased cell to the second physically erased cell and the step of copying the second data from the first physically erased cell to the third physically erased cell are performed while at least one of a valid data merge operation and an average wear operation is performed.
The invention provides a memory control circuit unit, which is used for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of memory sub-modules, each memory sub-module in the plurality of memory sub-modules comprises a plurality of entity erasing units, and the memory control circuit unit comprises: a host interface, a memory interface, and memory management circuitry. The host interface is used for electrically connecting to a host system. The memory interface is used for electrically connecting to the rewritable nonvolatile memory module, and the plurality of memory sub-modules are respectively electrically connected to the memory interface. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for executing the following operations: obtaining a plurality of data from a host system and temporarily storing the data in a buffer memory; writing a first data and a second data of the plurality of data temporarily stored in the buffer memory into a first solid erasing unit in the plurality of memory sub-modules; copying the first data from the first physically erased cell to a second physically erased cell; and copying the second data from the first physically-erased cell to a third physically-erased cell, wherein the memory sub-module to which the second physically-erased cell belongs is different from the memory sub-module to which the third physically-erased cell belongs.
In an embodiment of the invention, the plurality of memory sub-modules are respectively connected to the memory management circuit through a plurality of channels, and the memory management circuit reads the plurality of memory sub-modules in parallel through the plurality of channels.
In an embodiment of the invention, in the operation of writing the first data and the second data of the plurality of data temporarily stored in the buffer memory into the first physically erased cells in the plurality of memory sub-modules, the writing of the first data and the writing of the second data are completed in the same write operation.
In an embodiment of the invention, the plurality of data are arranged according to a sequence in the host system, the first data includes a first subdata and a second subdata, and the second data includes a third subdata and a fourth subdata. The memory management circuit is further configured to sequentially write the first sub-data and the second sub-data into a first physical page and a second physical page of the second physical erase unit, respectively, in an operation of copying the first data from the first physical erase unit to the second physical erase unit. The memory management circuit is further configured to sequentially write the third sub-data and the fourth sub-data into a third physical page and a fourth physical page in the third physical erase unit, respectively, in an operation of copying the second data from the first physical erase unit to the third physical erase unit. In the sequence of the plurality of data, the first sub-data and the second sub-data are continuous, the second sub-data and the third sub-data are continuous, and the third sub-data and the fourth sub-data are continuous.
In an embodiment of the invention, the plurality of data are arranged in the host system according to an order, the first data includes a fifth sub-data and a sixth sub-data, and the second data includes a seventh sub-data and an eighth sub-data. The memory management circuit is further configured to sequentially write the fifth sub-data and the sixth sub-data into a fifth physical page and a sixth physical page of the second physical erase unit, respectively, in an operation of copying the first data from the first physical erase unit to the second physical erase unit. The memory management circuit is further configured to sequentially write the seventh sub-data and the eighth sub-data into a seventh physical page and an eighth physical page in the third physical erase unit, respectively, in an operation of copying the second data from the first physical erase unit to the third physical erase unit. Wherein the fifth sub-data and the seventh sub-data are consecutive, the sixth sub-data and the seventh sub-data are consecutive, and the sixth sub-data and the eighth sub-data are consecutive in the sequence of the plurality of data.
In an embodiment of the invention, the memory management circuit is further configured to mark a first physical page set in the first physical erase unit for storing the first data and the second data with a first bit value. The memory management circuit is further configured to mark a second set of physical pages in the second physical erase unit for storing the first data with a second bit value. The memory management circuit is further configured to mark a third set of physical pages in the third physical erase unit for storing the second data using the second bit value.
In one embodiment of the present invention, the memory management circuit is further configured to copy the first data from the first physically erased cell to the second physically erased cell and copy the second data from the first physically erased cell to the third physically erased cell when performing at least one of a valid data merge operation and an average wear operation.
The invention provides a memory storage device, comprising: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of memory sub-modules, and each memory sub-module in the plurality of memory sub-modules comprises a plurality of entity erasing units. And the memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module, and the plurality of memory sub-modules are respectively and electrically connected to the memory control circuit unit. The memory control circuit unit is used for executing the following operations: obtaining a plurality of data from a host system and temporarily storing the data in a buffer memory; writing a first data and a second data of the plurality of data temporarily stored in the buffer memory into a first solid erasing unit in the plurality of memory sub-modules; copying the first data from the first physically erased cell to a second physically erased cell; and copying the second data from the first physically-erased cell to a third physically-erased cell, wherein the memory sub-module to which the second physically-erased cell belongs is different from the memory sub-module to which the third physically-erased cell belongs.
In an embodiment of the invention, the plurality of memory sub-modules are respectively connected to a memory control circuit unit through a plurality of channels, and the memory control circuit unit reads the plurality of memory sub-modules in parallel through the plurality of channels.
In an embodiment of the invention, in the operation of writing the first data and the second data of the plurality of data temporarily stored in the buffer memory into the first physically erased cells in the plurality of memory sub-modules, the writing of the first data and the writing of the second data are completed in the same write operation.
In an embodiment of the present invention, the plurality of data are arranged in the host system according to a sequence, the first data includes a first sub-data and a second sub-data, and the second data includes a third sub-data and a fourth sub-data. The memory control circuit unit is further configured to sequentially write the first sub-data and the second sub-data into a first physical page and a second physical page of the second physical erase unit, respectively, in an operation of copying the first data from the first physical erase unit to the second physical erase unit. The memory control circuit unit is further configured to sequentially write the third subdata and the fourth subdata into a third physical page and a fourth physical page in the third physical erase unit during the operation of copying the second data from the first physical erase unit to the third physical erase unit. Wherein the first sub-data and the second sub-data are consecutive, the second sub-data and the third sub-data are consecutive, and the third sub-data and the fourth sub-data are consecutive in the sequence of the plurality of data.
In an embodiment of the invention, the plurality of data are arranged according to an order in the host system, the first data includes a fifth sub-data and a sixth sub-data, and the second data includes a seventh sub-data and an eighth sub-data. The memory control circuit unit is further configured to sequentially write the fifth sub-data and the sixth sub-data into a fifth physical page and a sixth physical page of the second physical erase unit, respectively, in an operation of copying the first data from the first physical erase unit to the second physical erase unit. The memory control circuit unit is further configured to sequentially write the seventh sub-data and the eighth sub-data into a seventh physical page and an eighth physical page in the third physical erase unit, respectively, in an operation of copying the second data from the first physical erase unit to the third physical erase unit. Wherein the fifth sub-data and the seventh sub-data are consecutive, the sixth sub-data and the seventh sub-data are consecutive, and the sixth sub-data and the eighth sub-data are consecutive in the sequence of the plurality of data.
In an embodiment of the invention, the memory control circuit unit is further configured to mark a first physical page set in the first physical erase unit for storing the first data and the second data with a first bit value. The memory control circuit unit is further configured to mark a second physical page set in the second physical erase unit for storing the first data with a second bit value. The memory control circuit unit is further configured to mark a third physical page set in the third physical erase unit for storing the second data using the second bit value.
In an embodiment of the present invention, the memory control circuit unit is further configured to perform the operations of copying the first data from the first physically erased cell to the second physically erased cell and copying the second data from the first physically erased cell to the third physically erased cell when at least one of a valid data merge operation and an average wear operation is performed.
Based on the above, the data writing method, the memory control circuit unit and the memory storage device of the invention can reduce the space required by the buffer memory and can keep the technical effect of reading the data in a plurality of memory sub-modules in parallel.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a schematic block diagram of a rewritable nonvolatile memory module according to a first exemplary embodiment of the present invention;
FIG. 7 is a flowchart illustrating a data writing method according to an example embodiment of the present invention;
FIGS. 8A-8B are diagrams illustrating an example of a data writing method according to a first embodiment of the present invention;
fig. 9 is a diagram illustrating an example of a data writing method according to a second embodiment of the invention.
Description of the reference numerals
30. 10: memory storage device
31. 11: host system
110: system bus
111: processor with a memory having a plurality of memory cells
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: main machine board
201: u disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with a keyboard body
209: screen
210: horn type loudspeaker
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
404: memory control circuit unit
406: rewritable nonvolatile memory module
502: memory management circuit
504: host interface
506: memory interface
508: error checking and correcting circuit
510: buffer memory
512: power management circuit
310: first memory sub-module
320: second memory sub-module
330: third memory sub-module
340: fourth memory sub-module
316. 326, 336, 346: data bus
410(0) - (410 (N), 420(0) - (420 (N), 430(0) - (430 (N), 440(0) - (440 (N)): physical erase unit
S701: the method comprises the steps of obtaining a plurality of data from a host system and temporarily storing the data in a buffer memory
S703: writing the first data and the second data of the plurality of data temporarily stored in the buffer memory into the first physically erased unit in the plurality of memory sub-modules
S705: copying the first data from the first physically erased cell to the second physically erased cell
S707: copying the second data from the first physical erase unit to the third physical erase unit
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 are all electrically connected to a system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-Media Card (eMMC) 341 and/or embedded Multi-Chip Package (eMCP) memory device 342, which electrically connects the memory module directly to the embedded memory device on the substrate of the host system.
Fig. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used to electrically connect the memory storage device 10 to the host system 11. In the exemplary embodiment, the connection interface unit 402 conforms to the Peripheral Component Interconnect Express (PCI Express) standard and is compatible with the NVM Express interface standard. In particular, the flash non-volatile memory interface standard is a protocol for communication between a host system and a memory device, which defines a temporary memory interface, an instruction set, and a function set between a controller of the memory storage device and an operating system of the host system, and facilitates data access speed and data transfer rate of the memory storage device based on a PCIe interface by optimizing the interface standard of the memory storage device. However, in other exemplary embodiments, the connection interface unit 402 may conform to other suitable standards. In addition, the connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, a physically erased cell is the smallest unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, a physical erase unit is a physical block (block).
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.
In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another example embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding write, read, and erase operations. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.
The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for writing data, a read instruction sequence for reading data, an erase instruction sequence for erasing data, and corresponding instruction sequences for instructing various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequence of instructions may include one or more signals, or data, on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.
The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.
The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.
FIG. 6 is a schematic block diagram of a rewritable nonvolatile memory module according to a first exemplary embodiment of the present invention.
Referring to FIG. 6, the rewritable non-volatile memory module 406 includes a first memory sub-module 310, a second memory sub-module 320, a third memory sub-module 330, and a fourth memory sub-module 340. For example, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 are memory dies (die), respectively. The first memory sub-module 310 has physically erased cells 410(0) -410 (N). The second memory sub-module 320 has physically erased cells 420(0) -420 (N). The third memory sub-module 330 has physically erased cells 430(0) -430 (N). The fourth memory sub-module 340 has physically erased cells 440(0) -440 (N).
For example, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 are electrically connected to the memory control circuit unit 404 through independent data buses 316, 326, 336 and 346, respectively. Accordingly, the memory management circuit 502 may write data in parallel (parallel) to the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 via the data buses 316, 326, 336 and 346.
However, it should be understood that, in another exemplary embodiment of the present invention, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 may also be electrically connected to the memory control circuit unit 404 only through 1 data bus. Here, the memory management circuit 502 may write data to the first, second, third, and fourth memory sub-modules 310, 320, 330, and 340 in an interleaved (interleave) manner through a single data bus.
In particular, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 may respectively include a plurality of word lines, and a plurality of memory cells on the same word line form a plurality of physical pages, and the plurality of physical pages of the same word line may be referred to as a physical page group. Each of the physically erased cells of the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 has a plurality of physical pages, wherein the physical pages belonging to the same physically erased cell can be independently written and simultaneously erased. For example, each physical erase unit consists of 128 physical pages. However, it should be understood that the present invention is not limited thereto, and each physical erase unit can be composed of 64 physical pages, 256 physical pages, or any other physical pages.
In more detail, a physically erased cell is the smallest unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. The physical page is the smallest unit of programming. That is, the physical page is the smallest unit of write data. However, it should be understood that in another exemplary embodiment of the present invention, the minimum unit of the written data may be a Sector (Sector) or other size. Each physical page typically includes a data bit region and a redundancy bit region. The data bit area is used for storing user data, and the redundancy bit area is used for storing system data (such as error checking and correcting codes). It should be noted that, in another exemplary embodiment, a physically erased cell may also refer to a physical address, a physically programmed cell, or consist of multiple continuous or discontinuous physical addresses.
It should be noted that although the exemplary embodiment of the present invention is described by taking the rewritable nonvolatile memory module 406 including four memory sub-modules as an example. However, the invention is not limited thereto, and in other embodiments, the rewritable non-volatile memory module 406 may include six, eight, or ten memory sub-modules.
It should be noted that, in general, if a plurality of memory sub-modules are written simultaneously, the buffer memory 510 requires more space to store data from the host system 11. For example, if the rewritable nonvolatile memory module 406 supports four memory sub-modules that can be written to simultaneously (or in parallel), the buffer memory 510 needs to have a space of four physical page groups. When data from the host system 11 fills the space of the size of the four physical page groups in the buffer memory 510, the memory management circuit 502 will simultaneously write the data from the host system 11 from the buffer memory 510 into the four memory sub-modules. Assuming that the data is to be read, memory management circuit 502 may read the data from the four memory sub-modules simultaneously (or in parallel). However, this requires a large amount of space for the buffer memory 510, for the reason that multiple memory sub-modules are to be written simultaneously. Therefore, the present invention proposes a data writing method, and the buffer memory 510 only needs less space (e.g. the size of a physical page group) to temporarily store a plurality of data from the host system 11. When writing the rewritable non-volatile memory module 406, when the space of a physical page group in the buffer memory 510 is filled with data from the host system 11, the memory management circuit 502 writes the data from the host system 11 into a memory sub-module from the buffer memory 510. Thereafter, if a data movement operation (e.g., a valid data merge operation or an average wear operation) is to be performed, the memory management circuit 502 will distribute the data among a plurality of different memory sub-modules. When the data is to be read, the memory management circuit 502 can read the data from the memory sub-modules in parallel (or simultaneously).
Fig. 7 is a flowchart illustrating a data writing method according to an example embodiment of the present invention. Referring to fig. 7, in step S701, the memory management circuit 502 obtains a plurality of data from the host system 11 and temporarily stores the plurality of data in the buffer memory 510. In step S703, the memory management circuit 502 writes the first data and the second data of the plurality of data temporarily stored in the buffer memory 510 into the first physically erased units of the plurality of memory sub-modules. When the data shifting operation is performed, in step S705, the memory management circuit 502 copies the first data from the first entity erasing unit to the second entity erasing unit. In step S707, the memory management circuit 502 copies the second data from the first physically erased cell to a third physically erased cell. The memory sub-module to which the second entity-erased cells belong is different from the memory sub-module to which the third entity-erased cells belong.
By the data writing method of the present invention, the space required by the buffer memory 510 can be reduced, and the technical effect of reading data in a plurality of memory sub-modules in parallel can be retained.
The data writing process of the data writing method of the present application is described in more detail with reference to the following embodiments.
[ first embodiment ]
Fig. 8A to 8B are schematic diagrams illustrating an example of a data writing method according to a first embodiment of the invention.
Referring to fig. 8A to 8B, in the present exemplary embodiment, it is assumed that the rewritable nonvolatile memory module 406 is a Three-dimensional (3D) NAND flash memory module, and memory cells on each word line in the rewritable nonvolatile memory module 406 can form six physical pages, and the six physical pages on the same word line can be referred to as a physical page group. As shown in fig. 8A and 8B, the rewritable nonvolatile memory module 406 may include, for example, a word line WL1 and a word line WL2 belonging to a first memory sub-module, a word line WL3 belonging to a second memory sub-module, and a word line WL4 belonging to a third memory sub-module. The memory cells on word line WL1 form physical pages P1(0) through P1 (5). The memory cells on word line WL2 form physical pages P2(0) through P2 (5). The memory cells on word line WL3 form physical pages P3(0) through P3 (5). The memory cells on word line WL4 form physical pages P4(0) through P4 (5). In the first embodiment, word line WL1 is also referred to as "first word line", word line WL3 is also referred to as "second word line", and word line WL4 is also referred to as "third word line". In the embodiment, the physical pages P1(0) -P1 (5) and the physical pages P2(0) -P2 (5) belong to a physical erase unit (also referred to as a first physical erase unit) in the first memory sub-module. The physical pages P3(0) -P3 (5) belong to a physical erase unit (also called second physical erase unit) in the second memory sub-module. The physical pages P4(0) -P4 (5) belong to a physical erase unit (also called a third physical erase unit) in the third memory sub-module.
It is assumed that the host system 11 writes a plurality of continuous data into the rewritable nonvolatile memory module 406. The plurality of data includes first data and second data. The first data includes sub-data D0 and sub-data D1, and the second data includes sub-data D2 and sub-data D3. That is, from the viewpoint of the sub-data, the sub-data is arranged in the order of sub-data D0, sub-data D1, sub-data D2, and sub-data D3. In the first embodiment, sub-data D0 is also referred to as "first sub-data", sub-data D1 is also referred to as "second sub-data", sub-data D2 is also referred to as "third sub-data", and sub-data D3 is also referred to as "fourth sub-data". In addition, in this example, it is assumed that the host system 11 also writes a plurality of sub-data D4-D11 into the rewritable non-volatile memory module 406.
In the first embodiment, it is assumed that the buffer memory 510 stores data from the host system 11 using only the size of one physical page group. When the memory management circuit 502 obtains the sub-data D0-D5 from the host system 11, the sub-data D0-D5 are first temporarily stored in the buffer memory 510. Then, the memory management circuit 502 obtains the sub-data D0-D5 from the buffer memory 510, and writes the sub-data D0-D5 into the physical pages P1(0) -P1 (5) (also referred to as the first corresponding physical page) on the word line WL1 in the same write operation. Further, it is assumed that the memory management circuit 502 writes the sub-data D6 to D11 to the physical pages P2(0) to P2(5) on the word line WL2, respectively, in a manner similar to the foregoing. Thereafter, the memory management circuit 502 may mark a physical page group (also referred to as a first physical page group) composed of physical pages P1(0) through P1(5) on the word line WL1 and a physical page group composed of physical pages P2(0) through P2(5) on the word line WL2 with a first bit value (e.g., a value "1").
Thereafter, referring to fig. 8A and 8B, when the memory management circuit 502 is going to perform a data transfer operation, the memory management circuit 502 selects the physical page group of the word line WL1 and the physical page group of the word line WL2 according to the first bit value. The memory management circuit 502 copies the sub-data D0 and the sub-data D1 from the word line WL1, and sequentially writes the sub-data D0 and the sub-data D1 into the physical page P3(0) and the physical page P3(1) on the word line WL3, respectively. The memory management circuit 502 also copies the sub data D2 and the sub data D3 from the word line WL1, and sequentially writes the sub data D2 and the sub data D3 to the physical page P4(0) and the physical page P4(1) on the word line WL4, respectively. In the first embodiment, the entity page P3(0) is also referred to as "first entity page". Entity page P3(1) is also referred to as a "second entity page". Entity page P4(0) is also referred to as the "third entity page". Entity page P4(1) is also referred to as the "fourth entity page".
Similarly, when a data shifting operation is performed, the memory management circuit 502 also copies the sub data D4 and the sub data D5 from the word line WL1, and sequentially writes the sub data D4 and the sub data D5 into the physical page P3(2) and the physical page P3(3) on the word line WL3, respectively. The memory management circuit 502 also copies sub-data D6 and sub-data D7 from the word line WL2, and sequentially writes sub-data D6 and sub-data D7 to the physical page P4(2) and the physical page P4(3) on the word line WL4, respectively. The memory management circuit 502 also copies sub-data D8 and sub-data D9 from the word line WL2, and sequentially writes sub-data D8 and sub-data D9 to the physical page P3(4) and the physical page P3(5) on the word line WL3, respectively. The memory management circuit 502 also copies sub-data D10 and sub-data D11 from the word line WL2, and sequentially writes sub-data D10 and sub-data D11 to the physical page P4(4) and the physical page P4(5) on the word line WL4, respectively.
Thereafter, the memory management circuit 502 may mark a physical page group (also referred to as a second physical page group) composed of physical pages P3(0) -P3 (5) on the word line WL3 and a physical page group (also referred to as a third physical page group) composed of physical pages P4(0) -P4 (5) on the word line WL4 with a second bit value (e.g., a value of "0"). In this example, the entity pages P3(0) and P3(1) in the word line WL3 for writing the first data (i.e., the sub data D0 and the sub data D1) may be collectively referred to as "second corresponding entity pages". The entity page P4(0) and the entity page P4(1) in the word line WL4 for writing the second data (i.e., the sub data D2 and the sub data D3) may be collectively referred to as a "third corresponding entity page".
Then, assuming that the memory management circuit 502 is to read the sub-data D0-D3, the memory management circuit 502 may read the entity pages P3(0) -P3 (1) and the entity pages P4(0) -P4 (1) located in different memory sub-modules in parallel to obtain the sub-data D0-D3.
[ second embodiment ]
Fig. 9 is a diagram illustrating an example of a data writing method according to a second embodiment of the invention.
Referring to fig. 8A and fig. 9, in the present exemplary embodiment, similar to the description of the first embodiment, it is assumed that the host system 11 is to write a plurality of continuous data into the rewritable nonvolatile memory module 406. The plurality of data includes first data and second data. The first data includes sub-data D0 and sub-data D2, and the second data includes sub-data D1 and sub-data D3. From the viewpoint of the sub-data, the sub-data is sequentially arranged as sub-data D0, sub-data D1, sub-data D2, and sub-data D3. In the second embodiment, sub-data D0 is also referred to as "fifth sub-data", sub-data D1 is also referred to as "seventh sub-data", sub-data D2 is also referred to as "sixth sub-data", and sub-data D3 is also referred to as "eighth sub-data". In addition, in this example, it is assumed that the host system 11 also writes a plurality of sub-data D4-D11 into the rewritable non-volatile memory module 406. In the embodiment, the physical pages P1(0) -P1 (5) and the physical pages P2(0) -P2 (5) belong to a physical erase unit (also referred to as a first physical erase unit) in the first memory sub-module. The physical pages P3(0) -P3 (5) belong to a physical erase unit (also called second physical erase unit) in the second memory sub-module. The physical pages P4(0) -P4 (5) belong to a physical erase unit (also called a third physical erase unit) in the third memory sub-module.
In the second embodiment, it is assumed that the buffer memory 510 stores data from the host system 11 using only the size of one physical page group. When the memory management circuit 502 obtains the sub-data D0-D5 from the host system 11, the sub-data D0-D5 are first temporarily stored in the buffer memory 510. Then, the memory management circuit 502 obtains the sub-data D0 to D5 from the buffer memory 510, and writes the sub-data D0 to D5 to the physical pages P1(0) to P1(5) (also referred to as the first corresponding physical page) on the word line WL1 in the same write operation. Further, it is assumed that the memory management circuit 502 writes the sub-data D6 to D11 to the physical pages P2(0) to P2(5) on the word line WL2, respectively, in a manner similar to the foregoing. Thereafter, the memory management circuit 502 may mark a physical page group (also referred to as a first physical page group) composed of physical pages P1(0) through P1(5) on the word line WL1 and a physical page group composed of physical pages P2(0) through P2(5) on the word line WL2 with a first bit value (e.g., a value "1").
Thereafter, referring to fig. 8A and fig. 9, when the memory management circuit 502 is going to perform a data transfer operation, the memory management circuit 502 selects the physical page group of the word line WL1 and the physical page group of the word line WL2 according to the first bit value. The memory management circuit 502 copies the sub-data D0 and the sub-data D2 from the word line WL1, and sequentially writes the sub-data D0 and the sub-data D2 to the physical page P3(0) and the physical page P3(1) on the word line WL3, respectively. The memory management circuit 502 also copies the sub data D1 and the sub data D3 from the word line WL1, and sequentially writes the sub data D1 and the sub data D3 to the physical page P4(0) and the physical page P4(1) on the word line WL4, respectively. In the second embodiment, the physical page P3(0) is also referred to as "fifth volume page". Entity page P3(1) is also referred to as the "sixth entity page". Entity page P4(0) is also referred to as the "seventh entity page". Entity page P4(1) is also referred to as "eighth entity page".
Similarly, when data shifting operation is performed, the memory management circuit 502 also copies sub-data D4 and sub-data D6 from the word line WL1 and the word line WL2, and sequentially writes the sub-data D4 and the sub-data D6 into the physical page P3(2) and the physical page P3(3) on the word line WL3, respectively. The memory management circuit 502 also copies sub-data D5 and sub-data D7 from the word line WL1 and the word line WL2, and sequentially writes sub-data D5 and sub-data D7 to the physical page P4(2) and the physical page P4(3) on the word line WL4, respectively. The memory management circuit 502 also copies sub-data D8 and sub-data D10 from the word line WL2, and sequentially writes sub-data D8 and sub-data D10 to the physical page P3(4) and the physical page P3(5) on the word line WL3, respectively. The memory management circuit 502 also copies sub-data D9 and sub-data D11 from the word line WL2, and sequentially writes sub-data D9 and sub-data D11 to the physical page P4(4) and the physical page P4(5) on the word line WL4, respectively.
Thereafter, the memory management circuit 502 may mark a physical page group (also referred to as a second physical page group) composed of physical pages P3(0) -P3 (5) on the word line WL3 and a physical page group (also referred to as a third physical page group) composed of physical pages P4(0) -P4 (5) on the word line WL4 with a second bit value (e.g., a value of "0"). In this example, the entity pages P3(0) and P3(1) in the word line WL3 for writing the first data (i.e., the sub data D0 and the sub data D2) may be collectively referred to as "second corresponding entity pages". The entity page P4(0) and the entity page P4(1) in the word line WL4 for writing the second data (i.e., the sub data D1 and the sub data D3) may be collectively referred to as a "third corresponding entity page".
Then, assuming that the memory management circuit 502 is to read the sub-data D0-D3, the memory management circuit 502 may read the entity pages P3(0) -P3 (1) and the entity pages P4(0) -P4 (1) located in different memory sub-modules in parallel to obtain the sub-data D0-D3.
In summary, the data writing method, the memory control circuit unit and the memory storage device of the present invention can reduce the space required by the buffer memory and retain the technical effect of reading the data in the plurality of memory sub-modules in parallel.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (18)

1. A data writing method is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module comprises a plurality of memory sub-modules, each memory sub-module in the plurality of memory sub-modules comprises a plurality of entity erasing units, and the data writing method comprises the following steps:
obtaining a plurality of data from a host system and temporarily storing the data in a buffer memory;
writing first data and second data in the plurality of data temporarily stored in the buffer memory into first entity erasing units in the plurality of memory sub-modules;
copying the first data and the second data from the first physically erased cell to a second physically erased cell and a third physically erased cell, respectively, simultaneously; and
wherein the memory sub-module to which the second physically-erased cells belong is different from the memory sub-module to which the third physically-erased cells belong,
the plurality of memory sub-modules are respectively connected with a memory control circuit unit through a plurality of channels, and the memory control circuit unit reads the plurality of memory sub-modules in parallel through the plurality of channels.
2. The data writing method according to claim 1, wherein in the step of writing the first data and the second data of the plurality of data temporarily stored in the buffer memory to the first physically erased cell of the plurality of memory sub-modules,
the writing of the first data and the writing of the second data are completed in the same write operation.
3. The data writing method of claim 1, wherein the plurality of data are arranged according to an order in the host system, the first data includes first sub data and second sub data, the second data includes third sub data and fourth sub data,
wherein the step of simultaneously copying the first data and the second data from the first physically erased cell to the second physically erased cell and the third physically erased cell, respectively, comprises:
sequentially writing the first subdata and the second subdata into a first physical page and a second physical page in the second physical erasing unit respectively,
sequentially writing the third sub data and the fourth sub data into a third physical page and a fourth physical page in the third physical erase unit,
wherein the first sub-data and the second sub-data are consecutive, the second sub-data and the third sub-data are consecutive, and the third sub-data and the fourth sub-data are consecutive in the sequence of the plurality of data.
4. The data writing method of claim 1, wherein the plurality of data are arranged according to an order in the host system, the first data includes fifth sub data and sixth sub data, the second data includes seventh sub data and eighth sub data,
wherein the step of simultaneously copying the first data and the second data from the first physically erased cell to the second physically erased cell and the third physically erased cell, respectively, comprises:
sequentially writing the fifth sub data and the sixth sub data into a fifth physical page and a sixth physical page in the second physical erase unit,
sequentially writing the seventh sub data and the eighth sub data into a seventh physical page and an eighth physical page in the third physical erase unit,
wherein the fifth sub-data and the seventh sub-data are consecutive, the sixth sub-data and the seventh sub-data are consecutive, and the sixth sub-data and the eighth sub-data are consecutive in the sequence of the plurality of data.
5. The data writing method according to claim 1, further comprising:
marking a first entity page group used for storing the first data and the second data in the first entity erasing unit by using a first bit value;
marking a second set of physical pages in the second physically erasable unit for storing the first data with a second bit value; and
marking a third set of physical pages in the third physical erase unit for storing the second data using the second bit values.
6. The data writing method according to claim 1, further comprising:
the step of simultaneously copying the first data and the second data from the first physically erased cell to the second physically erased cell and the third physically erased cell, respectively, is performed while at least one of a valid data merge operation and an average wear operation is performed.
7. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of memory sub-modules, each of the plurality of memory sub-modules includes a plurality of physical erase units, the memory control circuit unit comprising:
a host interface for electrically connecting to a host system;
the memory interface is used for being electrically connected to the rewritable nonvolatile memory module, and the plurality of memory sub-modules are respectively and electrically connected to the memory interface;
a memory management circuit electrically connected to the host interface and the memory interface,
wherein the memory management circuit is used for obtaining a plurality of data from the host system and temporarily storing the plurality of data in a buffer memory,
wherein the memory management circuit is further configured to write a first data and a second data of the plurality of data temporarily stored in the buffer memory into a first physically erased cell of the plurality of memory sub-modules,
wherein the memory management circuit is further configured to copy the first data and the second data from the first physically erased cell to a second physically erased cell and a third physically erased cell, respectively,
wherein the memory sub-module to which the second physically-erased cells belong is different from the memory sub-module to which the third physically-erased cells belong,
the memory management circuit reads the memory sub-modules in parallel through the channels.
8. The memory control circuit unit of claim 7, wherein in the operation of writing the first data and the second data of the plurality of data temporarily stored in the buffer memory to the first physical erase unit of the plurality of memory sub-modules,
the writing of the first data and the writing of the second data are completed in the same write operation.
9. The memory control circuit unit of claim 7, wherein the plurality of data are arranged according to an order in the host system, the first data includes first sub data and second sub data, the second data includes third sub data and fourth sub data,
wherein in the operation of copying the first data and the second data from the first physically erased cell to the second physically erased cell and the third physically erased cell simultaneously,
the memory management circuit is further configured to sequentially write the first sub data and the second sub data into a first physical page and a second physical page of the second physical erase unit,
the memory management circuit is further configured to sequentially write the third sub-data and the fourth sub-data into a third physical page and a fourth physical page of the third physical erase unit,
in the sequence of the plurality of data, the first sub-data and the second sub-data are continuous, the second sub-data and the third sub-data are continuous, and the third sub-data and the fourth sub-data are continuous.
10. The memory control circuit unit of claim 7, wherein the plurality of data are arranged according to an order in the host system, the first data include fifth sub data and sixth sub data, the second data include seventh sub data and eighth sub data,
wherein in the operation of copying the first data and the second data from the first physically erased cell to the second physically erased cell and the third physically erased cell simultaneously,
the memory management circuit is further configured to sequentially write the fifth sub-data and the sixth sub-data into a fifth physical page and a sixth physical page of the second physical erase unit,
the memory management circuit is further configured to sequentially write the seventh sub-data and the eighth sub-data into a seventh physical page and an eighth physical page of the third physical erase unit,
in the sequence of the plurality of data, the fifth sub-data and the seventh sub-data are consecutive, the sixth sub-data and the seventh sub-data are consecutive, and the sixth sub-data and the eighth sub-data are consecutive.
11. The memory control circuit cell of claim 7, wherein
The memory management circuit is further configured to mark a first set of physical pages in the first physically erased cell for storing the first data and the second data with a first bit value,
the memory management circuit is further configured to mark a second set of physical pages in the second physically erased cell for storing the first data using a second bit value,
the memory management circuit is further configured to mark a third set of physical pages in the third physical erase unit for storing the second data using the second bit value.
12. The memory control circuit cell of claim 7, wherein
The memory management circuit is further configured to perform an operation of simultaneously copying the first data and the second data from the first physically-erased cell to the second physically-erased cell and the third physically-erased cell, respectively, when at least one of a valid data merge operation and an average wear operation is performed.
13. A memory storage device, comprising:
the connection interface unit is used for electrically connecting to a host system;
the rewritable nonvolatile memory module comprises a plurality of memory sub-modules, wherein each memory sub-module comprises a plurality of entity erasing units; and
a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module, and the memory sub-modules are respectively electrically connected to the memory control circuit unit,
the memory control circuit unit is used for obtaining a plurality of data from the host system and temporarily storing the data in a buffer memory;
the memory control circuit unit is further used for writing first data and second data in the plurality of data temporarily stored in the buffer memory into a first entity erasing unit in the plurality of memory sub-modules;
wherein the memory control circuit unit is further configured to copy the first data and the second data from the first physically erased cell to a second physically erased cell and a third physically erased cell, respectively, simultaneously;
wherein the memory sub-module to which the second physically-erased cells belong is different from the memory sub-module to which the third physically-erased cells belong,
the memory control circuit unit reads the memory sub-modules in parallel through the channels.
14. The memory storage device of claim 13, wherein in the operation of writing the first data and the second data of the plurality of data temporarily stored in the buffer memory to the first physically erasable unit of the plurality of memory sub-modules,
the writing of the first data and the writing of the second data are completed in the same write operation.
15. The memory storage device of claim 13, wherein the plurality of data is arranged according to an order in the host system, the first data includes first sub data and second sub data, the second data includes third sub data and fourth sub data,
wherein in an operation to copy the first data and the second data from the first physically erased cell to the second physically erased cell and the third physically erased cell, respectively, simultaneously,
the memory control circuit unit is further configured to sequentially write the first sub data and the second sub data into a first physical page and a second physical page of the second physical erase unit,
the memory control circuit unit is further configured to sequentially write the third sub data and the fourth sub data into a third physical page and a fourth physical page of the third physical erase unit,
wherein the first sub-data and the second sub-data are consecutive, the second sub-data and the third sub-data are consecutive, and the third sub-data and the fourth sub-data are consecutive in the sequence of the plurality of data.
16. The memory storage device of claim 13, wherein the plurality of data is arranged according to an order in the host system, the first data includes fifth sub-data and sixth sub-data, the second data includes seventh sub-data and eighth sub-data,
wherein in the operation of copying the first data and the second data from the first physically erased cell to the second physically erased cell and the third physically erased cell simultaneously,
the memory control circuit unit is further configured to sequentially write the fifth sub-data and the sixth sub-data into a fifth physical page and a sixth physical page of the second physical erase unit,
the memory control circuit unit is further configured to sequentially write the seventh sub-data and the eighth sub-data into a seventh physical page and an eighth physical page of the third physical erase unit,
wherein the fifth sub-data and the seventh sub-data are consecutive, the sixth sub-data and the seventh sub-data are consecutive, and the sixth sub-data and the eighth sub-data are consecutive in the sequence of the plurality of data.
17. The memory storage device of claim 13, wherein
The memory control circuit unit is further configured to mark a first physical page set in the first physical erase unit for storing the first data and the second data with a first bit value,
the memory control circuit unit is further configured to mark a second set of physical pages in the second physically erased unit for storing the first data with a second bit value, an
The memory control circuit unit is further configured to mark a third set of physical pages in the third physical erase unit for storing the second data using the second bit values.
18. The memory storage device of claim 13, wherein
The memory control circuit unit is further configured to perform an operation of copying the first data and the second data from the first physically-erased cell to the second physically-erased cell and the third physically-erased cell, respectively, simultaneously when at least one of a valid data merge operation and an average wear operation is performed.
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CN108733577A (en) * 2017-04-21 2018-11-02 群联电子股份有限公司 Storage management method, memorizer control circuit unit and memory storage apparatus
CN108959109A (en) * 2017-05-26 2018-12-07 群联电子股份有限公司 Method for reading data, memorizer control circuit unit and memory storage apparatus
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CN107818808A (en) * 2016-09-14 2018-03-20 群联电子股份有限公司 Method for writing data, memorizer control circuit unit and memory storage apparatus
CN108733577A (en) * 2017-04-21 2018-11-02 群联电子股份有限公司 Storage management method, memorizer control circuit unit and memory storage apparatus
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