CN112216329B - Data erasing method, memory control circuit unit and memory storage device - Google Patents

Data erasing method, memory control circuit unit and memory storage device Download PDF

Info

Publication number
CN112216329B
CN112216329B CN201910627492.XA CN201910627492A CN112216329B CN 112216329 B CN112216329 B CN 112216329B CN 201910627492 A CN201910627492 A CN 201910627492A CN 112216329 B CN112216329 B CN 112216329B
Authority
CN
China
Prior art keywords
physical
unit
erase
units
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910627492.XA
Other languages
Chinese (zh)
Other versions
CN112216329A (en
Inventor
叶志刚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Phison Electronics Corp
Original Assignee
Phison Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phison Electronics Corp filed Critical Phison Electronics Corp
Priority to CN201910627492.XA priority Critical patent/CN112216329B/en
Publication of CN112216329A publication Critical patent/CN112216329A/en
Application granted granted Critical
Publication of CN112216329B publication Critical patent/CN112216329B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Read Only Memory (AREA)

Abstract

The invention provides a data erasing method, a memory control circuit unit and a memory storage device. The method comprises the following steps: selecting a first physical erase unit group from the plurality of physical erase unit groups; and performing an erase operation on the first physically erased cell group. The first physical erasing unit group comprises a plurality of first physical erasing units, and the number of at least one second physical erasing unit in the plurality of first physical erasing units used for executing the erasing operation in the same time point is different from the number of the plurality of first physical erasing units.

Description

Data erasing method, memory control circuit unit and memory storage device
Technical Field
The invention relates to a data erasing method, a memory control circuit unit and a memory storage device.
Background
Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since the rewritable nonvolatile memory module (e.g., flash memory) has the characteristics of nonvolatile data, power saving, small size, no mechanical structure, etc., it is very suitable for being built in the various portable multimedia devices as exemplified above.
In general, a rewritable non-volatile memory module may include a plurality of memory sub-modules. To increase the writing efficiency, the memory management circuit generally writes data into the aforementioned memory sub-modules through a plurality of data buses in a parallel (parallel) manner. In the parallel writing process, each physical erasing unit in the physical erasing unit group is usually simultaneously written with data at a certain time point, assuming that the data volume for writing is exactly equal to the data volume that can be stored in one physical erasing unit group.
If the memory management circuit needs to perform an erase operation (e.g., perform a valid data merge or other operation) on the physically erased cells in the physically erased cell group, the memory management circuit will typically perform the erase operation on a plurality of physically erased cells in the physically erased cell group at the same time. That is, in the prior art, in order to maintain the efficiency of parallel writing, an erase operation is usually performed in units of one physical erase unit to release the space of one physical erase unit and to be used for the subsequent parallel writing.
In the case that a physical erase unit group includes a physical erase unit in each memory sub-module, when an erase operation is performed in units of a physical erase unit group, since all the memory sub-modules in the rewritable nonvolatile memory are used to perform the erase operation, if the host system continues to issue a plurality of write commands at this time, data from the host system cannot be written into the rewritable nonvolatile memory and needs to be temporarily stored in the buffer memory. However, due to the limited space of the buffer memory, a larger buffer memory is required to temporarily store data from the host system as the erase operation is performed longer and the host system continues to issue write commands. Therefore, it is one of the problems to be solved by those skilled in the art how to avoid the problem caused by that all the memory sub-modules in the rewritable nonvolatile memory are simultaneously used for performing the erase operation.
Disclosure of Invention
The invention provides a data erasing method, a memory control circuit unit and a memory storage device, which can avoid the problem caused by that all memory submodules in a rewritable nonvolatile memory are simultaneously used for executing erasing operation without using a buffer memory with larger capacity.
The invention provides a data erasing method, which is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of entity erasing unit groups, each entity erasing unit group in the entity erasing unit groups is provided with a plurality of entity erasing units, and the data erasing method comprises the following steps: selecting a first physical erase unit group from the plurality of physical erase unit groups; and performing an erase operation on the first set of physically-erased cells, wherein the first set of physically-erased cells includes a plurality of first physically-erased cells, and a number of at least one second physically-erased cell of the plurality of first physically-erased cells used to perform the erase operation at a same point in time is different from a number of the plurality of first physically-erased cells.
In an embodiment of the invention, the method further comprises: performing a write operation on a second physical erase unit of the plurality of physical erase unit groups according to at least one write command, wherein the second physical erase unit group comprises a plurality of third physical erase units; when the data amount stored in the second entity erasing unit group reaches a first threshold value, executing the step of executing the erasing operation on the first entity erasing unit group so as to execute the erasing operation on a fourth entity erasing unit in the plurality of first entity erasing units; and when the data amount stored in the second physical erasing unit group reaches a second threshold value, executing the step of executing the erasing operation on the first physical erasing unit group to execute the erasing operation on a fifth physical erasing unit in the plurality of first physical erasing units, wherein the first threshold value is smaller than the second threshold value.
In an embodiment of the present invention, when the amount of data stored in the second physical erase unit reaches the capacity of the second physical erase unit for storing data, the data stored in the plurality of first physical erase units of the first physical erase unit are erased.
In an embodiment of the invention, the rewritable nonvolatile memory module includes a plurality of memory sub-modules, the plurality of memory sub-modules are respectively connected to a memory control circuit unit through a plurality of channels, and the plurality of physical erasing units of each of the plurality of physical erasing unit groups respectively belong to different memory sub-modules of the plurality of memory sub-modules.
In an embodiment of the present invention, the memory control circuit unit performs the write operation on the plurality of third physical erase units in the second physical erase unit group through the plurality of channels to write a plurality of data in parallel in the plurality of third physical erase units.
In one embodiment of the present invention, before performing the erase operation on the first physical erase unit group, the method further includes: adjusting the order of performing a write operation on the plurality of first physical erase units; and executing the write operation on the plurality of first physical erasing units according to the write sequence and a write instruction so that at least one sixth physical erasing unit in the plurality of first physical erasing units has a usable storage space when the storage space of the second physical erasing unit is full.
In one embodiment of the present invention, in the plurality of physical erase unit groups, the plurality of physical erase units in the same physical erase unit group correspond to a same index code in a logical address-physical address mapping table.
In an embodiment of the present invention, each of the plurality of first physical erase units in the first physical erase unit group includes a first physical program unit and a second physical program unit. When the first physical programming units of each of the plurality of first physical erasing units are programmed, the second physical programming units of each of the plurality of first physical erasing units can be programmed.
In an embodiment of the present invention, each of the plurality of first physical erase units in the first physical erase unit group includes a first physical program unit. When the first physical erasing unit group is written with continuous data, a plurality of logic addresses corresponding to a plurality of data stored by the first physical programming units of the first physical erasing units in the first physical erasing unit group are continuous.
In an embodiment of the present invention, each of the plurality of first physical erase units in the first physical erase unit group includes a first physical program unit and a second physical program unit. When the first physical erasing unit group is written with continuous data, the logic address corresponding to the data stored by the first physical programming unit of a seventh physical erasing unit in the first physical erasing unit group is discontinuous with the logic address corresponding to the data stored by the second physical programming unit of the seventh physical erasing unit, and the first physical programming unit and the second physical programming unit of the seventh physical erasing unit are arranged continuously in entity.
The invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of entity erasing unit groups, each entity erasing unit group in the entity erasing unit groups is provided with a plurality of entity erasing units, and the memory control circuit unit comprises: host interface, memory interface and memory management circuit. The host interface is used for being electrically connected to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface and is used for executing the following operations: selecting a first physical erase unit group from the plurality of physical erase unit groups; and performing an erase operation on the first set of physically-erased cells, wherein the first set of physically-erased cells includes a plurality of first physically-erased cells, and a number of at least one second physically-erased cell of the plurality of first physically-erased cells used to perform the erase operation at a same point in time is different from a number of the plurality of first physically-erased cells.
In an embodiment of the invention, the memory management circuit is further configured to perform a write operation on a second physical erase unit among the plurality of physical erase unit groups according to at least one write command, wherein the second physical erase unit group includes a plurality of third physical erase units. When the data amount stored in the second physical erasing unit group reaches a first threshold value, the memory management circuit is further configured to perform the operation of performing the erasing operation on the first physical erasing unit group so as to perform the erasing operation on a fourth physical erasing unit of the plurality of first physical erasing units. When the data amount stored in the second physical erase unit group reaches a second threshold, the memory management circuit is further configured to perform the erase operation on the first physical erase unit group to perform the erase operation on a fifth physical erase unit of the plurality of first physical erase units, wherein the first threshold is smaller than the second threshold.
In an embodiment of the present invention, when the amount of data stored in the second physical erase unit reaches the capacity of the second physical erase unit for storing data, the data stored in the plurality of first physical erase units of the first physical erase unit are erased.
In an embodiment of the invention, the rewritable nonvolatile memory module includes a plurality of memory sub-modules, the plurality of memory sub-modules are respectively connected to the memory management circuit through a plurality of channels, and the plurality of physical erasing units of each of the plurality of physical erasing unit groups respectively belong to different memory sub-modules in the plurality of memory sub-modules.
In one embodiment of the present invention, the memory management circuit performs the write operation on the plurality of third physical erase units in the second physical erase unit group through the plurality of channels to write a plurality of data in parallel in the plurality of third physical erase units.
In one embodiment of the present invention, the memory management circuit is further configured to adjust an order of performing a write operation on the plurality of first physically erased cells before performing the erase operation on the first physically erased cell group. The memory management circuit is further configured to perform the write operation on the plurality of first physical erase units according to the write sequence and a write command such that at least a sixth physical erase unit of the plurality of first physical erase units has a usable memory space when the memory space of the second physical erase unit is full.
In one embodiment of the present invention, in the plurality of physical erase unit groups, the plurality of physical erase units in the same physical erase unit group correspond to a same index code in a logical address-physical address mapping table.
In an embodiment of the present invention, each of the plurality of first physical erase units in the first physical erase unit group includes a first physical program unit and a second physical program unit. When the first physical programming units of each of the plurality of first physical erasing units are programmed, the second physical programming units of each of the plurality of first physical erasing units can be programmed.
In an embodiment of the present invention, each of the plurality of first physical erase units in the first physical erase unit group includes a first physical program unit. When the first physical erasing unit group is written with continuous data, a plurality of logic addresses corresponding to a plurality of data stored by the first physical programming units of the first physical erasing units in the first physical erasing unit group are continuous.
In an embodiment of the present invention, each of the plurality of first physical erase units in the first physical erase unit group includes a first physical program unit and a second physical program unit. When the first physical erasing unit group is written with continuous data, the logic address corresponding to the data stored by the first physical programming unit of a seventh physical erasing unit in the first physical erasing unit group is discontinuous with the logic address corresponding to the data stored by the second physical programming unit of the seventh physical erasing unit, and the first physical programming unit and the second physical programming unit of the seventh physical erasing unit are arranged continuously in entity.
The invention proposes a memory storage device comprising: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The connection interface unit is used for being electrically connected to a host system. The rewritable nonvolatile memory module comprises a plurality of physical erasing unit groups, wherein each physical erasing unit group in the plurality of physical erasing unit groups is provided with a plurality of physical erasing units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module and is used for executing the following operations: selecting a first physical erase unit group from the plurality of physical erase unit groups; and performing an erase operation on the first set of physically-erased cells, wherein the first set of physically-erased cells includes a plurality of first physically-erased cells, and a number of at least one second physically-erased cell of the plurality of first physically-erased cells used to perform the erase operation at a same point in time is different from a number of the plurality of first physically-erased cells.
In an embodiment of the invention, the memory control circuit unit is further configured to perform a write operation on a second physical erase unit among the plurality of physical erase unit groups according to at least one write command, wherein the second physical erase unit group includes a plurality of third physical erase units. When the data amount stored in the second physical erasing unit group reaches a first threshold value, the memory control circuit unit is further configured to perform the step of performing the erasing operation on the first physical erasing unit group to perform the erasing operation on a fourth physical erasing unit of the plurality of first physical erasing units. When the data amount stored in the second physical erasing unit group reaches a second threshold value, the memory control circuit unit is further configured to perform the step of performing the erasing operation on the first physical erasing unit group to perform the erasing operation on a fifth physical erasing unit of the plurality of first physical erasing units, wherein the first threshold value is smaller than the second threshold value.
In an embodiment of the present invention, when the amount of data stored in the second physical erase unit reaches the capacity of the second physical erase unit for storing data, the data stored in the plurality of first physical erase units of the first physical erase unit are erased.
In an embodiment of the invention, the rewritable nonvolatile memory module includes a plurality of memory sub-modules, the plurality of memory sub-modules are respectively connected to a memory control circuit unit through a plurality of channels, and the plurality of physical erasing units of each of the plurality of physical erasing unit groups respectively belong to different memory sub-modules of the plurality of memory sub-modules.
In an embodiment of the present invention, the memory control circuit unit performs the write operation on the plurality of third physical erase units in the second physical erase unit group through the plurality of channels to write a plurality of data in parallel in the plurality of third physical erase units.
In an embodiment of the present invention, before the erasing operation is performed on the first physical erasing unit group, the memory control circuit unit is further configured to adjust an order of performing a writing operation on the plurality of first physical erasing units, and the memory control circuit unit is further configured to perform the writing operation on the plurality of first physical erasing units according to the writing order and a writing instruction, so that at least a sixth physical erasing unit of the plurality of first physical erasing units has a usable storage space when the storage space of the second physical erasing unit is full.
In one embodiment of the present invention, in the plurality of physical erase unit groups, the plurality of physical erase units in the same physical erase unit group correspond to a same index code in a logical address-physical address mapping table.
In an embodiment of the present invention, each of the plurality of first physical erase units in the first physical erase unit group includes a first physical program unit and a second physical program unit. When the first physical programming units of each of the plurality of first physical erasing units are programmed, the second physical programming units of each of the plurality of first physical erasing units can be programmed.
In an embodiment of the present invention, each of the plurality of first physical erase units in the first physical erase unit group includes a first physical program unit. When the first physical erasing unit group is written with continuous data, a plurality of logic addresses corresponding to a plurality of data stored by the first physical programming units of the first physical erasing units in the first physical erasing unit group are continuous.
In an embodiment of the present invention, each of the plurality of first physical erase units in the first physical erase unit group includes a first physical program unit and a second physical program unit. When the first physical erasing unit group is written with continuous data, the logic address corresponding to the data stored by the first physical programming unit of a seventh physical erasing unit in the first physical erasing unit group is discontinuous with the logic address corresponding to the data stored by the second physical programming unit of the seventh physical erasing unit, and the first physical programming unit and the second physical programming unit of the seventh physical erasing unit are arranged continuously in entity.
In view of the foregoing, in the data erasing method, the memory control circuit unit and the memory storage device of the present invention, since the erasing operation is not performed on all the physically erased cells in a physically erased cell group at the same time point, not all the memory sub-modules are used to perform the erasing operation at the same time point. At this time, when the host system still continues to issue the write command, the data from the host system can be written into the rewritable nonvolatile memory without being temporarily stored in the buffer memory for waiting for the completion of the erase operation. Therefore, the data erasing method of the invention can avoid the problem caused by that all the memory submodules in the rewritable nonvolatile memory are simultaneously used for executing the erasing operation without using a buffer memory with larger capacity.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;
FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;
FIG. 6 is a schematic block diagram of a rewritable non-volatile memory module according to a first exemplary embodiment of the present invention;
FIG. 7 is a flowchart of a method for erasing data according to an exemplary embodiment of the present invention;
8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A and 12B are schematic diagrams illustrating examples of a data erasing method according to a first exemplary embodiment of the invention;
FIG. 13 is a diagram illustrating an example of a data erasing method according to the second exemplary embodiment of the present invention.
Reference numerals illustrate:
30. 10: memory storage device
31. 11: host system
110: system bus
111: processor and method for controlling the same
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: motherboard
201: portable disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with keyboard body
209: screen panel
210: horn with horn body
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
404: memory control circuit unit
406: rewritable nonvolatile memory module
502: memory management circuit
504: host interface
506: memory interface
508: error checking and correcting circuit
510: buffer memory
512: power management circuit
310: first memory submodule
320: second memory sub-module
330: third memory sub-module
340: fourth memory sub-module
316. 326, 336, 346: data bus
410 (0) to 410 (N), 420 (0) to 420 (N), 430 (0) to 430 (N), 440 (0) to 440 (N): physical erasing unit
OD1 to OD16, ND1 to ND16, ID1 to ID8: data
S701: selecting a first physical erase unit from a plurality of physical erase units
S703: performing an erase operation on a first physical erase unit group including a plurality of first physical erase units, wherein the number of second physical erase units in the first physical erase units used to perform the erase operation at the same time is different from the number of first physical erase units
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are all electrically connected to a system bus 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through a wired or wireless manner via the data transmission interface 114. The memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.
In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded memory devices of various types, such as embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or embedded multi-chip package (embedded Multi Chip Package, eMCP) memory device 342, that electrically connect the memory module directly to the substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used for electrically connecting the memory storage device 10 to the host system 11. In the present exemplary embodiment, the connection interface unit 402 is compliant with the high speed peripheral component interconnect (PCI Express) interface (Peripheral Component Interconnect Express) standard and compatible with the flash nonvolatile memory (NVM Express) interface standard. Specifically, the flash nonvolatile memory interface standard is a protocol for communication between a host system and a memory device, which defines a register interface, an instruction set, and a function set between a controller of the memory storage device and an operating system of the host system, and facilitates data access speed and data transfer rate of a memory storage device based on a PCIe interface by optimizing the interface standard of the memory storage device. However, in another exemplary embodiment, the connection interface unit 402 may also conform to other suitable standards. In addition, the connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or solid state and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a complex-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.
In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical program cells, and the physical program cells form a plurality of physical erase cells. Specifically, memory cells on the same word line constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.
In the present exemplary embodiment, the physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit is a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units typically include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical sectors, and one physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased. For example, the physical erased cells are physical blocks (blocks).
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is operating. The operation of the memory management circuit 502 is described as follows, which is equivalent to the description of the operation of the memory control circuit unit 404.
In the present example embodiment, the control instructions of the memory management circuitry 502 are implemented in a solid state fashion. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.
In another example embodiment, the control instructions of the memory management circuit 502 may also be stored in program code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.
Furthermore, in another example embodiment, the control instructions of the memory management circuit 502 may also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 406 to perform the corresponding write, read, erase, etc. In an example embodiment, the memory management circuitry 502 may also issue other types of sequences of instructions to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and recognizing the commands and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the present exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.
The memory interface 506 is electrically connected to the memory management circuit 502 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 is to access the rewritable nonvolatile memory module 406, the memory interface 506 will transmit the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by memory management circuitry 502 and transferred to rewritable non-volatile memory module 406 through memory interface 506. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.
In an example embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.
The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 508 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.
The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.
FIG. 6 is a schematic block diagram of a rewritable nonvolatile memory module according to a first exemplary embodiment of the present invention.
Referring to fig. 6, the rewritable nonvolatile memory module 406 includes a first memory sub-module 310, a second memory sub-module 320, a third memory sub-module 330 and a fourth memory sub-module 340. For example, the first, second, third, and fourth memory sub-modules 310, 320, 330, and 340 are memory dies (die), respectively. The first memory sub-module 310 has physical erase units 410 (0) to 410 (N). The second memory sub-module 320 has physical erase units 420 (0) through 420 (N). The third memory sub-module 330 has physical erase units 430 (0) to 430 (N). The fourth memory sub-module 340 has physical erase units 440 (0) to 440 (N).
For example, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 are electrically connected to the memory control circuit unit 404 through independent data buses 316, 326, 336 and 346, respectively. Accordingly, the memory management circuit 502 may write data to the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 via the data buses 316, 326, 336 and 346 in a parallel (parallel) manner.
However, it should be understood that in another exemplary embodiment of the present invention, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 may be electrically connected to the memory control circuit unit 404 through only 1 data bus. Here, the memory management circuit 502 may write data to the first, second, third, and fourth memory sub-modules 310, 320, 330, and 340 via a single data bus in an interleaved (interleaved) manner.
In particular, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 may include a plurality of word lines, respectively, and a plurality of memory cells on the same word line may form a plurality of physical pages, and the plurality of physical pages of the same word line may be referred to as a physical page group. Each physical erase unit of the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 has a plurality of physical pages, respectively, wherein the physical pages belonging to the same physical erase unit can be independently written and simultaneously erased. For example, each physical erase unit is composed of 128 physical pages. However, it should be understood that the present invention is not limited thereto, and each physical erase unit may be composed of 64 physical pages, 256 physical pages, or any other physical pages.
In more detail, a physical erased cell is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased. The entity page is the minimum unit of programming. That is, the physical page is the smallest unit of write data. However, it should be understood that in another exemplary embodiment of the present invention, the minimum unit of the write data may be a Sector (Sector) or other size. Each physical page typically includes a data bit region and a redundancy bit region. The data bit area is used to store user data, and the redundant bit area is used to store system data (e.g., error checking and correction codes). It should be noted that in another exemplary embodiment, a physical erase unit may also refer to a physical address, a physical program unit, or a unit composed of a plurality of consecutive or non-consecutive physical addresses.
It should be noted that although the exemplary embodiment of the present invention is described with respect to the rewritable nonvolatile memory module 406 including four memory sub-modules. However, the invention is not limited thereto, and in other embodiments, the rewritable nonvolatile memory module 406 may include six, eight, or ten memory sub-modules.
Herein, a plurality of physical erase units for parallel writing at the same time may be collectively referred to as a "physical erase unit group". In this embodiment, a plurality of physical erasing units in one physical erasing unit group belong to different memory sub-modules respectively and can be written simultaneously through the data bus. Taking the example of the physical erased cell group consisting of the physical erased cell 410 (1), the physical erased cell 420 (1), the physical erased cell 430 (1) and the physical erased cell 440 (1), the memory management circuit 502 can write data into the physical erased cell 410 (1), the physical erased cell 420 (1), the physical erased cell 430 (1) and the physical erased cell 440 (1) in parallel through the data buses 316, 326, 336 and 346. Physical erase unit 410 (1), physical erase unit 420 (1), physical erase unit 430 (1) and physical erase unit 440 (1) are located in different memory sub-modules, respectively. For another example, using the physical erased cell group formed by physical erased cell 410 (0), physical erased cell 420 (0), physical erased cell 430 (0), and physical erased cell 440 (0), memory management circuit 502 may write data to physical erased cell 410 (0), physical erased cell 420 (0), physical erased cell 430 (0), and physical erased cell 440 (0) in parallel via data buses 316, 326, 336, and 346. Physical erase unit 410 (0), physical erase unit 420 (0), physical erase unit 430 (0) and physical erase unit 440 (0) are located in different memory sub-modules, respectively.
In particular, in this embodiment, for convenience of management, a plurality of physical erasing units in the same physical erasing unit group correspond to a same index code in a logical address-physical address mapping table, and different physical erasing unit groups correspond to different index codes. For example, taking the physical erased cell group formed by the physical erased cell 410 (0), the physical erased cell 420 (0), the physical erased cell 430 (0) and the physical erased cell 440 (0) as an example, the physical erased cell 410 (0), the physical erased cell 420 (0), the physical erased cell 430 (0) and the physical erased cell 440 (0) correspond to a same index code in the logical address-physical address mapping table, and the value of the index code is "001", for example. For another example, taking the physical erase unit group formed by the physical erase unit 410 (1), the physical erase unit 420 (1), the physical erase unit 430 (1) and the physical erase unit 440 (1) as an instance, the physical erase unit 410 (1), the physical erase unit 420 (1), the physical erase unit 430 (1) and the physical erase unit 440 (1) correspond to a same index code in the logical address-physical address mapping table, the value of the index code is "002", for example. Similar situation exists for other physical erased cell groups, and will not be described in detail herein.
It should be noted that, in general, to increase the writing efficiency, the memory management circuit 502 writes data to the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 via the data buses 316, 326, 336 and 346 in a parallel (parallel) manner. For example, the memory management circuit 502 writes data in parallel to the physical erase unit 410 (1), the physical erase unit 420 (1), the physical erase unit 430 (1) and the physical erase unit 440 (1) through the data buses 316, 326, 336 and 346. In the parallel writing process, it is assumed that the amount of data used for writing is exactly equal to the amount of data that can be stored in one physical erasing unit group (i.e., the amount of data that can be stored in four physical erasing units), the physical erasing unit 410 (1), the physical erasing unit 420 (1), the physical erasing unit 430 (1) and the physical erasing unit 440 (1) are generally simultaneously filled with data at a certain time point.
Assuming that the memory management circuit 502 then performs an erase operation (e.g., performs a valid data merge or other operation) on the set of physically erased cells consisting of physically erased cell 410 (1), physically erased cell 420 (1), physically erased cell 430 (1), and physically erased cell 440 (1) for reasons, the memory management circuit 502 typically performs the erase operation on physically erased cell 410 (1), physically erased cell 420 (1), physically erased cell 430 (1), and physically erased cell 440 (1) simultaneously. That is, in the prior art, in order to maintain the efficiency of parallel writing, an erase operation is usually performed in units of one physical erase unit to release the space of one physical erase unit and to be used for the subsequent parallel writing.
In this case, since four memory sub-modules in the rewritable nonvolatile memory 406 are all used to perform the erase operation, if the host system 11 continues to issue a plurality of write commands at this time, the data from the host system 11 cannot be written into the rewritable nonvolatile memory 406 and needs to be temporarily stored in the buffer memory 510. However, since the space of the buffer memory 510 is limited, the larger the execution time of the erase operation and the host system 11 continues to issue the write command, the larger the buffer memory 510 is required to temporarily store the data from the host system 11. Therefore, it is one of the problems to be solved by those skilled in the art how to avoid that all the memory sub-modules in the rewritable nonvolatile memory 406 are simultaneously used to perform the erase operation.
FIG. 7 is a flowchart of a method for erasing data according to an exemplary embodiment of the present invention.
Referring to FIG. 7, it is assumed that when an erase operation is to be performed, in step S701, the memory management circuit 502 selects a physical erase unit group (also referred to as a first physical erase unit group) from a plurality of physical erase unit groups in the rewritable nonvolatile memory 406. Then, in step S703, the memory management circuit 502 performs an erase operation on the first physically erased cell group. In particular, the first physically-erased cell group includes a plurality of physically-erased cells (also referred to as first physically-erased cells), and the number of at least one physically-erased cell (also referred to as second physically-erased cell) in the first physically-erased cells used to perform the erase operation at the same time point is different from the number of the first physically-erased cells.
It should be noted that, in the present embodiment, since the plurality of physical erasing units in one physical erasing unit group respectively belong to different memory sub-modules, in the data erasing method of the present invention, since the erasing operation is not performed on all the physical erasing units in one physical erasing unit group at the same time point, not all the memory sub-modules are used to perform the erasing operation at the same time point. At this time, while the host system 11 is still continuously issuing the write command, the data from the host system 11 can be written into the rewritable nonvolatile memory 406 without being temporarily stored in the buffer memory 510 for waiting for completion of the erase operation. Thus, the data erasing method of the present invention can avoid the problem caused by that the buffer memory 510 with larger capacity is not used and all the memory sub-modules in the rewritable nonvolatile memory 406 are used for performing the erasing operation at the same time.
The data erasing method of the present invention is described in the following embodiments.
First embodiment
Fig. 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A and 12B are schematic diagrams illustrating an example of a data erasing method according to a first example embodiment of the invention.
Referring to fig. 8A and 8B, the set of physical erased cells including the physical erased cell 410 (1), the physical erased cell 420 (1), the physical erased cell 430 (1) and the physical erased cell 440 (1) is referred to as a "first physical erased cell set", and the plurality of physical erased cells of the first physical erased cell set may be referred to as "first physical erased cells". In addition, the set of physically erased cells including physically erased cell 410 (0), physically erased cell 420 (0), physically erased cell 430 (0) and physically erased cell 440 (0) is referred to herein as a "second physically erased cell set", and the plurality of physically erased cells of the second physically erased cell set may be referred to herein as a "third physically erased cell".
In the initial state of the first embodiment, the physical erasing units 410 (0), 420 (0), 430 (0) and 440 (0) of the second physical erasing unit set have not yet stored data, while the physical erasing units 410 (1), 420 (1), 430 (1) and 440 (1) of the first physical erasing unit set store data OD 1-OD 16. As shown in FIG. 8B, the 1 st to 4 th physical program units of the physical erase unit 410 (1) store data OD1, data OD5, data OD9 and data OD13, respectively. The 1 st to 4 th physical program units of the physical erase unit 420 (1) store data OD2, data OD6, data OD10 and data OD14, respectively. The 1 st to 4 th physical program units of the physical erase unit 430 (1) store data OD3, data OD7, data OD11 and data OD15, respectively. The 1 st to 4 th physical program units of the physical erase unit 440 (1) store data OD4, data OD8, data OD12 and data OD16, respectively.
Since the physical erase unit 410 (1), the physical erase unit 420 (1), the physical erase unit 430 (1) and the physical erase unit 440 (1) have stored the data OD 1-OD 16, it is assumed that the memory management circuit 502 needs to perform the erase operation on the physical erase unit 410 (1), the physical erase unit 420 (1), the physical erase unit 430 (1) and the physical erase unit 440 (1) due to the reasons, in this embodiment, the memory management circuit 502 will perform the erase operation performed on the plurality of physical erase units in a distributed manner.
In more detail, referring to fig. 9A and 9B, it is assumed that the host system 11 issues a write command to write the data ND1 to ND4 into the rewritable nonvolatile memory 10. Since the second physical erase unit group has not stored data, the memory management circuit 502 can select the second physical erase unit group for writing. Then, the memory management circuit 502 can perform a write operation on the second physical erase unit according to the write command issued by the host system 11. For example, the memory management circuit 502 may write the data ND 1-ND 4 into the 1 st physical program unit of the physical erase unit 410 (0), the 1 st physical program unit of the physical erase unit 420 (0), the 1 st physical program unit of the physical erase unit 430 (0), and the 1 st physical program unit of the physical erase unit 440 (0) in parallel according to the write command issued by the host system 11.
At this time, the memory management circuit 502 determines whether the amount of data stored in the second physically erased cell group reaches a threshold value (also referred to as a first threshold value). In this example, it is assumed that the first threshold is one-fourth of the amount of data that can be stored in a physical erased cell group, however, the present invention is not limited to the exact value of the first threshold.
Since the second physical erase unit of FIG. 9A includes 16 physical program units, and 4 physical program units of the physical program units store data ND 1-ND 4, the memory management circuit 502 determines that the data amount stored in the second physical erase unit reaches the first threshold. At this time, the memory management circuit 502 can perform an erase operation on the physically erased cells 410 (1) (also referred to as a fourth physically erased cell) of the first physically erased cell group, as shown in FIG. 9B.
Then, referring to fig. 10A and fig. 10B, it is assumed that the host system 11 issues a write command to write the data ND5 to ND8 into the rewritable nonvolatile memory 10. The memory management circuit 502 can execute the write operation again on the second physical erase unit according to the write command issued by the host system 11. For example, the memory management circuit 502 can write the data ND 5-ND 8 into the 2 ND physical program unit of the physical erase unit 410 (0), the 2 ND physical program unit of the physical erase unit 420 (0), the 2 ND physical program unit of the physical erase unit 430 (0) and the 2 ND physical program unit of the physical erase unit 440 (0) in parallel according to the write command issued by the host system 11.
At this time, the memory management circuit 502 determines whether the amount of data stored in the second physically erased cell group reaches another threshold (also referred to as a second threshold). In this example, it is assumed that the second threshold is one-half of the amount of data that can be stored in a physical erased cell group, however, the present invention is not limited to the exact value of the second threshold.
Since the second physical erase unit group of fig. 10A includes 16 physical program units, and 8 physical program units among the physical program units store data ND 1-ND 8, the memory management circuit 502 determines that the data amount stored in the second physical erase unit group reaches the second threshold. At this time, the memory management circuit 502 can perform an erase operation on the physically erased cells 420 (1) (also referred to as a fifth physically erased cell) of the first physically erased cell group, as shown in FIG. 10B.
Then, referring to fig. 11A and 11B, it is assumed that the host system 11 issues a write command to write the data ND9 to ND12 into the rewritable nonvolatile memory 10. The memory management circuit 502 can execute the write operation again on the second physical erase unit according to the write command issued by the host system 11. For example, the memory management circuit 502 can write the data ND 9-ND 12 into the 3 rd physical program unit of the physical erase unit 410 (0), the 3 rd physical program unit of the physical erase unit 420 (0), the 3 rd physical program unit of the physical erase unit 430 (0) and the 3 rd physical program unit of the physical erase unit 440 (0) in parallel according to the write command issued by the host system 11.
At this time, the memory management circuit 502 determines whether the amount of data stored in the second physically erased cell group reaches another threshold (also referred to as a third threshold). In this example, it is assumed that the third threshold is three-fourths of the amount of data that can be stored in a physical erased cell group, however, the present invention is not limited to the exact value of the third threshold.
Since the second physical erase unit of FIG. 11A includes 16 physical program units, and 12 physical program units of the physical program units store data ND 1-ND 12, the memory management circuit 502 determines that the data amount stored in the second physical erase unit reaches the third threshold. At this time, the memory management circuit 502 can perform an erase operation on the physical erase unit 430 (1) of the first physical erase unit group, as shown in FIG. 11B.
Then, referring to fig. 12A and 12B, it is assumed that the host system 11 issues a write command to write the data ND13 to ND16 into the rewritable nonvolatile memory 10. The memory management circuit 502 can execute the write operation again on the second physical erase unit according to the write command issued by the host system 11. For example, the memory management circuit 502 can write the data ND 13-ND 16 into the 4 th physical program unit of the physical erase unit 410 (0), the 4 th physical program unit of the physical erase unit 420 (0), the 4 th physical program unit of the physical erase unit 430 (0) and the 4 th physical program unit of the physical erase unit 440 (0) in parallel according to the write command issued by the host system 11.
At this time, the memory management circuit 502 determines whether the amount of data stored in the second physically erased cell group reaches another threshold (also referred to as a fourth threshold). In this example, it is assumed that the fourth threshold is the amount of data that a physical erased cell group can store, however, the present invention is not limited to the exact value of the fourth threshold.
Since the second physical erase unit of FIG. 12A includes 16 physical program units, and 16 physical program units among the physical program units store data ND 1-ND 16, the memory management circuit 502 determines that the data amount stored in the second physical erase unit reaches the fourth threshold. At this time, the memory management circuit 502 can perform an erase operation on the physically erased cells 440 (1) of the first physically erased cell group, as shown in FIG. 12B.
In other words, in the data writing method of the present invention, when the amount of data stored in the second physical erasing unit set reaches the capacity of the second physical erasing unit set for storing data (i.e. when all 16 physical programming units in the second physical erasing unit set have been written with data), the data stored in the physical erasing unit 410 (1), the physical erasing unit 420 (1), the physical erasing unit 430 (1) and the physical erasing unit 440 (1) of the first physical erasing unit set have been erased. Therefore, after the write operation corresponding to the data ND 1-ND 16 is completed, the second physical erasing unit is restored to the idle state, so that the memory management circuit 502 can directly write in parallel to the second physical erasing unit when the host system 11 continues to issue the write command.
It should be noted that, the 1 st physical program unit of the physical erase unit 410 (0), the physical erase unit 420 (0), the physical erase unit 430 (0) and the physical erase unit 440 (0) is referred to herein as a "first physical program unit", and the 2 nd physical program unit of the physical erase unit 410 (0), the physical erase unit 420 (0), the physical erase unit 430 (0) and the physical erase unit 440 (0) is referred to herein as a "second physical program unit". In particular, during the parallel writing process, after the 1 st physical program unit of the physical erase unit 410 (0), the physical erase unit 420 (0), the physical erase unit 430 (0) and the physical erase unit 440 (0) is programmed, the 2 nd physical program unit of the physical erase unit 410 (0), the physical erase unit 420 (0), the physical erase unit 430 (0) and the physical erase unit 440 (0) can be programmed.
The above-described data ND1 to ND16 are assumed to be continuous data. That is, the data ND1 to ND16 are sequentially data ND1 to ND16. In the above example, since the physical erase unit group consisting of the physical erase unit 410 (0), the physical erase unit 420 (0), the physical erase unit 430 (0) and the physical erase unit 440 (0) is used to write the consecutive data ND 1-ND 16, the logical addresses corresponding to the data stored in the physical erase unit 410 (0), the physical erase unit 420 (0), the physical erase unit 430 (0) and the physical erase unit 440 (0) are consecutive. For example, the 1 st physical programming unit among the physical erasing unit 410 (0), the physical erasing unit 420 (0), the physical erasing unit 430 (0) and the physical erasing unit 440 (0) is used for storing the data ND 1-ND 4, and the logical addresses corresponding to the data ND 1-ND 4 are consecutive.
It should be noted that, in the process of writing the continuous data ND 1-ND 16 into the physical erasing unit 410 (0), the physical erasing unit 420 (0), the physical erasing unit 430 (0) and the physical erasing unit 440 (0) in parallel, the data stored in the physical programming units in the same physical erasing unit are discontinuous. For example, taking the physical erasing unit 430 (0) (also referred to as a seventh physical erasing unit) as an example, the logical address corresponding to the data ND3 stored in the 1 st physical programming unit of the physical erasing unit 430 (0) is discontinuous with the logical address corresponding to the data ND7 stored in the 2 ND physical programming unit of the physical erasing unit 430 (0). However, in the physical erase unit 430 (0), the 1 st physical program unit of the physical erase unit 430 (0) and the 2 nd physical program unit of the physical erase unit 430 (0) are physically arranged in series. Other physical erased cells have similar phenomena and are not described herein.
In this way, since the memory management circuit 502 does not perform the erase operation on all the physically erased cells in a physically erased cell group at the same time, not all the memory sub-modules are used to perform the erase operation at the same time. In this way, the problems of the prior art caused by simultaneously performing the erase operation on all of the memory sub-modules in the rewritable nonvolatile memory 406 can be avoided, and the capacity of the buffer memory 510 can be effectively reduced.
Second embodiment
FIG. 13 is a diagram illustrating an example of a data erasing method according to the second exemplary embodiment of the present invention. It should be noted that, in the second embodiment of the present invention, the memory management circuit 502 adjusts the sequence of performing the write operation on the plurality of physically erased cells in a physically erased cell group, so that the physically erased cells are not fully written with data at different times. In particular, the physically erased cells that were first fully written with data can be used to perform the erase operation first, thereby avoiding the problems associated with prior art simultaneous erase operations for all of the memory sub-modules in the rewritable nonvolatile memory 406.
In detail, referring to FIG. 13, it is assumed that the first physical erase unit is written. Assume that the host system 11 issues a write instruction to write the data IDs 1 to 8 into the rewritable nonvolatile memory 10. The memory management circuit 502 can perform a write operation on the first physical erase unit according to the write command issued by the host system 11. In particular, unlike the prior art method using parallel writing, in the second embodiment of the present invention, the memory management circuit 502 adjusts the order of performing the write operations on the plurality of first physical erase units in the first erase unit. For example, the memory management circuit 502 may obtain the order in which write operations are performed on a plurality of physically erased cells in a physically erased cell group according to an algorithm or a lookup table. In particular, the present invention is not limited to the order of writing operations and the manner in which the order is generated and obtained.
Here, it is assumed that the memory management circuit 502 sequentially performs "physical erasing unit 410 (1), physical erasing unit 420 (1), physical erasing unit 430 (1), physical erasing unit 440 (1), physical erasing unit 420 (1) and physical erasing unit 420 (1)" according to the order of the write operations obtained by the algorithm or the lookup table. The memory management circuit 502 performs a write operation to the physical erase unit 410 (1), the physical erase unit 420 (1), the physical erase unit 430 (1) and the physical erase unit 440 (1) according to the write sequence and the write command. In more detail, the memory management circuit 502 writes the data ID1 to the physical erasing unit 410 (1), the data ID2 to the physical erasing unit 420 (1), the data ID3 to the physical erasing unit 410 (1), the data ID4 to the physical erasing unit 420 (1), the data ID5 to the physical erasing unit 430 (1), the data ID6 to the physical erasing unit 440 (1), the data ID7 to the physical erasing unit 420 (1) and the data ID8 to the physical erasing unit 420 (1) according to the above-mentioned writing sequence, and the result is shown in FIG. 13.
That is, in the second embodiment of the present invention, when the memory space of a physical erasing unit (e.g., the physical erasing unit 420 (1)) in a physical programming unit group is fully written, at least one other physical erasing unit in the physical programming unit group has available memory space. In particular, the physically erased cells that were first fully written with data can be used to perform the erase operation first, thereby avoiding the problems associated with prior art simultaneous erase operations for all of the memory sub-modules in the rewritable nonvolatile memory 406.
In view of the foregoing, in the data erasing method, the memory control circuit unit and the memory storage device of the present invention, since the erasing operation is not performed on all the physically erased cells in a physically erased cell group at the same time point, not all the memory sub-modules are used to perform the erasing operation at the same time point. At this time, when the host system still continues to issue the write command, the data from the host system can be written into the rewritable nonvolatile memory without being temporarily stored in the buffer memory for waiting for the completion of the erase operation. Therefore, the data erasing method of the invention can avoid the problem caused by that all the memory submodules in the rewritable nonvolatile memory are simultaneously used for executing the erasing operation without using a buffer memory with larger capacity.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims (27)

1. A data erasing method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of physical erase unit groups, each physical erase unit group of the plurality of physical erase unit groups having a plurality of physical erase units, the data erasing method comprising:
Selecting a first physical erase unit group from the plurality of physical erase unit groups;
performing an erase operation on the first physical erase unit group, wherein the first physical erase unit group includes a plurality of first physical erase units, and a number of at least one second physical erase unit among the plurality of first physical erase units used to perform the erase operation at the same time point is different from a number of the plurality of first physical erase units;
performing a write operation on a second physical erase unit of the plurality of physical erase unit groups according to at least one write command, wherein the second physical erase unit group comprises a plurality of third physical erase units;
when the data amount stored in the second entity erasing unit group reaches a first threshold value, executing the step of executing the erasing operation on the first entity erasing unit group so as to execute the erasing operation on a fourth entity erasing unit in the plurality of first entity erasing units; and
when the amount of data stored in the second physically-erased cell group reaches a second threshold, performing the step of performing the erase operation on the first physically-erased cell group to perform the erase operation on a fifth physically-erased cell of the plurality of first physically-erased cells,
Wherein the first threshold is less than the second threshold.
2. The data erasing method of claim 1, wherein the data stored in the plurality of first physical erase units of the first physical erase unit has been erased when the amount of data stored in the second physical erase unit reaches a capacity of the second physical erase unit available for storing data.
3. The data erasing method of claim 1, wherein the rewritable nonvolatile memory module comprises a plurality of memory sub-modules, the plurality of memory sub-modules are respectively connected with a memory control circuit unit through a plurality of channels, and the plurality of physical erasing units of each of the plurality of physical erasing unit groups respectively belong to different memory sub-modules of the plurality of memory sub-modules.
4. The data erasing method of claim 3, wherein the memory control circuit unit performs the write operation on the plurality of third physical erase units in the second physical erase unit group through the plurality of channels to write a plurality of data in parallel in the plurality of third physical erase units.
5. The data erase method of claim 1, wherein prior to performing the erase operation on the first physical erase cell group, the method further comprises:
adjusting the order in which the write operations are performed on the plurality of first physical erase units; and
and executing the write operation on the plurality of first entity erasing units according to the write sequence and the at least one write instruction so that at least one sixth entity erasing unit in the plurality of first entity erasing units has available storage space when the storage space of the second entity erasing unit is full.
6. The method of claim 1, wherein the plurality of physical erased cells in the same physical erased cell group correspond to the same index code in a logical address-physical address mapping table.
7. The method of claim 1, wherein each of the plurality of first physical erase units in the first physical erase unit group comprises a first physical program unit and a second physical program unit,
when the first physical programming units of each of the plurality of first physical erasing units are programmed, the second physical programming units of each of the plurality of first physical erasing units can be programmed.
8. The method of claim 1, wherein each of the plurality of first physical erase units in the first physical erase unit group comprises a first physical program unit,
when the first physical erasing unit group is written with continuous data, a plurality of logic addresses corresponding to a plurality of data stored by the first physical programming unit of the first physical erasing unit in the first physical erasing unit group are continuous.
9. The method of claim 1, wherein each of the plurality of first physical erase units in the first physical erase unit group comprises a first physical program unit and a second physical program unit,
when the first physical erasing unit group is written with continuous data, the logical address corresponding to the data stored by the first physical programming unit of the seventh physical erasing unit in the first physical erasing unit group is discontinuous with the logical address corresponding to the data stored by the second physical programming unit of the seventh physical erasing unit, and the first physical programming unit and the second physical programming unit of the seventh physical erasing unit are physically and continuously arranged.
10. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical erase unit groups, each physical erase unit group of the plurality of physical erase unit groups having a plurality of physical erase units, the memory control circuit unit comprising:
the host interface is used for being electrically connected to a host system;
a memory interface electrically connected to the rewritable non-volatile memory module;
a memory management circuit electrically connected to the host interface and the memory interface,
wherein the memory management circuit is configured to select a first physically erased cell group from the plurality of physically erased cell groups,
wherein the memory management circuit is further configured to perform an erase operation on the first set of physically-erased cells, wherein the first set of physically-erased cells includes a plurality of first physically-erased cells, and at least one second physically-erased cell of the plurality of first physically-erased cells used to perform the erase operation at a same point in time is different from the number of the plurality of first physically-erased cells,
Wherein the memory management circuit is further configured to perform a write operation on a second physical erase unit among the plurality of physical erase unit groups according to at least one write command, wherein the second physical erase unit group includes a plurality of third physical erase units,
when the data amount stored in the second physically-erased cell group reaches a first threshold value, the memory management circuit is further configured to perform the operation of performing the erase operation on the first physically-erased cell group to perform the erase operation on a fourth physically-erased cell of the plurality of first physically-erased cells,
when the data amount stored in the second physically-erased cell group reaches a second threshold value, the memory management circuit is further configured to perform the operation of performing the erase operation on the first physically-erased cell group to perform the erase operation on a fifth physically-erased cell of the plurality of first physically-erased cells,
wherein the first threshold is less than the second threshold.
11. The memory control circuit unit of claim 10, wherein the data stored in the plurality of first physical erase units of the first physical erase unit has been erased when the amount of data stored in the second physical erase unit reaches a capacity available for storing data for the second physical erase unit.
12. The memory control circuit unit of claim 10, wherein the rewritable non-volatile memory module comprises a plurality of memory sub-modules respectively connected to the memory management circuit through a plurality of channels, the plurality of physical erase units of each of the plurality of physical erase unit groups respectively belonging to different ones of the plurality of memory sub-modules.
13. The memory control circuit unit of claim 12, wherein the memory management circuit performs the write operation on the plurality of third physical erase units in the second physical erase unit group through the plurality of channels to write a plurality of data in parallel in the plurality of third physical erase units.
14. The memory control circuit unit of claim 10, wherein prior to performing the erase operation on the first set of physical erase units,
the memory management circuit is also configured to adjust an order in which the write operations are performed on the plurality of first physical erase units,
the memory management circuit is further configured to perform the write operation on the plurality of first physical erase units according to a write sequence and the at least one write command such that at least one sixth physical erase unit of the plurality of first physical erase units has a usable memory space when the memory space of the second physical erase unit is full.
15. The memory control circuit unit of claim 10, wherein among the plurality of physically-erased cells, the plurality of physically-erased cells in a same physically-erased cell group correspond to a same index code in a logical address-to-physical address mapping table.
16. The memory control circuit unit of claim 10, wherein each of the plurality of first physical erase units in the first physical erase unit group comprises a first physical program unit and a second physical program unit,
when the first physical programming units of each of the plurality of first physical erasing units are programmed, the second physical programming units of each of the plurality of first physical erasing units can be programmed.
17. The memory control circuit unit of claim 10, wherein each of the plurality of first physical erase units in the first physical erase unit group comprises a first physical program unit,
when the first physical erasing unit group is written with continuous data, a plurality of logic addresses corresponding to a plurality of data stored by the first physical programming unit of the first physical erasing unit in the first physical erasing unit group are continuous.
18. The memory control circuit unit of claim 10, wherein each of the plurality of first physical erase units in the first physical erase unit group comprises a first physical program unit and a second physical program unit,
when the first physical erasing unit group is written with continuous data, the logical address corresponding to the data stored by the first physical programming unit of the seventh physical erasing unit in the first physical erasing unit group is discontinuous with the logical address corresponding to the data stored by the second physical programming unit of the seventh physical erasing unit, and the first physical programming unit and the second physical programming unit of the seventh physical erasing unit are physically and continuously arranged.
19. A memory storage device, comprising:
the connection interface unit is used for being electrically connected to the host system;
a rewritable non-volatile memory module comprising a plurality of physical erase unit groups, each physical erase unit group of the plurality of physical erase unit groups having a plurality of physical erase units; and
A memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is used for selecting a first physically erased cell group from the plurality of physically erased cell groups,
wherein the memory control circuit unit is further configured to perform an erase operation on the first physical erase unit group, wherein the first physical erase unit group includes a plurality of first physical erase units, and at least one second physical erase unit of the plurality of first physical erase units used to perform the erase operation at the same time point is different from the plurality of first physical erase units,
wherein the memory control circuit unit is further configured to perform a write operation on a second physical erase unit among the plurality of physical erase unit groups according to at least one write command, wherein the second physical erase unit group includes a plurality of third physical erase units,
when the data amount stored in the second physical erasing unit group reaches a first threshold value, the memory control circuit unit is further configured to perform the step of performing the erasing operation on the first physical erasing unit group to perform the erasing operation on a fourth physical erasing unit of the plurality of first physical erasing units,
When the data amount stored in the second physical erase unit group reaches a second threshold value, the memory control circuit unit is further configured to perform the step of performing the erase operation on the first physical erase unit group to perform the erase operation on a fifth physical erase unit of the plurality of first physical erase units,
wherein the first threshold is less than the second threshold.
20. The memory storage device of claim 19, wherein the data stored in the plurality of first physical erase units of the first physical erase unit has been erased when the amount of data stored in the second physical erase unit reaches a capacity available for storing data for the second physical erase unit.
21. The memory storage device of claim 19, wherein the rewritable non-volatile memory module comprises a plurality of memory sub-modules respectively connected to memory control circuit units through a plurality of channels, the plurality of physical erase units of each of the plurality of physical erase unit groups respectively belonging to different ones of the plurality of memory sub-modules.
22. The memory storage device of claim 21, wherein the memory control circuit unit performs the write operation on the plurality of third physical erase units in the second physical erase unit group through the plurality of channels to write a plurality of data in parallel in the plurality of third physical erase units.
23. The memory storage device of claim 19, wherein prior to performing the erase operation on the first physical set of erased cells,
the memory control circuit unit is also configured to adjust an order in which the write operations are performed on the plurality of first physical erase units,
the memory control circuit unit is further configured to perform the write operation on the plurality of first physical erase units according to a write sequence and the at least one write command such that at least one sixth physical erase unit of the plurality of first physical erase units has a usable memory space when the memory space of the second physical erase unit is full.
24. The memory storage device of claim 19, wherein among the plurality of physically erased cells, the plurality of physically erased cells in a same physically erased cell group correspond to a same index code in a logical address-to-physical address mapping table.
25. The memory storage device of claim 19, wherein each of the plurality of first physical erase units in the first set of physical erase units comprises a first physical program unit and a second physical program unit,
when the first physical programming units of each of the plurality of first physical erasing units are programmed, the second physical programming units of each of the plurality of first physical erasing units can be programmed.
26. The memory storage device of claim 19, wherein each of the plurality of first physical erase units in the first set of physical erase units comprises a first physical program unit,
when the first physical erasing unit group is written with continuous data, a plurality of logic addresses corresponding to a plurality of data stored by the first physical programming unit of the first physical erasing unit in the first physical erasing unit group are continuous.
27. The memory storage device of claim 19, wherein each of the plurality of first physical erase units in the first set of physical erase units comprises a first physical program unit and a second physical program unit,
When the first physical erasing unit group is written with continuous data, the logical address corresponding to the data stored by the first physical programming unit of the seventh physical erasing unit in the first physical erasing unit group is discontinuous with the logical address corresponding to the data stored by the second physical programming unit of the seventh physical erasing unit, and the first physical programming unit and the second physical programming unit of the seventh physical erasing unit are physically and continuously arranged.
CN201910627492.XA 2019-07-12 2019-07-12 Data erasing method, memory control circuit unit and memory storage device Active CN112216329B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910627492.XA CN112216329B (en) 2019-07-12 2019-07-12 Data erasing method, memory control circuit unit and memory storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910627492.XA CN112216329B (en) 2019-07-12 2019-07-12 Data erasing method, memory control circuit unit and memory storage device

Publications (2)

Publication Number Publication Date
CN112216329A CN112216329A (en) 2021-01-12
CN112216329B true CN112216329B (en) 2023-11-07

Family

ID=74048522

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910627492.XA Active CN112216329B (en) 2019-07-12 2019-07-12 Data erasing method, memory control circuit unit and memory storage device

Country Status (1)

Country Link
CN (1) CN112216329B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5949716A (en) * 1997-04-16 1999-09-07 Invox Technology Look-ahead erase for sequential data storage
US6055188A (en) * 1997-04-30 2000-04-25 Kabushiki Kaishi Toshiba Nonvolatile semiconductor memory device having a data circuit for erasing and writing operations
CN102890617A (en) * 2011-07-18 2013-01-23 群联电子股份有限公司 Memory control method, memory controller and memory storage device
CN104732153A (en) * 2013-12-18 2015-06-24 群联电子股份有限公司 Data erasing method, storage control circuit unit and storage storing device
CN109308930A (en) * 2017-07-28 2019-02-05 群联电子股份有限公司 Method for writing data, memorizer control circuit unit and memory storage apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5949716A (en) * 1997-04-16 1999-09-07 Invox Technology Look-ahead erase for sequential data storage
US6055188A (en) * 1997-04-30 2000-04-25 Kabushiki Kaishi Toshiba Nonvolatile semiconductor memory device having a data circuit for erasing and writing operations
CN102890617A (en) * 2011-07-18 2013-01-23 群联电子股份有限公司 Memory control method, memory controller and memory storage device
CN104732153A (en) * 2013-12-18 2015-06-24 群联电子股份有限公司 Data erasing method, storage control circuit unit and storage storing device
CN109308930A (en) * 2017-07-28 2019-02-05 群联电子股份有限公司 Method for writing data, memorizer control circuit unit and memory storage apparatus

Also Published As

Publication number Publication date
CN112216329A (en) 2021-01-12

Similar Documents

Publication Publication Date Title
CN111078149A (en) Memory management method, memory storage device and memory control circuit unit
CN109491588B (en) Memory management method, memory control circuit unit and memory storage device
US20170242597A1 (en) Wear leveling method, memory control circuit unit and memory storage device
CN106951186B (en) Data programming method, memory storage device and memory control circuit unit
CN111258505B (en) Data merging method of flash memory, control circuit unit and storage device
CN111078146B (en) Memory management method, memory storage device and memory control circuit unit
TWI717751B (en) Data writing method, memory control circuit unit and memory storage device
CN106959818B (en) Data writing method, memory control circuit unit and memory storage device
CN109273033B (en) Memory management method, memory control circuit unit and memory storage device
CN109032957B (en) Memory management method, memory control circuit unit and memory storage device
CN107132989B (en) Data programming method, memory control circuit unit and memory storage device
CN112463018B (en) Instruction transmission method, memory control circuit unit and memory storage device
TWI711048B (en) Value adjusting method, memory control circuit unit and memory storage device for flash memory
CN112216329B (en) Data erasing method, memory control circuit unit and memory storage device
CN109522236B (en) Memory management method, memory control circuit unit and memory storage device
TWI769386B (en) Data erasing method, memory control circuit unit and memory storage device
CN108958640B (en) Memory management method, memory control circuit unit and memory storage device
CN112099727B (en) Data writing method, memory control circuit unit and memory storage device
CN111240602B (en) Data sorting method of flash memory, control circuit unit and storage device
US11144244B2 (en) Command transmitting method with temporary storing commands by memory interfaces for rewritable non-volatile memory modules, memory control circuit unit and memory storage device
CN117632042B (en) Memory management method, memory storage device and memory control circuit unit
CN114527941B (en) Memory control method, memory storage device and memory control circuit unit
CN114115739B (en) Memory management method, memory storage device and memory control circuit unit
CN112181859B (en) Effective data merging method, memory control circuit unit and memory device
CN111435287B (en) Memory control method, memory storage device and memory control circuit unit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant