CN109308930A

CN109308930A - Method for writing data, memorizer control circuit unit and memory storage apparatus

Info

Publication number: CN109308930A
Application number: CN201710628850.XA
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2017-07-28
Filing date: 2017-07-28
Publication date: 2019-02-05
Anticipated expiration: 2037-07-28
Also published as: CN109308930B

Abstract

The present invention proposes a kind of method for writing data, memorizer control circuit unit and memory storage apparatus.The described method includes: the first data requesting instructions of transmission obtain multiple data to host system, and the multiple data are to be arranged in host system according to a sequence；According to the first data requesting instructions, the first data in the multiple data are obtained from host system, and after obtaining the first data, connects the second data obtained in the multiple data from host system；The correspondent entity page on one first word-line is write first data into multiple word-lines；And another pair that second data are written into the multiple word-line on one second word-line is answered into physical page, wherein the first word-line belongs to the first memory submodule in multiple memory submodules, second word-line belongs to the second memory submodule in the multiple memory submodule, and first data and second data are discontinuously to arrange in the sequence.

Description

Method for writing data, memorizer control circuit unit and memory storage apparatus

Technical field

The present invention relates to a kind of method for writing data, memorizer control circuit unit and memory storage apparatus.

Background technique

Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data It is non-volatile, power saving, small in size, and without characteristics such as mechanical structures, so being very suitable to be built into above-mentioned illustrated various In portable multimedia device.

In general, reproducible nonvolatile memorizer module includes a plurality of word-line, and on each word-line Storage unit can form multiple physical pages to storing data.The Memory Controller of memory storage apparatus is usually According in data reproducible nonvolatile memorizer module to be stored in initial position and final position, assign instruction to Host system is to obtain to be intended to store the continuous data between this initial position and final position.

In particular, memory storage apparatus usually requires largely slow when to a plurality of word-line being written in parallel Storage space is rushed to keep in the continuous data from host system.Also, when executing sequencing, Memory Controller can be from Select the data of the correspondent entity page on each word-line to be stored in buffer memory size, and will be selected more A data are respectively written into the physical page on each word-line, to achieve the effect that be written in parallel.

However, above-mentioned process would generally consume the space of a large amount of buffer storage, therefore, if memory storage dress The buffer storage without configuration large capacity is set, parallel write-in can not be just executed, and influences write-in efficiency.Base this, how can reach To data parallel writing speed and reduce the usage amount of buffer storage, the target that field technical staff is endeavoured thus.

Summary of the invention

The present invention, which provides a kind of present invention and provides a kind of method for writing data, memorizer control circuit unit and memory, to deposit Storage device can assign instruction to obtain discontinuous to host system and be respectively stored in multiple numbers on different word-lines According to excessive resource can be expended to avoid the temporary a large amount of continuous data of memory storage apparatus whereby, and can achieve The technical effect that the physical page on multiple word-lines is written simultaneously.

The present invention provides a kind of method for writing data, is used for reproducible nonvolatile memorizer module, described to make carbon copies Formula non-volatile memory module includes the multiple memory submodules for being respectively and electrically connected to memorizer control circuit unit, institute Stating multiple memory submodules includes a plurality of word-line, multiple storage lists among a plurality of word-line on same word-line Member forms multiple physical pages, and the method for writing data includes: to transmit the first data requesting instructions to host system to obtain Multiple data, and the multiple data are to be arranged in host system according to a sequence；According to the first data requesting instructions, from Host system obtains the first data in multiple data；After obtaining the first data, connects from host system and obtain multiple data In the second data；It is write first data into the multiple word-line on one first word-line via one first data/address bus The correspondent entity page；And second data are written into the multiple word-line one via one second data/address bus Another pair on two word-lines answers physical page, wherein first depositing of belonging in the multiple memory submodule of the first word-line Reservoir submodule, the second word-line belong to the second memory submodule in the multiple memory submodule, and the first data And second data be discontinuously to arrange in the sequence.

In one embodiment of this invention, the first data include the first subdata and the second subdata, the second data packet Third subdata and the 4th subdata are included, wherein on the first word-line write first data into the multiple word-line The correspondent entity page the step of include: that sequentially the first subdata and the second subdata are respectively written into the first word-line The first instance page and the second instance page.Second data are wherein written to the second character into the multiple word-line The step of another pair on line answers physical page includes: that sequentially third subdata and the 4th subdata are respectively written into second Third physical page and the 4th physical page on word-line.

In one embodiment of this invention, wherein third subdata and the 4th subdata are respectively written into sequentially After the step of third physical page and four physical pages on two word-lines, the method for writing data is further included: being passed Send the second data requesting instructions to host system；According to the second data requesting instructions, the multiple data are obtained from host system In third data and the 4th data；And sequentially by third data the 5th subdata and the 6th subdata write respectively Enter to the 5th physical page and the 6th physical page on first word-line, and sequentially by the 7th in the 4th data Subdata and the 8th subdata are respectively written into the 7th physical page and the 8th physical page on the second word-line, wherein Third data and the 4th data are discontinuous in the sequence of the multiple data.

In one embodiment of this invention, the first data and third data are to connect in the sequence of the multiple data Continuous, the second data and the 4th data are continuous in the sequence of the multiple data.

In one embodiment of this invention, the second data and third data are to connect in the sequence of the multiple data It is continuous.

In one embodiment of this invention, the first data requesting instructions are to indicate that host system transmission is intended to be stored in first First data of the correspondent entity page on word-line and the another pair for being intended to be stored on the second word-line answer physical page Second data.

The present invention provides a kind of memorizer control circuit unit, for controlling reproducible nonvolatile memorizer module, Wherein reproducible nonvolatile memorizer module includes multiple memory submodules, and the multiple memory submodule includes more Word-line, and multiple storage units among a plurality of word-line on same word-line form multiple physical pages, institute Stating memorizer control circuit unit includes: host interface, memory interface and memory management circuitry.Host interface electrically connects It is connected to host system.Memory interface is electrically connected to reproducible nonvolatile memorizer module, and the multiple memory Submodule is respectively and electrically connected to memory interface.Memory management circuitry is electrically connected to host interface and memory connects Mouthful.Memory management circuitry is to execute following running: the first data requesting instructions of transmission are to host system to obtain multiple numbers According to, and the multiple data are to be arranged in host system according to a sequence；According to the first data requesting instructions, from host system System obtains the first data in multiple data；After obtaining the first data, the obtained in multiple data from host system is connected Two data；The correspondence on one first word-line is write first data into the multiple word-line via one first data/address bus Physical page；And one second character is written into the multiple word-line in second data via one second data/address bus Another pair on line answers physical page, wherein the first word-line belongs to of the first memory in the multiple memory submodule Module, the second word-line belong to the second memory submodule in the multiple memory submodule, and the first data and Two data are discontinuously to arrange in the sequence.

In one embodiment of this invention, the first data include the first subdata and the second subdata, the second data packet Third subdata and the 4th subdata are included, wherein in the first word-line write first data into the multiple word-line On the correspondent entity page running in, the first subdata and the second subdata are sequentially respectively written by memory management circuitry The first instance page and the second instance page on to the first word-line.It is written by the second data to the multiple word-line In the second word-line on another pair answer in the running of physical page, memory management circuitry sequentially by third subdata and 4th subdata is respectively written into the third physical page and the 4th physical page on the second word-line.

In one embodiment of this invention, third subdata and the 4th subdata are respectively written into the second word sequentially Third physical page on first line and after the running of the 4th physical page, memory management circuitry transmits the second request of data It instructs to host system.Memory management circuitry obtains the multiple data according to the second data requesting instructions, from host system In third data and the 4th data.Memory management circuitry is sequentially by the 5th subdata and the 6th son in third data Data are respectively written into the 5th physical page and the 6th physical page on first word-line, and sequentially by the 4th number The 7th subdata and the 8th subdata in are respectively written into the 7th physical page and the 8th on the second word-line in fact The body page, wherein third data and the 4th data are discontinuous in the sequence of the multiple data.

The present invention provides a kind of memory storage apparatus, comprising: connecting interface unit, type nonvolatile Module and memorizer control circuit unit.Connecting interface unit is electrically connected to host system.Duplicative is non-volatile to be deposited Memory modules include multiple memory submodules, and the multiple memory submodule includes a plurality of word-line and a plurality of character Multiple storage units among line on same word-line form multiple physical pages.Memorizer control circuit unit is electrically connected To connecting interface unit and reproducible nonvolatile memorizer module, and the multiple memory submodule is electrically connected To memorizer control circuit unit.Memorizer control circuit unit is to execute following runnings: the first data requesting instructions of transmission To host system to obtain multiple data, and the multiple data are to be arranged in host system according to a sequence；According to One data requesting instructions obtain the first data in multiple data from host system；After obtaining the first data, connect from host System obtains the second data in multiple data；It writes first data into via one first data/address bus to the multiple word-line In the correspondent entity page on one first word-line；And second data are written to described via one second data/address bus Another pair in multiple word-lines on one second word-line answers physical page, wherein the first word-line belongs to the multiple memory First memory submodule in submodule, the second word-line belong to of the second memory in the multiple memory submodule Module, and the first data and the second data are discontinuously to arrange in the sequence.

In one embodiment of this invention, the first data include the first subdata and the second subdata, the second data packet Third subdata and the 4th subdata are included, wherein in the first word-line write first data into the multiple word-line On the correspondent entity page running in, memorizer control circuit unit sequentially distinguishes the first subdata and the second subdata It is written to the first instance page and the second instance page on the first word-line.It is written by the second data to the multiple word Another pair on the second word-line in first line is answered in the running of physical page, and memorizer control circuit unit is sequentially by third Data and the 4th subdata are respectively written into the third physical page and the 4th physical page on the second word-line.

In one embodiment of this invention, third subdata and the 4th subdata are respectively written into the second word sequentially Third physical page on first line and after the running of the 4th physical page, memorizer control circuit unit transmits the second data Request instruction is to host system.Memorizer control circuit unit is according to the second data requesting instructions, described in host system acquirement Third data and the 4th data in multiple data.Memorizer control circuit unit is sequentially by the 5th subnumber in third data Accordingly and the 6th subdata is respectively written into the 5th physical page and the 6th physical page on first word-line, and Sequentially by the 4th data the 7th subdata and the 8th subdata be respectively written into the 7th physical page on the second word-line Face and the 8th physical page

Face, wherein third data and the 4th data are discontinuous in the sequence of the multiple data.

Passed through based on above-mentioned, of the invention method for writing data, memorizer control circuit unit and memory storage apparatus Instruction is assigned to obtain discontinuous to host system and be intended to the multiple data being stored on different word-lines respectively, it is possible thereby to It avoids the temporary a large amount of continuous data of memory storage apparatus and expends excessive resource, and can achieve while to multiple words The technical effect that physical page on first line is written.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.

Detailed description of the invention

Fig. 1 is host system, memory storage apparatus and input shown by an exemplary embodiment according to the present invention/defeated The schematic diagram of (I/O) device out；

Fig. 2 is host system shown by another exemplary embodiment according to the present invention, memory storage apparatus and I/O dress The schematic diagram set；

Fig. 3 is the signal of host system and memory storage apparatus shown by another exemplary embodiment according to the present invention Figure；

Fig. 4 is the schematic block diagram of memory storage apparatus shown by an exemplary embodiment according to the present invention；

Fig. 5 is the schematic block diagram of memorizer control circuit unit shown by an exemplary embodiment according to the present invention；

Fig. 6 is management reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention Schematic diagram；

Fig. 7 is the flow chart of method for writing data shown by an exemplary embodiment according to the present invention；

Fig. 8 A to Fig. 8 C is that multiple data are respectively written into multiple shown by an exemplary embodiment according to the present invention The schematic diagram of physical page on word-line；

Fig. 9 is that multiple data are respectively written into multiple word-lines shown by another exemplary embodiment according to the present invention On physical page schematic diagram；

Figure 10 is the flow chart of method for writing data shown by another exemplary embodiment according to the present invention.

Drawing reference numeral explanation:

30,10: memory storage apparatus

31,11: host system

110: system bus

111: processor

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: motherboard

201: portable disk

202: storage card

203: solid state hard disk

204: radio memory storage device

205: GPS module

206: network interface card

207: radio transmitting device

208: keyboard

209: screen

210: loudspeaker

32:SD card

33:CF card

34: embedded storage device

341: embedded multi-media card

342: embedded type multi-core piece sealed storage device

402: connecting interface unit

404: memorizer control circuit unit

406: reproducible nonvolatile memorizer module

502: memory management circuitry

504: host interface

506: memory interface

508: error checking and correcting circuit

510: buffer storage

512: electric power management circuit

310: first memory submodule

320: second memory submodule

312: the first block face of first memory submodule

314: the second block face of first memory submodule

316,326: data/address bus

322: the first block face of second memory submodule

324: the second block face of second memory submodule

410 (0)~410 (N), 420 (0)~420 (N), 430 (0)~430 (N), 440 (0)~440 (N): entity is erased Unit

Step S701: the first data requesting instructions of transmission obtain multiple data, and the multiple data to host system It is the step of being arranged according to a sequence in host system

Step S703: according to the first data requesting instructions, obtaining the first data in the multiple data from host system, And after obtaining the first data, the step of the second data in the multiple data are obtained from host system is connected

Step S705: the step of writing first data into the correspondent entity page on the first word-line

Step S707: the step of answering physical page to another pair on the second word-line is written into the second data

WL1, WL2, WL3, WL4: word-line

P1(0)、P1(1)、P1(2)、P1(3)、P1(4)、P1(5)、P2(0)、P2(1)、P2(2)、P2(3)、P2(4)、P2 (5), P3 (0), P3 (1), P3 (2), P3 (3), P3 (4), P3 (5), P4 (0), P4 (1), P4 (2), P4 (3), P4 (4), P4 (5): Physical page

DATA0、DATA1、DATA2、DATA3、DATA4、DATA5、DATA6、DATA7、DATA8、DATA9、DATA10、 DATA11、DATA12、DATA13、DATA14、DATA15、DATA16、DATA17、DATA18、DATA19、DATA20、DATA21、 DATA22, DATA23: subdata

Step S1001: the first data requesting instructions of transmission obtain multiple data, and the multiple data to host system It is the step of being arranged according to a sequence in host system

Step S1003: according to the first data requesting instructions, the first number in the multiple data is obtained from host system According to, and after obtaining the first data, connect the step of the second data in the multiple data are obtained from host system

Step S1005: sequentially the first subdata of the first data and the second subdata are respectively written into the first character The step of first instance page and the second instance page on line

Step S1007: sequentially by the second data third subdata and the 4th subdata be respectively written into the second word The step of third physical page and four physical pages on first line

Step S1009: the step of transmitting the second data requesting instructions to host system

Step S1011: according to the second data requesting instructions, the third data in the multiple data are obtained from host system And the step of four data

Step S1013: sequentially by third data the 5th subdata and the 6th subdata be respectively written into the first word The 5th physical page and the 6th physical page on first line, and sequentially by the 7th subdata and the 8th in the 4th data The step of subdata is respectively written into the 7th physical page and eight physical pages on the second word-line

Specific embodiment

In general, memory storage apparatus (also known as, storage system) includes duplicative non-volatile memories Device module (rewritable non-volatile memory module) and controller (also known as, control circuit).It is commonly stored Device storage device is used together with host system, so that host system can write data into memory storage apparatus or from depositing Data are read in reservoir storage device.

Fig. 1 is host system, memory storage apparatus and input shown by an exemplary embodiment according to the present invention/defeated The schematic diagram of (I/O) device out.Fig. 2 is that host system shown by another exemplary embodiment according to the present invention, memory are deposited The schematic diagram of storage device and I/O device.

Fig. 1 and Fig. 2 are please referred to, host system 11 generally comprises processor 111, random access memory (random Access memory, RAM) 112, read-only memory (read only memory, ROM) 113 and data transmission interface 114.Place Reason device 111, random access memory 112, read-only memory 113 and data transmission interface 114 are all electrically connected to system bus (system bus)110。

In this exemplary embodiment, host system 11 is by 10 electricity of data transmission interface 114 and memory storage apparatus Property connection.For example, host system 11 can store data to memory storage apparatus 10 via data transmission interface 114 or from depositing Data are read in reservoir storage device 10.In addition, host system 11 is electrically connected by system bus 110 and I/O device 12. For example, output signal can be sent to I/O device 12 via system bus 110 or received from I/O device 12 defeated by host system 11 Enter signal.

In this exemplary embodiment, processor 111, random access memory 112, read-only memory 113 and data transmission Interface 114 may be provided on the motherboard 20 of host system 11.The number of data transmission interface 114 can be one or more.It is logical Data transmission interface 114 is crossed, motherboard 20 can be electrically connected to memory storage apparatus 10 via wired or wireless way.It deposits Reservoir storage device 10 can be for example portable disk 201, storage card 202, solid state hard disk (Solid State Drive, SSD) 203 Or radio memory storage device 204.Radio memory storage device 204 can be for example close range wireless communication (Near Field Communication, NFC) memory storage apparatus, radio facsimile (WiFi) memory storage apparatus, bluetooth (Bluetooth) memory storage apparatus or low-power consumption bluetooth memory storage apparatus (for example, iBeacon) etc. are with various wireless Memory storage apparatus based on mechanics of communication.In addition, motherboard 20 can also be electrically connected to entirely by system bus 110 Ball positioning system (Global Positioning System, GPS) module 205, network interface card 206, radio transmitting device 207, the various I/O device such as keyboard 208, screen 209, loudspeaker 210.For example, motherboard 20 can pass through in an exemplary embodiment 207 access wireless memory storage apparatus 204 of radio transmitting device.

In an exemplary embodiment, mentioned host system is substantially to cooperate with memory storage apparatus to store The arbitrary system of data.Although host system is explained with computer system, however, Fig. 3 is in above-mentioned exemplary embodiment The schematic diagram of host system and memory storage apparatus shown by another exemplary embodiment according to the present invention.Referring to figure 3., In another exemplary embodiment, host system 31 is also possible to digital camera, video camera, communication device, audio player, video The systems such as player or tablet computer, and memory storage apparatus 30 can be its used safe digital (Secure Digital, SD) card 32, compact flash (Compact Flash, CF) block 33 or embedded storage device 34 etc. it is various non-volatile Property memory storage apparatus.Embedded storage device 34 includes embedded multi-media card (embedded Multi Media Card, eMMC) 341 and/or embedded type multi-core piece encapsulate (embedded Multi Chip Package, eMCP) storage device Embedded storage device on all types of substrates that memory module is directly electrically connected to host system such as 342.

Fig. 4 is the schematic block diagram of memory storage apparatus shown by an exemplary embodiment according to the present invention.

Referring to figure 4., memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.

Connecting interface unit 402 is to be electrically connected to host system 11 for memory storage apparatus 10.In this example reality It applies in example, connecting interface unit 402 is to meet high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, and it is compatible to flash non-volatile memory (NVM express) Interface standard.Specifically, flash non-volatile memory interface standard is led between a kind of host system and memory device The agreement of news, define buffer interface between the controller of memory storage apparatus and the operating system of host system, Instruction set and function collection, and optimized by the interface standard to memory storage apparatus, to promote based on PCIe interface The data access speed and message transmission rate of memory storage apparatus.However, in another exemplary embodiment, connecting interface list Member 402 can also meet other suitable standards.In addition, connecting interface unit 402 can be with memorizer control circuit unit 404 Be encapsulated in a chip or connecting interface unit 402 be laid in one include memorizer control circuit unit 404 chip Outside.

Memorizer control circuit unit 404 is to execute multiple logic gates or control with hardware pattern or firmware pattern implementation System instructs and carries out writing for data in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The running such as enter, read and erase.

Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404 and uses The data being written with host system 11.Reproducible nonvolatile memorizer module 406 can be single-order storage unit (Single Level Cell, SLC) NAND type flash memory module is (that is, can store 1 bit in a storage unit Flash memory module), multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory module is (that is, one The flash memory module of 2 bits can be stored in a storage unit), most rank storage unit (Triple Level Cell, TLC) NAND type flash memory module (that is, flash memory module that 3 bits can be stored in a storage unit), other Flash memory module or other memory modules with the same characteristics.

Each of reproducible nonvolatile memorizer module 406 storage unit is (following also known as to face with voltage Boundary's voltage) change store one or more bits.Specifically, the control grid (control of each storage unit Gate) there is an electric charge capture layer between channel.By bestowing a write-in voltage to controlling grid, thus it is possible to vary charge benefit is caught The amount of electrons of layer, and then change the critical voltage of storage unit.This change storage unit critical voltage operation be also known as " Data are written to storage unit " or " sequencing (programming) storage unit ".With the change of critical voltage, can make carbon copies Each of formula non-volatile memory module 406 storage unit has multiple storage states.It can by bestowing reading voltage To judge a storage unit is which storage state belonged to, one or more positions that this storage unit is stored are obtained whereby Member.

In this exemplary embodiment, the storage unit of reproducible nonvolatile memorizer module 406 can constitute multiple realities Body programmed cell, and these entity program units can constitute multiple entity erased cells.Specifically, same character Storage unit on line can form one or more entity program units.If each storage unit can store 2 or more positions Member, then the entity program unit on same word-line can at least be classified as lower entity program unit and upper entity program Change unit.For example, the least significant bit (Least Significant Bit, LSB) of a storage unit is to belong to lower entity journey Sequence unit, and the most significant bit first (Most Significant Bit, MSB) of a storage unit is to belong to entity journey Sequence unit.In general, in MLC NAND type flash memory, the writing speed of lower entity program unit can be greater than upper The reliability of the writing speed of entity program unit and/or lower entity program unit is above entity program unit Reliability.

In this exemplary embodiment, entity program unit is the minimum unit of sequencing.That is, entity program unit is The minimum unit of data is written.For example, entity program unit is physical page (page) or entity fan (sector).If real Body programmed cell is physical page, then these entity program units generally include data bit element area and redundancy (redundancy) bit area.Data bit element area is fanned comprising multiple entities, and to store user's data, and redundancy bit area uses With memory system data (for example, error correcting code etc. manages data).In this exemplary embodiment, data bit element area includes 32 Entity fan, and the size of entity fan is 512 bit groups (byte, B).However, in other exemplary embodiments, data bit element It also may include 8,16 or the more or fewer entity fans of number in area, and the size of each entity fan is also possible to more It is big or smaller.On the other hand, entity erased cell is the minimum unit erased.Also that is, each entity erased cell contains minimum The storage unit of number being erased together.For example, entity erased cell is physical blocks (block).

Fig. 5 is the schematic block diagram of memorizer control circuit unit shown by an exemplary embodiment according to the present invention.

Referring to figure 5., memorizer control circuit unit 404 includes memory management circuitry 502, host interface 504 and deposits Memory interface 506.

Overall operation of the memory management circuitry 502 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 502, has multiple control instructions, and when memory storage apparatus 10 operates, these control instructions can quilt It executes the running such as to carry out the write-in of data, read and erase.It is equivalent when illustrating the operation of memory management circuitry 502 below In the operation for illustrating memorizer control circuit unit 404.

In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with firmware pattern.For example, Memory management circuitry 502 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 10 operates, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.

In another exemplary embodiment, the control instruction of memory management circuitry 502 can be also stored in procedure code pattern The specific region of reproducible nonvolatile memorizer module 406 is (for example, be exclusively used in storage system data in memory module System area) in.In addition, memory management circuitry 502 have microprocessor unit (not shown), read-only memory (not shown) and Random access memory (not shown).In particular, this read-only memory has boot code (boot code), and work as memory When control circuit unit 404 is enabled, microprocessor unit can first carry out this boot code, and will to be stored in duplicative non-volatile Control instruction in property memory module 406 is loaded into the random access memory of memory management circuitry 502.Later, micro- Processor unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.

In addition, the control instruction of memory management circuitry 502 can also a hardware pattern in another exemplary embodiment Implementation.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write circuit, storage Device reading circuit, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write circuit, storage Device reading circuit, memory erase circuit and data processing circuit is electrically connected to microcontroller.Storage Unit Management circuit To manage storage unit or its group of reproducible nonvolatile memorizer module 406.Memory write circuit is to right Reproducible nonvolatile memorizer module 406 assigns write instruction sequence to write data into duplicative is non-volatile and deposit In memory modules 406.Memory reading circuitry is to assign reading sequence of instructions to reproducible nonvolatile memorizer module 406 Column are to read data from reproducible nonvolatile memorizer module 406.Memory erases circuit to non-to duplicative Volatile 406 assign erase instruction sequence with by data from reproducible nonvolatile memorizer module 406 It erases.Data processing circuit is intended to be written data to reproducible nonvolatile memorizer module 406 and from can to handle The data read in manifolding formula non-volatile memory module 406.Write instruction sequence reads instruction sequence and sequence of instructions of erasing Column can be distinctly including one or more procedure codes or instruction code and to indicate that reproducible nonvolatile memorizer module 406 is held Row corresponding write-in such as reads and erases at the operation.In an exemplary embodiment, memory management circuitry 502 can also be assigned Other kinds of instruction sequence indicates to execute corresponding operation to reproducible nonvolatile memorizer module 406.

Host interface 504 is electrically connected to memory management circuitry 502 and to receive and identification host system 11 The instruction and data transmitted.That is, the instruction that host system 11 is transmitted can be passed with data by host interface 504 It send to memory management circuitry 502.In this exemplary embodiment, host interface 504 is to be compatible to SATA standard.However, it is necessary to It is appreciated that the invention is not limited thereto, host interface 504 can also be compatible to PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS mark Standard, CF standard, IDE standard or other suitable data transmission standards.

Memory interface 506 is electrically connected to memory management circuitry 502 and non-volatile to access duplicative Property memory module 406.That is, the data for being intended to be written to reproducible nonvolatile memorizer module 406 can be via depositing Memory interface 506 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.Specifically, if storage Device management circuit 502 will access reproducible nonvolatile memorizer module 406, and memory interface 506 can transmit corresponding finger Enable sequence.For example, the reading that these instruction sequences may include the write instruction sequence of instruction write-in data, instruction reading data refers to Enable sequence, instruction erase data erase instruction sequence and to indicate various storage operations (for example, change read electricity Press level or execute garbage collection operation etc.) corresponding instruction sequence.These instruction sequences are, for example, by memory pipe Reason circuit 502 generates and is sent to reproducible nonvolatile memorizer module 406 by memory interface 506.These refer to Enabling sequence may include one or more signals, or the data in bus.These signals or data may include instruction code or program Code.For example, will include the information such as identification code, the storage address of reading in reading instruction sequence.

In an exemplary embodiment, memorizer control circuit unit 404 further includes error checking and correcting circuit 508, delays Rush memory 510 and electric power management circuit 512.

Error checking and correcting circuit 508 are electrically connected to memory management circuitry 502 and to execute wrong inspection It looks into and correct operation is to ensure the correctness of data.Specifically, when memory management circuitry 502 is received from host system 11 When to write instruction, error checking can be the corresponding error correction of data generation of this corresponding write instruction with correcting circuit 508 Code (error correcting code, ECC) and/or error checking code (error detecting code, EDC), and deposit Reservoir manages circuit 502 and the data of this corresponding write instruction can be written with corresponding error correcting code and/or error checking code Into reproducible nonvolatile memorizer module 406.Later, when memory management circuitry 502 is non-volatile from duplicative The corresponding error correcting code of this data and/or error checking code can be read simultaneously when reading data in memory module 406, and Error checking and correcting circuit 508 can execute mistake to read data according to this error correcting code and/or error checking code Inspection and correct operation.

Buffer storage 510 is electrically connected to memory management circuitry 502 and is configured to temporarily store from host system 11 data and instruction or the data from reproducible nonvolatile memorizer module 406.Electric power management circuit 512 is electricity Property is connected to memory management circuitry 502 and the power supply to control memory storage apparatus 10.

Fig. 6 is the summary of reproducible nonvolatile memorizer module shown by the first exemplary embodiment according to the present invention Block diagram.

Fig. 6 is please referred to, reproducible nonvolatile memorizer module 406 includes first memory submodule 310 and second Memory submodule 320.For example, first memory submodule 310 and second memory submodule 320 are respectively brilliant for memory Grain (die).First memory submodule 310 has the first block face 312 and the second block face 314 and second memory submodule Block 320 has the first block face 322 and the second block face 324.First block face 312 of first memory submodule 310 has Second block face 314 of entity erased cell 410 (0)~410 (N), first memory submodule 310 has entity erased cell First block face 322 of 420 (0)~420 (N), second memory submodule 320 has entity erased cell 430 (0)~430 (N), and the second block face 324 of second memory submodule 320 has entity erased cell 440 (0)~440 (N).

For example, first memory submodule 310 is total separately by independent data with second memory submodule 320 Line 316 and data/address bus 326 are electrically connected to memorizer control circuit unit 404.Base this, memory management circuitry 502 can be with Data are written by data/address bus 316 and data/address bus 326 to first memory submodule 310 (parallel) mode in parallel With second memory submodule 320.

However, it is necessary to be appreciated that, in another exemplary embodiment of the present invention, first memory submodule 310 and second Memory submodule 320 also can be only electrically connected by 1 data/address bus and memorizer control circuit unit 404.Here, storage Device management circuit 502 can staggeredly data be written by single data/address bus to first memory (interleave) mode Module 310 and second memory submodule 320.

In particular, first memory submodule 310 and second memory submodule 320 can respectively include a plurality of character Line, and multiple storage units on same word-line will form multiple physical pages.First memory submodule 310 and second Each entity erased cell of memory submodule 320 is respectively provided with most physical pages, smears wherein belonging to the same entity Except the physical page of unit can be written independently and simultaneously be erased.For example, each entity erased cell is by 128 realities The body page is formed.However, it is necessary to be appreciated that, the invention is not limited thereto, and each entity erased cell is can be by 64 entities The page, 256 physical pages or any other a physical page are formed.

In more detail, entity erased cell is the minimum unit erased.Also that is, each entity erased cell contains minimum The storage unit of number being erased together.Physical page is the minimum unit of sequencing.That is, physical page is write-in data Minimum unit.However, it is necessary to be appreciated that, in another exemplary embodiment of the present invention, the minimum unit that data are written can also It is sector (Sector) or other sizes.Each physical page generally includes data bit element area and redundancy bit area.Data bit element Data of the area to store user, and data (for example, error checking and correcting code) of the redundancy bit area to storage system. It is noted that an entity erased cell can also refer to a physical address, an entity in another exemplary embodiment Programmed cell is made of multiple continuous or discontinuous physical address.

It is noted that although exemplary embodiment of the present invention is non-to include the duplicative of 2 memory submodules It is described for volatile 406, however, the present invention is not limited thereto.

In this exemplary embodiment, memory management circuitry 502 can assign data requesting instructions to host system 11.This Data requesting instructions are to indicate that host system 11 transmits one in reproducible nonvolatile memorizer module 406 to be stored in In the first data and reproducible nonvolatile memorizer module to be stored in 406 of the correspondent entity page on word-line Another pair on another word-line answers the second data of physical page.Wherein, the above-mentioned word-line for the first data to be written is Belong to a first memory submodule, above-mentioned for the word-line of the second data to be written is to belong to a second memory submodule, First memory submodule is different from second memory submodule.First data and the second data can be multiple continuous datas Among two mutual discrete dates.That is, in this exemplary embodiment, memory management circuitry 502 can be not required to according to Data script puts in order to obtain all data, but the position that can be actually stored according to data in physical page It sets, assigns data requesting instructions and be written to host system 11 with directly obtaining corresponding data.Whereby, memory management Circuit 502 can not need to obtain all data and all data are temporarily stored in after buffer storage 510 to count again According to select, but data needed for directly obtaining write-in at present to host system 11 therefore can reduce buffer storage 510 Usage amount.

Fig. 7 is the flow chart of method for writing data shown by an exemplary embodiment according to the present invention.

Fig. 7 is please referred to, in step s 701, memory management circuitry 502 transmits at least one first data requesting instructions extremely For host system 11 to obtain the first data in multiple data and the second data, the multiple data are basis in host system One sequence is arranged, and the sequence of the first data and the second data in the multiple data is discontinuous arrangement.Wherein institute The first data requesting instructions are stated to indicate that host system 11 transmits the correspondent entity page for being intended to be stored on the first word-line First data and the another pair for being intended to be stored on the second word-line answer the second data of physical page.In step S703, deposit Reservoir manages circuit 502 according to the first data requesting instructions, obtains the first data in multiple data from host system 11, and After obtaining the first data, the second data obtained in the multiple data from host system 11 are connected.Later, in step S705 In, memory management circuitry 502 writes first data into the correspondent entity page on the first word-line.Finally in step S707 In, the second data are written to another pair on the second word-line and answer physical page by memory management circuitry 502.In particular, institute It states the first word-line and belongs to a first memory submodule, second word-line belongs to a second memory submodule, and first Memory submodule is different from second memory submodule.

Illustrate the data writing process of this case method for writing data with more detailed embodiment below.

Fig. 8 A to Fig. 8 C is that multiple data are respectively written into multiple shown by an exemplary embodiment according to the present invention The schematic diagram of physical page on word-line.

Fig. 8 A to Fig. 8 C is please referred to, in this exemplary embodiment, it is assumed that reproducible nonvolatile memorizer module 406 is Three-dimensional (Three-Dimension, 3D) NAND type flash memory module, and reproducible nonvolatile memorizer module 406 In each word-line on storage unit can form four physical pages.As shown in Figure 8 A, duplicative is non-volatile deposits It for example may include the word-line WL1 (also known as, the first word-line) for belonging to a first memory submodule in memory modules 406 And belong to the word-line WL2 (also known as, the second word-line) of a second memory submodule.Storage list on word-line WL1 Member forms physical page P1 (0)~P1 (3), and the storage unit on word-line WL2 forms physical page P2 (0)~P2 (3).

It should be noted that it is assumed herein that memory management circuitry 502 by multiple continuous datas be written to word-line WL1 with And in the physical page on word-line WL2.The multiple continuous data include the first data, the second data, third data and 4th data, and putting in order for the multiple data is sequentially the first data, third data, the second data and the 4th number According to.Wherein, wherein the first data packet enclosed tool data DATA0 and subdata DATA1, third data packet enclosed tool data DATA2 with And subdata DATA3, the second data packet enclosed tool data DATA4 and subdata DATA5, the 4th data packet enclosed tool data DATA6 And subdata DATA7.That is, putting in order for subdata is sequentially subdata from the perspective of with subdata DATA0, subdata DATA1, subdata DATA2, subdata DATA3, subdata DATA4, subdata DATA5, subdata DATA6 And subdata DATA7.

When memory management circuitry 502 will write in parallel the physical page on word-line WL1 and word-line WL2 Fashionable, memory management circuitry 502 can transmit an at least data requesting instructions (also known as, the first data requesting instructions) to host System 11 transmits physical page P1 (0) and physical page P1 (1) on word-line WL1 to be stored in requesting host system 11 Data and physical page P2 (0) and physical page P2 (1) on word-line WL2 to be stored in data.

Then, Fig. 8 B is please referred to, memory management circuitry 502 can be according to the first above-mentioned data requesting instructions, from host System 11 obtains the first data and the second data in multiple continuous datas.First data include being intended to be written to word-line WL1 On physical page P1 (0) in subdata DATA0 (also known as, the first subdata) and be intended to be written to word-line WL1 Subdata DATA1 (also known as, the second subdata) in physical page P1 (1).Second data include word-line WL2 to be written in On physical page P2 (0) in subdata DATA4 (also known as, third subdata) and word-line WL2 to be written on Subdata DATA5 (also known as, the 4th subdata) in physical page P2 (1).That is, the first data requesting instructions are to use To obtain mutual discontinuous first data and the second data in multiple continuous datas.Later, memory management circuitry 502 can Sequentially subdata DATA0 and subdata DATA1 to be respectively written into physical page P1 (0) (also known as, first instance page Face) and physical page P1 (1) (also known as, the second instance page).Similarly, memory management circuitry 502 can sequentially by Subdata DATA4 and subdata DATA5 is respectively written into physical page P2 (0) (also known as, third physical page) and reality Body page P2 (1) (also known as, the 4th physical page).

Later, memory management circuitry 502 can be resent to few data requesting instructions (also known as, the second data are asked Ask instruction) to host system 11 with requesting host system 11 transmit physical page P1 (2) on word-line WL1 to be stored in and The physical page P2 (2) and physical page P2 (3) in data and word-line WL2 to be stored in physical page P1 (3) In data.

Fig. 8 C is please referred to, memory management circuitry 502 can be according to the second above-mentioned data requesting instructions, from host system 11 obtain the third data and the 4th data in multiple continuous datas.Third data include to be written on word-line WL1 The subdata DATA2 (also known as, the 5th subdata) of physical page P1 (2) and the physical page to be written on word-line WL1 The subdata DATA3 (also known as, the 6th subdata) of face P1 (3).4th data include the entity to be written on word-line WL2 The subdata DATA6 (also known as, the 7th subdata) of page P2 (2) and the physical page to be written on word-line WL2 The subdata DATA7 (also known as, the 8th subdata) of P2 (3).That is, the second data requesting instructions are to obtain more Mutual discontinuous third data and the 4th data in a continuous data.Later, memory management circuitry 502 can sequentially will be sub Data DATA2 and subdata DATA3 is respectively written into physical page P1 (2) (also known as, the 5th physical page) and entity Page P1 (3) (also known as, the 6th physical page).Similarly, memory management circuitry 502 can be sequentially by subdata DATA6 And subdata DATA7 is respectively written into physical page P2 (2) (also known as, the 7th physical page) and physical page P2 (3) In (also known as, the 8th physical page).

In particular, after via above-mentioned write-in, be stored in the physical page P1 (2) of least significant end in word-line WL (1)~ The third data of P1 (3) are to connect the number of physical page P2 (0)~P2 (1) second for being stored in and originating in word-line WL (2) According to.That is, data can be stored in order in word-line WL1 and word-line WL2 after via above-mentioned write operation.

It is to be noted that the present invention is not limited to the number of the physical page on a word-line.In other realities It applies in example, a word-line may include more or fewer physical pages.

Fig. 9 is that multiple data are respectively written into multiple word-lines shown by another exemplary embodiment according to the present invention On physical page schematic diagram.

Fig. 9 is please referred to, in this exemplary embodiment, it is assumed that reproducible nonvolatile memorizer module 406 is three-dimensional (Three-Dimension, 3D) NAND type flash memory module, and in reproducible nonvolatile memorizer module 406 Storage unit on each word-line forms six physical pages.As shown in figure 9, reproducible nonvolatile memorizer module It for example may include word-line WL1, word-line WL2, word-line WL3 and word-line WL4 in 406.Storage on word-line WL1 Unit forms physical page P1 (0)~P1 (5), and the storage unit on word-line WL2 forms physical page P2 (0)~P2 (5), word Storage unit on first line WL3 forms physical page P3 (0)~P3 (5), and the storage unit on word-line WL4 forms entity Page P4 (0)~P4 (5).Wherein, word-line WL1, word-line WL2, word-line WL3 and word-line WL4 are belonging respectively to difference Memory submodule.For example, word-line WL1 belongs to a first memory submodule, word-line WL2 belongs to a second memory Submodule, word-line WL3 belong to a third memory submodule and word-line WL4 belongs to one the 4th memory submodule.

When memory management circuitry 502 will be on word-line WL1, word-line WL2, word-line WL3 and word-line WL4 When physical page is written in parallel, memory management circuitry 502 can transmit an at least data requesting instructions to host system 11 are transmitted data in physical page P1 (0)~P1 (1) on word-line WL1 to be stored in requesting host system 11, are intended to deposit Storage is in the data in the physical page P2 (0) on word-line WL2~P2 (1), the physical page P3 on word-line WL3 to be stored in (0) data in physical page P4 (0)~P4 (1) in data and word-line WL4 to be stored in~P3 (1).

Memory management circuitry 502 can be according to the data requesting instructions for being sent to host system 11, from host system 11 Obtain be intended to the subdata DATA0 that is written into the physical page P1 (0) on word-line WL1~P1 (1) and subdata DATA1, It is intended to be written subdata DATA6 and subdata DATA7 into the physical page P2 (0) on word-line WL2~P2 (1), is intended to write Enter subdata DATA12 and subdata DATA13 in the physical page P3 (0) on word-line WL3~P3 (1) and is intended to be written The subdata DATA18 and subdata DATA19 in physical page P4 (0)~P4 (1) on word-line WL4.

Later, memory management circuitry 502 can sequentially by subdata DATA0, subdata DATA1, subdata DATA6, Subdata DATA7, subdata DATA12, subdata DATA13, subdata DATA18 and subdata DATA19 be respectively written into Physical page P1 (0), physical page P1 (1), physical page P2 (0), physical page P2 (1), physical page P3 (0), physical page In face P3 (1), physical page P4 (0) and physical page P4 (1).

Later, memory management circuitry 502 can be resent to few data requesting instructions to host system 11 to request to lead The data in physical page P1 (2)~P1 (3) on the transmission of machine system 11 word-line WL1 to be stored in, word-line to be stored in The data in physical page P2 (2)~P2 (3) on WL2, the physical page P3 (2) on word-line WL3 to be stored in~P3 (3) In data and the data in physical page P4 (2)~P4 (3) on word-line WL4 to be stored in.

Memory management circuitry 502 can be according to the data requesting instructions for being sent to host system 11, from host system 11 Obtain be intended to the subdata DATA2 that is written into the physical page P1 (2) on word-line WL1~P1 (3) and subdata DATA3, It is intended to be written subdata DATA8 and subdata DATA9 into the physical page P2 (2) on word-line WL2~P2 (3), is intended to write Enter subdata DATA14 and subdata DATA15 into the physical page P3 (2) on word-line WL3~P3 (3) and is intended to write Enter the subdata DATA20 and subdata DATA21 into the physical page P4 (2) on word-line WL4~P4 (3).

Later, memory management circuitry 502 can sequentially by subdata DATA2, subdata DATA3, subdata DATA8, Subdata DATA9, subdata DATA14, subdata DATA15, subdata DATA20 and subdata DATA21 be respectively written into Physical page P1 (2), physical page P1 (3), physical page P2 (2), physical page P2 (3), physical page P3 (2), physical page In face P3 (3), physical page P4 (2) and physical page P4 (3).

Later, memory management circuitry 502 can be resent to few data requesting instructions to host system 11 to request The data in physical page P1 (4)~P1 (5) on the transmission of host system 11 word-line WL1 to be stored in, character to be stored in The data in physical page P2 (4)~P2 (5) on line WL2, physical page P3 (4)~P3 on word-line WL3 to be stored in (5) data in physical page P4 (4)~P4 (5) in data and word-line WL4 to be stored in.

Memory management circuitry 502 can be according to the data requesting instructions for being sent to host system 11, from host system 11 Obtain be intended to the subdata DATA4 that is written into the physical page P1 (4) on word-line WL1~P1 (5) and subdata DATA5, It is intended to the subdata DATA10 being written into the physical page P2 (4) on word-line WL2~P2 (5) and subdata DATA11, is intended to The subdata DATA16 into the physical page P3 (4) on word-line WL3~P3 (5) and subdata DATA17 and desire is written Subdata DATA22 and subdata DATA23 into the physical page P4 (4) on word-line WL4~P4 (5) is written.

Later, memory management circuitry 502 can sequentially by subdata DATA4, subdata DATA5, subdata DATA10, Subdata DATA11, subdata DATA16, subdata DATA17, subdata DATA22 and subdata DATA23 be respectively written into Physical page P1 (4), physical page P1 (5), physical page P2 (4), physical page P2 (5), physical page P3 (4), physical page In face P3 (5), physical page P4 (4) and physical page P4 (5).

In particular, the ordinal relation between above-mentioned subdata is sequentially subdata DATA0, subdata DATA1, subnumber According to DATA2, subdata DATA3, subdata DATA4, subdata DATA5, subdata DATA6, subdata DATA7, subdata DATA8, subdata DATA9, subdata DATA10, subdata DATA11, subdata DATA12, subdata DATA13, subdata DATA14, subdata DATA15, subdata DATA16, subdata DATA17, subdata DATA18, subdata DATA19, subnumber According to DATA20, subdata DATA21, subdata DATA22 and subdata DATA23.By above-mentioned content it is found that memory pipe Reason circuit 502 can obtain discrete date from host system 11 each word-line to be written every time.In addition, by Fig. 9 Content it is found that after having executed above-mentioned write operation, physical page P2 (0)~P2 (1) for being stored on word-line WL2 Subdata DATA6 and DATA7 is to be connected in physical page P1 (4)~P1 (5) subdata being stored on word-line WL1 DATA4 and DATA5.The physical page P3 (0) being stored on word-line WL3~P3 (1) subdata DATA12 and DATA13 is It is connected in physical page P2 (4)~P2 (5) the subdata DATA10 and DATA11 being stored on word-line WL2.It is stored in word Physical page P4 (0)~P4 (1) subdata DATA18 and DATA19 on first line WL4 are to be connected in be stored in word-line WL3 On physical page P3 (4)~P3 (5) subdata DATA16 and DATA17.

Figure 10 is please referred to, in step S1001, memory management circuitry 502 transmits the first data requesting instructions to host For system 11 to obtain the first data in multiple data and the second data, the multiple data are suitable according to one in host system Sequence is arranged, and the sequence of the first data and the second data in the multiple data is discontinuous arrangement.Wherein the first number According to request instruction to indicate the host system transmission first to the correspondent entity page being stored on the first word-line Data and another pair to be stored on the second word-line answer the second data of physical page.In the step s 1003, it stores Device manages circuit 502 according to the first data requesting instructions, obtains the first data in the multiple data from host system 11, and And after obtaining the first data, the second data obtained in the multiple data from host system 11 are connected.In step S1005 In, the first subdata of the first data and the second subdata are sequentially respectively written into the first word by memory management circuitry 502 The first instance page and the second instance page on first line.In step S1007, memory management circuitry 502 is sequentially by Third subdata and the 4th subdata in two data are respectively written into the third physical page and on the second word-line Four physical pages.In step S1009, memory management circuitry 502 transmits the second data requesting instructions to host system 11.? In step S1011, memory management circuitry 502 is obtained in multiple data according to the second data requesting instructions from host system 11 Third data and the 4th data, wherein the sequence of third data and the 4th data in the multiple data be do not connect It is continuous, the sequence of the first data and third data in the multiple data be it is continuous, the second data and the 4th data exist Sequence in the multiple data is continuous.In step S1013, memory management circuitry 502 sequentially will be in third data The 5th subdata and the 6th subdata be respectively written into the 5th physical page and the 6th physical page on the first word-line Face, and sequentially by the 4th data the 7th subdata and the 8th subdata be respectively written into the 7th on the second word-line Physical page and the 8th physical page.In particular, first word-line belongs to a first memory submodule, described second Word-line belongs to a second memory submodule, and first memory submodule is different from second memory submodule.

It should be noted that, it is assumed that the 5th physical page and the 6th physical page on the first word-line are the first word-line On most latter two physical page, then the 5th physical page and the 6th physical page institute in the sequence in the multiple data Second data of storage can be connected in two physical pages originated on the second word-line (that is, above-mentioned third physical page And four physical pages) the third data that are stored.

In conclusion method for writing data of the invention, memorizer control circuit unit and memory storage apparatus can be with Instruction is assigned to obtain discontinuous to host system and be respectively stored in multiple data on different word-lines, can be kept away whereby Exempt from the temporary a large amount of continuous data of memory storage apparatus and expend excessive resource, and can achieve while to multiple characters The technical effect that physical page on line is written.

Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention Subject to range ought be defined depending on appended claims.

Claims

1. a kind of method for writing data is used for reproducible nonvolatile memorizer module, the duplicative is non-volatile to be deposited Memory modules include the multiple memory submodules for being respectively and electrically connected to memorizer control circuit unit, the multiple memory Submodule includes a plurality of word-line, and multiple storage units among a plurality of word-line on same word-line form multiple realities The body page, which is characterized in that the method for writing data includes:

Transmission at least one first data requesting instructions obtain multiple data to host system, and the multiple data are in the master It is to be arranged according to a sequence in machine system；

According to first data requesting instructions, the first data in the multiple data are obtained from the host system；

After obtaining first data, the second data obtained in the multiple data from the host system are connected；

Corresponding in fact on the first word-line is written into the multiple word-line via the first data/address bus in first data The body page, first word-line belong to the first memory submodule in the multiple memory submodule；And

Second data are written via the second data/address bus to another pair into the multiple word-line on the second word-line Physical page is answered, second word-line belongs to the second memory submodule in the multiple memory submodule,

Wherein first data and second data are discontinuously to arrange in the sequence.

2. method for writing data according to claim 1, which is characterized in that first data include the first subdata with And second subdata, second data include third subdata and the 4th subdata,

First data are wherein written to the correspondent entity page to the first word-line described in the multiple word-line The step of face includes:

Sequentially first subdata and second subdata are respectively written into real to first on first word-line The body page and the second instance page,

Described another pair to the second word-line described in the multiple word-line wherein is written in second data should be real The step of body page includes:

Sequentially the third subdata and the 4th subdata are respectively written into real to the third on second word-line The body page and the 4th physical page.

3. method for writing data according to claim 2, wherein sequentially by the third subdata and the described 4th Subdata is respectively written into the step of third physical page and four physical page to second word-line Later, which is characterized in that the method for writing data further include:

At least one second data requesting instructions are transmitted to the host system；

According to second data requesting instructions, the third data and in the multiple data are obtained from the host system Four data；And

Sequentially by the third data the 5th subdata and the 6th subdata be respectively written into first word-line The 5th physical page and the 6th physical page, and sequentially by the 4th data the 7th subdata and the 8th son Data are respectively written into the 7th physical page and the 8th physical page on second word-line,

Wherein the third data described in the sequence of the multiple data and the 4th data are discontinuous.

4. method for writing data according to claim 3, which is characterized in that described in the sequence of the multiple data One data and the third data are continuous, the second data described in the sequence of the multiple data and the 4th number According to being continuous.

5. method for writing data according to claim 4, which is characterized in that described in the sequence of the multiple data Two data and the third data are continuous.

6. method for writing data according to claim 1, which is characterized in that first data requesting instructions are to indicate Host system transmission be intended to be stored in the correspondent entity page on first word-line first data and The described another pair for being intended to be stored on second word-line answers second data of physical page.

7. a kind of memorizer control circuit unit, for controlling reproducible nonvolatile memorizer module, wherein described can answer The formula non-volatile memory module of writing includes multiple memory submodules, and the multiple memory submodule includes a plurality of character Line, and multiple storage units among a plurality of word-line on same word-line form multiple physical pages, feature exists In the memorizer control circuit unit includes:

Host interface is electrically connected to host system；

Memory interface is electrically connected to the reproducible nonvolatile memorizer module, and the multiple memory Submodule is respectively and electrically connected to the memory interface；

Memory management circuitry is electrically connected to the host interface and the memory interface,

Wherein the memory management circuitry is to transmit at least one first data requesting instructions to the host system to obtain Multiple data, and the multiple data are to be arranged in the host system according to a sequence,

Wherein the memory management circuitry is more to obtain institute from the host system according to first data requesting instructions The first data in multiple data are stated,

Wherein the memory management circuitry is more to connect from the host system and obtain institute after obtaining first data The second data in multiple data are stated,

Wherein the memory management circuitry via the first data/address bus more being written first data to the multiple The correspondent entity page in word-line on the first word-line, and first word-line belongs in the multiple memory submodule First memory submodule,

Wherein the memory management circuitry via the second data/address bus more being written second data to the multiple Another pair in word-line on the second word-line answers physical page, and second word-line belongs to the multiple memory submodule Second memory submodule in block,

8. memorizer control circuit unit according to claim 7, which is characterized in that first data include the first son Data and the second subdata, second data include third subdata and the 4th subdata,

First data are wherein written to the correspondent entity page to the first word-line described in the multiple word-line In the running in face,

The memory management circuitry more to sequentially by first subdata and second subdata be respectively written into The first instance page and the second instance page on first word-line,

Described another pair to the second word-line described in the multiple word-line wherein is written in second data should be real In the running of the body page,

The memory management circuitry more to sequentially by the third subdata and the 4th subdata be respectively written into Third physical page and the 4th physical page on second word-line.

9. memorizer control circuit unit according to claim 8, which is characterized in that sequentially by the third subdata And the 4th subdata is respectively written into the third physical page and the described 4th to second word-line in fact After the running of the body page,

The memory management circuitry more to transmit at least one second data requesting instructions to the host system,

The memory management circuitry from the host system more to obtain described more according to second data requesting instructions Third data and the 4th data in a data,

The memory management circuitry is more to sequentially by the 5th subdata and the 6th subdata point in the third data It Xie Ru not be to the 5th physical page and the 6th physical page on first word-line, and sequentially by the 4th data In the 7th subdata and the 8th subdata be respectively written into the 7th physical page and the 8th on second word-line Physical page,

10. memorizer control circuit unit according to claim 9, which is characterized in that in the sequence of the multiple data Described in the first data and the third data be continuous, the second data described in the sequence of the multiple data and institute It is continuous for stating the 4th data.

11. memorizer control circuit unit according to claim 10, which is characterized in that in the sequence of the multiple data Described in the second data and the third data be continuous.

12. memorizer control circuit unit according to claim 7, which is characterized in that first data requesting instructions To indicate that the host system transmission is intended to be stored in described first of the correspondent entity page on first word-line Data and the described another pair for being intended to be stored on second word-line answer second data of physical page.

13. a kind of memory storage apparatus characterized by comprising

Connecting interface unit, is electrically connected to host system；

Reproducible nonvolatile memorizer module, including multiple memory submodules, the multiple memory submodule include Multiple storage units among a plurality of word-line and a plurality of word-line on same word-line form multiple physical pages；With And

Memorizer control circuit unit is electrically connected to the connecting interface unit and the type nonvolatile Module, and the multiple memory submodule is respectively and electrically connected to the memorizer control circuit unit,

Wherein the memorizer control circuit unit to transmit at least one first data requesting instructions to the host system with Multiple data are obtained, and the multiple data are to be arranged in the host system according to a sequence,

Wherein the memorizer control circuit unit from the host system more to take according to first data requesting instructions The first data in the multiple data are obtained,

Wherein the memorizer control circuit unit is more to after obtaining first data, connecting takes from the host system The second data in the multiple data are obtained,

Wherein the memorizer control circuit unit via the first data/address bus more being written first data to described The correspondent entity page in multiple word-lines on the first word-line, and first word-line belongs to the multiple memory submodule First memory submodule in block,

Wherein the memorizer control circuit unit via the second data/address bus more being written second data to described Another pair in multiple word-lines on the second word-line answers physical page, and second word-line belongs to the multiple memory Second memory submodule in submodule,

14. memory storage apparatus according to claim 13, which is characterized in that first data include the first subnumber Accordingly and the second subdata, the second data include third subdata and the 4th subdata,

The memorizer control circuit unit more sequentially to write first subdata and second subdata respectively Enter to the first instance page and the second instance page on first word-line,

The memorizer control circuit unit more sequentially to write the third subdata and the 4th subdata respectively Enter to the third physical page and the 4th physical page on second word-line.

15. memory storage apparatus according to claim 14, which is characterized in that sequentially by the third subdata with And the 4th subdata is respectively written into the third physical page and the 4th entity to second word-line After the running of the page,

The memorizer control circuit unit more to transmit at least one second data requesting instructions to the host system,

The memorizer control circuit unit is more to obtain institute from the host system according to second data requesting instructions The third data and the 4th data in multiple data are stated,

The memorizer control circuit unit is more to sequentially by the 5th subdata and the 6th subnumber in the third data According to being respectively written into the 5th physical page and the 6th physical page on first word-line, and sequentially by the described 4th The 7th subdata and the 8th subdata in data be respectively written on second word-line the 7th physical page and 8th physical page,

16. memory storage apparatus according to claim 15, which is characterized in that the institute in the sequence of the multiple data It states the first data and the third data is continuous, the second data described in the sequence of the multiple data and described Four data are continuous.

17. memory storage apparatus according to claim 16, which is characterized in that second data and the third Sequence of the data in the multiple data is mutually continuous.

18. memory storage apparatus according to claim 13, which is characterized in that first data requesting instructions to Indicate that the host system transmission is intended to be stored in first data of the correspondent entity page on first word-line And the described another pair for being intended to be stored on second word-line answers second data of physical page.