CN109783001A - Data-encoding scheme, data decoding method and storage control - Google Patents
Data-encoding scheme, data decoding method and storage control Download PDFInfo
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Abstract
The present invention provides a kind of data-encoding scheme, data decoding method and storage control.The coding method includes that the verify data of corresponding initial data is obtained according to write instruction；The verify data is added to the initial data, and data after being upset accordingly；Encoding operation is executed to data after the upset, to obtain codeword data.The coding/decoding method includes executing decoding operate to codeword data, has decoded codeword data to obtain, and obtains upset preceding data accordingly；Identify the verify data and initial data before the upset in data；One or more the first system data of the initial data are corresponded to according to reading instruction identification；Judge whether the initial data is correct with the verify data via one or more described the first system data of comparison.
Description
Technical field
The present invention relates to a kind of data-encoding scheme and data decoding methods, more particularly to one kind to be suitable for being configured with and can answer
Write the data-encoding scheme, data decoding method and storage control of the storage device of formula non-volatile memory module.
Background technique
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage
The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data
It is non-volatile, power saving, small in size, and without characteristics such as mechanical structures, so being very suitable to be built into above-mentioned illustrated various
In portable multimedia device.
In general, the correctness of the data stored in order to ensure reproducible nonvolatile memorizer module is being incited somebody to action
A certain data are stored to before reproducible nonvolatile memorizer module, this data can be first encoded.Data (packet after coding
Containing initial data and error correcting code) it can be stored in reproducible nonvolatile memorizer module.Backward, the number after coding
According to that can be read and be decoded from reproducible nonvolatile memorizer module, to correct wherein mistake that may be present.
Previous error correcting code uses algebraic decoding algorithms more, such as (BCH code), and probability decoding algorithm at present, such as low-density parity
Check code (low density parity code, hereinafter also referred to LDPC), then gradually mature.LDPC coder/decoder can make
It is encoded with a sparse matrix (sparse matrix) and iterative decoding.However, some special error in data the case where
Under, the data after the successfully decoded of LDPC coder/decoder club passback are but still mistake.Above-mentioned responded successfully decoded
Data itself be still the phenomenon of mistake and can be described as approximate code word (Near Codeword) phenomenon, and the data can claim
For approximate code word.Above-mentioned approximation code word phenomenon may also appear in the coder/decoder using other algorithms.
It, can be before initial data be encoded, to original in traditional practice in order to solve the problems, such as this approximate code word
Beginning data carry out cyclic redundancy check (Cyclic redundancy check, CRC) operation to obtain corresponding cyclic redundancy school
Code is tested, and is appended to initial data, then is performed the encoding operation via coder/decoder.It thereafter, can be superfluous by recycling
Whether remaining check code is correct come the data for checking successfully decoded that coder/decoder is responded.
However, whether executing cyclic redundancy check operation or cyclic redundancy check code itself, can all need additionally to consume
The additional calculation resources of charge system or space.Therefore, it is whether correct that decoded data how is verified with more advanced mode,
To solve the problems, such as approximation code word and promote the accuracy of coding/decoding operation, and then promote asking Ding Du and imitating for storage device
Rate, thus field technical staff subject under discussion of concern.
Summary of the invention
The present invention provides a kind of data-encoding scheme, data decoding method and storage control, can be intended to encode according to correspondence
The known verify datas of data the data are performed the encoding operation.Also, using to known to desire target data
Verify data, it is whether correct to verify decoded data manipulation.
One embodiment of the invention, which provides, to be suitable for encoding the original for being intended to store to reproducible nonvolatile memorizer module
A kind of data-encoding scheme of beginning data, wherein the reproducible nonvolatile memorizer module has multiple solid elements,
And each solid element of the multiple solid element includes multiple entity subelements, and plurality of physical address is configured
To the multiple entity subelement.The method includes starting to execute write instruction, wherein institute is written in said write instruction instruction
State one or more the target entity addresses of initial data into the multiple physical address；It is corresponded to according to said write instruction
The verify data of the initial data；Adding the verify data to the initial data becomes data before upset；It is disturbed to described
Data, which execute, before unrest upsets operation, with data after being upset；Encoding operation is executed to data after the upset, to obtain code word
Data；And after obtaining the codeword data, the codeword data is written to one or more described target entity addresses, with complete
The execution instructed at said write.
One embodiment of the invention is provided for decoding the code word being stored in reproducible nonvolatile memorizer module
A kind of data decoding method of data, wherein the reproducible nonvolatile memorizer module has multiple solid elements, and
And each solid element of the multiple solid element includes multiple entity subelements, plurality of physical address is configured to
The multiple entity subelement.It instructs the method includes starting to execute to read instruction, and according to the reading from described more
Read the codeword data in one or more target entity addresses in a physical address；Decoding behaviour is executed to the codeword data
Make, has decoded codeword data to obtain；Unscrambling operation is executed to the codeword data that decoded, upsets preceding data to obtain；
Identify the verify data and initial data before the upset in data；The initial data is corresponded to according to the reading instruction identification
One or more the first system data；Via one or more described the first system data of comparison and the verify data to judge
Whether correct initial data is stated, wherein determining the original if the verify data is equal to one or more described the first system data
Beginning data are correct；And when it is correct for determining the initial data, determines the codeword data successfully decoded, transmit the original
Beginning data, to complete the execution for reading instruction.
One embodiment of the invention is provided to be filled for controlling the storage configured with reproducible nonvolatile memorizer module
A kind of storage control set, wherein the reproducible nonvolatile memorizer module has multiple solid elements, wherein institute
Stating reproducible nonvolatile memorizer module has multiple solid elements, and each entity of the multiple solid element
Unit includes multiple entity subelements, and plurality of physical address is configured to the multiple entity subelement.The storage control
Device processed includes memory interface control circuit, error checking and correcting circuit and processor.Memory interface control circuit to
It is coupled to the reproducible nonvolatile memorizer module.Error checking and correcting circuit to encode be intended to store to it is described can
The initial data of manifolding formula non-volatile memory module.Processor is coupled to the memory interface control circuit and the mistake
Erroneous detection is looked into and correcting circuit.The processor executes write instruction to start, and the initial data is sent to the mistake
Check and correcting circuit, wherein said write instruction instruction be written the initial data into the multiple physical address one or
Multiple target entity addresses.The error checking and correcting circuit are to instruct the corresponding original number of acquisition according to said write
According to verify data, wherein the error checking and correcting circuit more to add the verify data to the initial data at
Data before being upset for one, wherein the error checking and correcting circuit are more grasped to execute a upset to data before the upset
Make, to obtain data after a upset.In addition, the error checking and correcting circuit are more to execute volume to data after the upset
Code operation to obtain codeword data, and responds the processor and corresponds to the codeword data of initial data warp knit
Code is completed, wherein the processor is more to be written the codeword data to one or more described target entity addresses, to complete
The execution of said write instruction.
One embodiment of the invention is provided to be filled for controlling the storage configured with reproducible nonvolatile memorizer module
A kind of storage control set, wherein the reproducible nonvolatile memorizer module has multiple solid elements, wherein institute
Stating reproducible nonvolatile memorizer module has multiple solid elements, and each entity of the multiple solid element
Unit includes multiple entity subelements, and plurality of physical address is configured to the multiple entity subelement.The storage control
Device processed includes memory interface control circuit, error checking and correcting circuit and processor.Memory interface control circuit to
It is coupled to the reproducible nonvolatile memorizer module.Error checking and correcting circuit described can be answered for decoding to be stored in
Write the codeword data in formula non-volatile memory module.Processor is coupled to the memory interface control circuit and the mistake
Erroneous detection is looked into and correcting circuit.The processor reads instruction to start to execute, and is instructed according to the reading from the multiple reality
The codeword data is read in one or more target entity addresses in body address, and the codeword data is sent to the mistake
Erroneous detection is looked into and correcting circuit.The error checking and correcting circuit are to execute decoding operate to the codeword data, to obtain
Codeword data is decoded, wherein the error checking and correcting circuit are more to execute solution upset to the codeword data that decoded
Operation upsets preceding data to obtain.In addition, the error checking and correcting circuit are more to identify before the upset in data
Verify data and initial data, wherein the error checking and correcting circuit are more to according to the corresponding institute of the reading instruction identification
One or more the first system data of initial data are stated, wherein the error checking and correcting circuit are more to described via comparing
One or more the first system data judge whether the initial data is correct with the verify data, wherein if the verifying number
According to one or more described the first system data are equal to, the error checking determines that the initial data is correct with correcting circuit.When
When determining that the initial data is correct, the error checking and correcting circuit determine the codeword data successfully decoded, transmission
The initial data, and respond the processor and correspond to the initial data of the codeword data successfully decoded, with
Complete the execution for reading instruction.
Based on above-mentioned, data-encoding scheme, data decoding method provided by the embodiment of the present invention and storage control,
In encoding operation, verify data can be obtained according to the write instruction of corresponding initial data, with additional authentication data to original
Data execute encoding operation again, and do not need attached cyclic redundancy check code to initial data, and then reduce whole code word
The consuming space of data.In addition, in decoding operate, can according to the reading instruction identification of corresponding codeword data one or more first
System data, and original obtained after decoding is judged according to one or more described the first system data and the verify data
Whether beginning data are correct.In particular, above-mentioned coding/decoding operation can save consuming in the money of cyclic redundancy check code operation
Source/calculation amount.In this way, which decoded data can still be checked in the case where not needing via cyclic redundancy check code
It is whether correct, so can solve the problems, such as approximate code word and the storage device that is enhanced in the case where saving resource encode/
The whole efficiency of decoding data.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the block schematic diagram of host system shown by an embodiment according to the present invention and storage device；
Fig. 2 is that coding/decoding performed by error checking circuit shown by an embodiment according to the present invention operates
Schematic diagram；
Fig. 3 A is the schematic diagram that the initial data of codeword data is encoded as according to one embodiment of the invention；
Fig. 3 B is the schematic diagram that the codeword data of initial data is decoded as according to one embodiment of the invention；
Fig. 4 A is the flow chart of the data-encoding scheme according to one embodiment of the invention；
Fig. 4 B is the flow chart of the step S42 in Fig. 4 A according to one embodiment of the invention；
Fig. 5 A is the flow chart of the data decoding method according to one embodiment of the invention；
Fig. 5 B is the flow chart of the step S55 in Fig. 5 A according to one embodiment of the invention.
Drawing reference numeral explanation:
10: host system
20: storage device
110,211: processor
120: mainframe memory
130: data transmission interface circuit
210: storage control 212: data transfer management circuit
213: memory interface control circuit
214: error checking and correcting circuit
220: reproducible nonvolatile memorizer module
230: connecting interface circuit
2140: inspection unit
2141: disarrangement device
2142: descrambler
2143: encoder
2144: decoder
2145:CRC (cyclic redundancy checker)
A10, A11, A12, A13, A20, A21, A22, A23: arrow
RD1, RD2: initial data
CD1, CD2: codeword data
VD1, VD2: verify data
RVD1, RVD2: data before upsetting
RVSD1, RVSD2: data after upset
ECC1, ECC2: error checking and correcting code
S41, S42, S43, S44, S45, S46: the process step of data-encoding scheme
S421, S423, S425: the process step of step S42
S51, S52, S53, S54, S55, S56, S57: the process step of data decoding method
S551, S553, S555: the process step of step S55
Specific embodiment
In the present embodiment, storage device includes reproducible nonvolatile memorizer module (rewritable non-
Volatile memory module) and storage controller (also referred to as, storage control or storage control circuit).In addition,
Storage device is used together with host system, so that host system can write data into storage device or from storage device
Read data.
Fig. 1 is the block schematic diagram of host system shown by an embodiment according to the present invention and storage device.
Fig. 1 is please referred to, host system (Host System) 10 includes processor (Processor) 110, mainframe memory
(Host Memory) 120 and data transmission interface circuit (Data Transfer Interface Circuit) 130.In this reality
It applies in example, the coupling of data transmission interface circuit 130 (also referred to as, being electrically connected) to processor 110 and mainframe memory 120.Another
In one embodiment, system bus is utilized between processor 110, mainframe memory 120 and data transmission interface circuit 130
(System Bus) is coupled to each other.
Storage device 20 includes storage control (Storage Controller) 210, duplicative non-volatile memories
Device module (Rewritable Non-Volatile Memory Module) 220 and connecting interface circuit (Connection
Interface Circuit)230.Wherein, storage control 210 includes processor 211, data transfer management circuit (Data
Transfer Management Circuit) 212 and memory interface control circuit (Memory Interface Control
Circuit)213。
In the present embodiment, host system 10 is connect by data transmission interface circuit 130 and the connection of storage device 20
Mouth circuit 230 is coupled to storage device 20 to carry out the accessing operation of data.It is connect for example, host system 10 can be transmitted via data
Data are stored to storage device 20 or read data from storage device 20 by mouth circuit 130.
In the present embodiment, processor 110, mainframe memory 120 and data transmission interface circuit 130 may be provided at host
On the motherboard of system 10.The number of data transmission interface circuit 130 can be one or more.Pass through data transmission interface circuit
130, motherboard can be coupled to storage device 20 via wired or wireless way.Storage device 20 can be for example portable disk, deposit
Card storage, solid state hard disk (Solid State Drive, SSD) or radio memory storage device.Radio memory storage device can
E.g. close range wireless communication (Near Field Communication, NFC) memory storage apparatus, radio facsimile
(WiFi) memory storage apparatus, bluetooth (Bluetooth) memory storage apparatus or low-power consumption bluetooth memory storage apparatus
The memory storage apparatus based on various wireless communication technique such as (for example, iBeacon).In addition, motherboard can also lead to
It crosses system bus and is coupled to global positioning system (Global Positioning System, GPS) module, network interface card, nothing
The various I/O device such as line transmitting device, keyboard, screen, loudspeaker.
In the present embodiment, data transmission interface circuit 130 and connecting interface circuit 230 are to be compatible to high-speed peripheral part
The interface electricity of connecting interface (Peripheral Component Interconnect Express, PCI Express) standard
Road.It also, is to utilize flash non-volatile memory interface between data transmission interface circuit 130 and connecting interface circuit 230
Standard (Non-Volatile Memory express, NVMe) communications protocol carries out the transmission of data.
However, it is necessary to be appreciated that, the invention is not limited thereto, data transmission interface circuit 130 and connecting interface circuit 230
It is also possible to meet advanced attachment (Parallel Advanced Technology Attachment, PATA) standard, electricity arranged side by side
Gas and Electronic Engineering Association (Institute of Electrical and Electronic Engineers, IEEE) 1394
The advanced attachment of standard, sequence (Serial Advanced Technology Attachment, SATA) standard, universal sequence are total
Line (Universal Serial Bus, USB) standard, SD interface standard, a ultrahigh speed generation (Ultra High Speed-I,
UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory
Stick, MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, multimedia storage card (Multi
Media Card, MMC) interface standard, eMMC interface standard, general flash memory (Universal Flash Storage,
UFS) interface standard, eMCP interface standard, CF interface standard, integrated driving electrical interface (Integrated Device
Electronics, IDE) standard or other suitable standards.In addition, in another embodiment, connecting interface circuit 230 can be with
Storage control 210 is encapsulated in a chip or connecting interface circuit 230 is to be laid in one to include storage control 210
Chip outside.
In the present embodiment, mainframe memory 120 is configured to temporarily store instruction performed by processor 110 or data.For example,
In this exemplary embodiment, mainframe memory 120 can be dynamic random access memory (Dynamic Random Access
Memory, DRAM), static random access memory (Static Random Access Memory, SRAM) etc..However, it is necessary to
It is appreciated that, the invention is not limited thereto, and mainframe memory 120 is also possible to other suitable memories.
Storage control 210 is to execute with the multiple logic gates or control instruction of hardware pattern or firmware pattern implementation simultaneously
And carried out in reproducible nonvolatile memorizer module 220 according to the instruction of host system 10 data write-in, read with
It the running such as erases.
In more detail, the processor 211 in storage control 210 is the hardware for having operational capability, to control
The overall operation of storage control 210.Specifically, processor 211 has multiple control instructions, and transports in storage device 20
When making, the runnings such as these control instructions can be performed to carry out the write-in of data, read and erase.
It is noted that in the present embodiment, processor 110 and processor 211 are, for example, central processing unit
The place of (Central Processing Unit, CPU), microprocessor (micro-processor) or other programmables
Manage unit (Microprocessor), digital signal processor (Digital Signal Processor, DSP), programmable
Controller, special application integrated circuit (Application Specific Integrated Circuits, ASIC), can program
Change logic device (Programmable Logic Device, PLD) or other similar circuit element, the present invention is not limited thereto.
In one embodiment, storage control 210 also has read-only memory (not shown) and random access memory (not
Display).In particular, this read-only memory has boot code (boot code), and when storage control 210 is enabled, place
Reason device 211 can first carry out the control instruction that this boot code will be stored in reproducible nonvolatile memorizer module 220 and carry
Enter into the random access memory of storage control 210.Later, processor 211 can operate these control instructions to be counted
According to write-in, the running such as read and erase.In another embodiment, the control instruction of processor 211 can also be with procedure code pattern
It is stored in the specific region of reproducible nonvolatile memorizer module 220, for example, reproducible nonvolatile memorizer module
It is exclusively used in 220 in the entity storage unit of storage system data.
In the present embodiment, as described above, storage control 210 further includes that data transfer management circuit 212, memory connect
Mouth control circuit 213 and error checking and correcting circuit 214.It should be noted that behaviour performed by each component of storage control 220
Also it can be considered operation performed by storage control 220.
Wherein, data transfer management circuit 212 is coupled to processor 211, memory interface control circuit 213 connects with connection
Mouth circuit 230.Data transfer management circuit 212 carries out the transmission of data to receive the instruction of processor 211.For example, through
Data are read from host system 10 (e.g., mainframe memory 120) by connecting interface circuit 230, and read data are passed through
By the write-in of memory interface control circuit 213 into reproducible nonvolatile memorizer module 220 (e.g., according to from host
The write instruction of system 10 carries out write operation).In another example non-from duplicative via memory interface control circuit 213
Data are read in one or more solid elements of volatile 220, and (data are readable to be derived from one or more solid elements
In one or more storage units/entity subelement), and by read data via connecting interface circuit 230 be written extremely
(behaviour e.g., is read out according to the reading instruction from host system 10 in host system 10 (e.g., mainframe memory 120)
Make).In another embodiment, data transfer management circuit 212 can also be integrated into processor 211.
Instruction of the memory interface control circuit 213 to receive processor 211 cooperates data transfer management circuit 212
To carry out write-in (also referred to as, sequencing, Programming) operation, the reading for reproducible nonvolatile memorizer module 220
Extract operation or operation of erasing.
For example, write instruction sequence (or 211 designation date transfer management circuit of processor can be performed in processor 211
212 send write instruction sequence to memory interface control circuit 213), to indicate memory interface control circuit 213 by data
One or more physical address (also referred to as, target entity address) into reproducible nonvolatile memorizer module 220 are written；Place
The executable reading instruction sequence of reason device 211 (or 211 designation date transfer management circuit 212 of processor sends and reads instruction sequence
To memory interface control circuit 213), to indicate memory interface control circuit 213 from type nonvolatile
Data are read in corresponding one or more physical address (also referred to as, target entity address) for reading instruction of module 220；Processor
211 executable instruction sequences of erasing (or the transmission of 211 designation date transfer management circuit 212 of processor erases instruction sequence to depositing
Memory interface control circuit 213), to indicate memory interface control circuit 213 to reproducible nonvolatile memorizer module
220 carry out operation of erasing.Write instruction sequence reads instruction sequence and instruction sequence of erasing can distinctly include one or more programs
Code or instruction code and to indicate to execute reproducible nonvolatile memorizer module 220 corresponding write-in, read and
It the operation such as erases.In one embodiment, processor 211 can also assign other kinds of instruction sequence and control to memory interface
Circuit 213, to execute corresponding operation to reproducible nonvolatile memorizer module 220.
In addition, being intended to be written to the data of reproducible nonvolatile memorizer module 220 can control via memory interface
Circuit 213 is converted to the 220 receptible format of institute of reproducible nonvolatile memorizer module.Specifically, if processor 211
Reproducible nonvolatile memorizer module 220 is accessed, processor 211 can transmit corresponding instruction sequence to memory interface
Control circuit 213 is to indicate that memory interface control circuit 213 executes corresponding operation.For example, these instruction sequences may include
The instruction of erasing for data that the write instruction sequence of instruction write-in data, instruction read the reading instruction sequence of data, instruction is erased
Sequence and the corresponding finger to indicate various storage operations (e.g., garbage collection operation, loss balancing operation etc.)
Enable sequence.These instruction sequences may include one or more signals, or the data in bus.These signals or data may include
Instruction code or procedure code.For example, will include the information such as identification code, the storage address of reading in reading instruction sequence.
Fig. 2 is that coding/decoding performed by error checking circuit shown by an embodiment according to the present invention operates
Schematic diagram.Referring to figure 2., in the present embodiment, error checking and correcting circuit 214 include inspection unit (checking
Unit) 2140, disarrangement device (scrambler) 2141, descrambler (descrambler) 2142, encoder (encoder) 2143
With decoder (decoder) 2144.In another embodiment, error checking and correcting circuit 214 further include cyclic redundancy check
Device (Cyclic Redundancy Checker, CRC) 2145.
In the present embodiment, inspection unit 2140, encoder 2143 and decoder 2144 are come in a manner of hardware circuit
Implementation.It should be noted that in one embodiment, disarrangement device 2141 can be integrated into a upset/solution with descrambler 2142 and upset
Device (scrambler/descrambler), and encoder 2143 can integrate a coder/decoder with decoder 2144.This
Outside, in another embodiment, disarrangement device 2141 can also be integrated into encoder 2143, and descrambler 2142 can also be integrated into
In decoder 2144.
Error checking ensures to be stored in duplicative non-with correcting circuit 214 to execute error checking and correction program
Data (also referred to as, code word/codeword data, codeword/codeword data) in volatile 220 it is correct
Property.The error checking and correction program can divide into (1) again and initial data compiled the coded program (coding that seal character is codeword data
Operation), and codeword data is decoded as the decoding program (decoding operate) of initial data by (2).
In coded program, inspection unit 2140 is to the additional verify data for corresponding to initial data to initial data；It disturbs
Random device 2141 has upset data to carry out upset operation to received data, with output；Encoder 2143 is will be connect
The data (e.g., having upset data) of receipts perform the encoding operation, and are formed with additional error inspection and correcting code to received data
For codeword data.
In decoding program, decoder 2144 received data (e.g., codeword data) is decoded operation, with
According to error checking therein and correcting code to decode/correct received codeword data, and then output data (e.g., has been upset
Data) give descrambler 2142；Descrambler 2142 is received to carry out unscrambling operation to received data with reduction
Data be upset preoperative data (data before also referred to as, upsetting)；Inspection unit 2140 is to according to correspondence code number of words
Received data is examined (e.g., to upset according to the verify data of (or expected by initial data obtained by decoding program)
Preceding data), and then determine whether the codeword data is correctly decoded as initial data.The verify data can be metadata
(metadata), system data (system data) or other given datas.
In the present embodiment, encoder 2143 and algorithm used in decoder 2144 are identical algorithm.The algorithm
For example, low-density parity check code (low density parity code, LDPC) algorithm.However, in another embodiment,
Algorithm used in encoder 2143 and decoder 2144 is also possible to BCH code, convolution code (convolutional code), whirlpool
Take turns the coding/decodings algorithms such as code (turbo code), bit overturning (bit flipping).
It should be noted that above-mentioned inspection unit 2140 can also be integrated into processor 211, that is, processor 211 can have
The function of inspection unit 2140, error checking is sent to again with additional authentication data to initial data and correcting circuit 214 come into
Row encoding operation, or after error checking and the reception initial data of correcting circuit 214, via the system data of corresponding initial data
Check whether initial data obtained is correct with verify data.Error checking and school can be described in detail by multiple attached drawings below
The function and Collaboration mode of each element in positive circuit 214.
Reproducible nonvolatile memorizer module 220 is coupled to 210 (memory interface control circuit of storage control
213) data and to host system 10 being written.Reproducible nonvolatile memorizer module 220 can be list
Rank storage unit (Single Level Cell, SLC) NAND type flash memory module in a storage unit (that is, can store
The flash memory module of 1 bit), multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory mould
Block (that is, flash memory module that 2 bits can be stored in a storage unit), three rank storage unit (Triple Level
Cell, TLC) NAND type flash memory module be (that is, can store the flash memory mould of 3 bits in a storage unit
Block), three dimensional NAND type flash memory module (3D NAND flash memory module) or vertical nand type flash
Other flash memory modules such as device module (Vertical NAND flash memory module) or other with identical spy
The memory module of property.Storage unit in reproducible nonvolatile memorizer module 220 is to be arranged in array fashion.
In the present embodiment, multiple storage units of reproducible nonvolatile memorizer module 220 can constitute multiple realities
Body programmed cell (also referred to as, entity subelement), and (also referred to as, these entity program units can constitute multiple physical blocks
Entity erased cell or solid element).Specifically, the storage unit meeting on same word-line (or same word-line layer)
Form one or more entity program units.It is single to the multiple entity that multiple physical address can be respectively configured in processor 211
Member.
It in the examples below, is using storage unit as the minimum unit that (sequencing) data are written.Solid element is
The minimum unit erased, that is, each solid element contains the storage unit of minimal amount being erased together.In addition, entity list
Member is physical blocks, and entity subelement is physical page, and ground of each physical address to refer to corresponding physical page
Location.
It should be noted that in the present embodiment, can be described as entity to record the system data of information of a solid element
Unit information, and it can be recorded using one or more entity subelements in the solid element, or utilize a system
It is recorded in area to record one or more entity subelements of the special entity unit of all system datas.In the present embodiment
In, the solid element information includes time numerical value (Program erase cycle, PEC), timestamp of erasing of the solid element
Remember (Timestamp), reading times value (Read counter value), solid element index code (Physical Unit
The information such as Index).In more detail, it when processor 211, which erase to a solid element, to be operated, smears described in the completion
After operation, processor 211 can add 1 to time numerical value of erasing for currently corresponding to the solid element, and (e.g., erasing time numerical value can be with every
Secondary erasing is operated and is added up since 0).That is, time numerical value of erasing can reflect being erased for solid element corresponding to it
The summation of number.The time stab is to indicate that corresponding solid element stores the time of the first stroke data therein.Time
The size (numerical value difference) of stamp can be used to indicate the sequencing of time.The present invention does not limit the detailed of the time stab
Format.The total degree that the reading times value is read to count corresponding solid element.The solid element index code is used
To represent the unique identification code of corresponding solid element, processor 211 can identify that its institute is right according to solid element index code
The solid element answered and relevant data.
Storage control 210 can configure multiple logic units to reproducible nonvolatile memorizer module 220.Host system
System 10 is the logic unit by being configured to access the user's data being stored in multiple solid elements.Here, each
Logic unit can be to be made of one or more logical addresses.For example, logic unit can be logical blocks (Logical
Block), logical page (LPAGE) (Logical Page) or logic sector (Logical Sector).One logic unit can be
Map to one or more solid elements, wherein solid element can be one or more physical address, one or more entities fan, one or
Multiple entity program units or one or more entity erased cells.In the present embodiment, logic unit is logical blocks, and
And logical subunit is logical page (LPAGE).Each logic unit has multiple logical subunits.
In addition, storage control 210, which can establish logic, turns physical address mapping table (Logical To Physical
Address mapping table) with entity turn logical address mapping table (Physical To Logical address
Mapping table), to record logic unit (e.g., the logic area for being allocated to reproducible nonvolatile memorizer module 220
Block, logical page (LPAGE) or logic sector) with solid element (e.g., entity erased cell, entity program unit, entity sector) between
Mapping relations.In other words, storage control 210 can be turned physical address mapping table by logic and be reflected to search a logic unit
The solid element penetrated, and storage control 210 can be turned logical address mapping table by entity and be reflected to search a solid element
The logic unit penetrated.However, the above-mentioned technological concept in relation to logic unit and solid element mapping is those skilled in the art's
Conventional techniques are repeated no more in this.
In one embodiment, storage control 210 further includes buffer storage and electric power management circuit.Buffer storage is
Be coupled to processor 211 and be configured to temporarily store data from host system 10 with instruction, it is non-volatile from duplicative
The data of property memory module 220 or other system datas to managing storage 20, to allow processor 211 can be rapidly
The data, instruction or system data are accessed from buffer storage.Electric power management circuit is coupled to processor 211 and uses
To control the power supply of storage device 20.
Fig. 3 A is the schematic diagram that the initial data of codeword data is encoded as according to one embodiment of the invention.
Fig. 4 A is the flow chart of the data-encoding scheme according to one embodiment of the invention.Referring to Fig. 2, Fig. 3 A, figure
4A, in step S41, processor 211 starts to execute write instruction, and wherein the initial data is written in said write instruction instruction
To one or more target entity addresses in the multiple physical address.
For example, in this example, it is assumed that host system 10 sends write instruction and initial data RD1 to processor
211, and write instruction instruction stores the initial data RD1 to one or more logical addresses (also referred to as, target logic
Location).It is instructed according to said write, processor 211 can be from all available realities of reproducible nonvolatile memorizer module 220
One or more physical address (also referred to as, target entity address) are selected to store the initial data RD1 in body address.Processor
211 can send initial data RD1 to error checking and correcting circuit 214 to start to carry out the coding for initial data RD1
Program (arrow A10 as shown in Figure 2).
Then, after receiving the initial data RD1, in step S42, inspection unit 2140 is instructed from said write
The middle verify data VD1 for obtaining the corresponding initial data.That is, inspection unit 2140 can directly be read from write instruction
The verify data VD1 of the corresponding initial data.The verify data VD1 can be for store the one or more of initial data RD1
A destination logical address.Below by way of Fig. 4 B, the details of the step S42 and verify data VD1 is more described in detail.
Fig. 4 B is the flow chart of the step S42 in Fig. 4 A according to one embodiment of the invention.B referring to figure 4.,
In the present embodiment, in step S421, the corresponding initial data of identification from said write instruction of inspection unit 2140
Multiple the first system data.In the present embodiment, write instruction includes multiple the first system data, and instruction narration.It is described
The first system data include one or more destination logical address to store initial data RD1；To store initial data RD1
One or more target entity addresses；And the solid element information of the target entity unit to store initial data RD1.It is real
Body unit information has been illustrated as above, is repeated no more in this.Above-mentioned the first system data can have respective data length respectively.This
Outside, the processor 211 can know that said write instruction is intended to original number according to the information for the instruction narration that said write instructs
According to write-in to one or more described destination logical address.
Then, in step S423, inspection unit 2140 determines the verify data according to preset checking ability
Length.Specifically, manufacturer can set the height of the checking ability of inspection unit 2140 according to demand.With checking ability
The range of the length of the different verify datas of height also can and then change.For example, the range of the length of verify data can be 1~16
Tuple.That is, the length of verify data can be preset.
Then, in step S425, inspection unit 2140 is according to the length of the verify data from the multiple
One or more second system data are selected in one system data, combine one or more selected described second system data
At the verify data, wherein the total data length of selected one or more second system data is equal to the verifying number
According to the length.Specifically, due to the length of verify data it is determined that, inspection unit 2140 can come accordingly from the multiple
One or more are selected in the first system data, so that the first system data (also referred to as, one or more the second system numbers selected
According to) the summation (also referred to as, total data length) of data length can be equal to the length of preset verify data.Then, it is determining
After one or more second system data, inspection unit 2140 can read one or more second system data from write instruction
One or more described second system data are combined, to constitute a verify data (inspection unit 2140 obtains verify data).
That is, inspection unit 2140 can accordingly change the type of second system data when the length of verify data changes, with
Form different verify datas.In addition, in one embodiment, also one or more cleavable specific first systems of inspection unit 2140
It unites data, to become second system data, so that via verify data made of combined by one or more second system data
Length meets preset value.
It should be noted that multiple second system data for constituting verify data put in order can according to demand or
It is setting to be changed.In addition, via the explanation of Fig. 4 B, it is to be understood that verify data can direct writing from the correspondence initial data
Enter and read in instruction, does not need in addition to expend resource to calculate or encoding verification data.
Fig. 4 A please be return, after obtaining verify data, in step S43, as shown in the arrow A11 in Fig. 2, Fig. 3 A,
Inspection unit 2140, which adds the verify data VD1 to the initial data RD1, becomes data RVD1 before upset.In addition, upsetting
Preceding data RVD1 can be transmitted to disarrangement device 2141, to carry out upset operation.
Before obtaining upset after data RVD1, in step S44, as shown in the arrow A12 in Fig. 2, Fig. 3 A, disarrangement device
Data RVD1, which is executed, before 2141 pairs of upsets upsets operation, with data RVSD1 after being upset.In addition, data after upsetting
RVSD1 can be transmitted to encoder 2143, to perform the encoding operation.
After being upset after data RVSD1, in step S45, as shown in the arrow A13 in Fig. 2, Fig. 3 A, encoder
Data RVSD1 executes encoding operation after 2143 pairs of upsets, to obtain codeword data CD1.Specifically, to the upset
After data RVSD1 executes encoding operation afterwards, encoder 2143 can generate error checking and correcting code ECC1, and encoder 2143
Error checking and correcting code ECC1 are attached to data RVSD1 after upsetting, to form codeword data CD1 (as shown in Fig. 3 A).
Finally, in step S46, after obtaining the codeword data, be written the codeword data to it is described one or more
Target entity address, to complete the execution of said write instruction.Specifically, after obtaining codeword data CD1, error checking with
The codeword data encoded completion of the corresponding initial data RD1 of the meeting response handler 211 of correcting circuit 214.Processor 211 can incite somebody to action
The codeword data CD1 that coding is completed is written to one or more described target entity addresses, to complete the execution of said write instruction.
In addition, one or more described destination logical address can also be mapped to one or more described target entity addresses by processor 211, and
And it responds initial data RD1 described in host system 10 and has been written into 220 (write instruction of reproducible nonvolatile memorizer module
It is completed).
It should be noted that in the above-described embodiments, write instruction is transmitted by host system, to be written as user's data
Initial data.However, in another embodiment, write instruction can be used to execute processor 211 also in order to manage and be stored
The corresponding data write operation executed of the management operation (e.g., data union operation, garbage collection operation etc.) of data.
Fig. 3 B is the schematic diagram that the initial data of codeword data is encoded as according to one embodiment of the invention.
Fig. 5 A is the flow chart of the data decoding method according to one embodiment of the invention.Referring to Fig. 2, Fig. 3 B, figure
5A, in step s 51, processor 211 start execute read instruction, and according to readings instruct from it is the multiple physically
Read the codeword data in one or more target entity addresses in location.
For example, in this example, it is assumed that host system 10, which is sent, reads instruction to processor 211, and it is described
It reads instruction instruction and reads initial data from one or more logical addresses (also referred to as, destination logical address).Referred to according to the reading
It enables, processor 211 can map to described from all available physical address of reproducible nonvolatile memorizer module 220
One or more physical address (also referred to as, target entity address) of one or more destination logical address read codeword data CD2 (code
Digital data CD2 is encoded by the initial data to be read of host system 10 and is written to the data of target entity address).Processing
Codeword data CD2 can be sent to error checking and correcting circuit 214 to start to carry out the solution for codeword data CD2 by device 211
Coded program (arrow A20 as shown in Figure 2).
Then, after receiving the codeword data CD2, in step S52, as shown in the arrow A21 in Fig. 2, Fig. 3 A,
Decoder 2144 executes decoding operate to the codeword data CD2, has decoded codeword data RVSD2 (also referred to as, after upset to obtain
Data RVSD2).Specifically, B, decoder 2144 can identify error checking and correction in codeword data CD2 referring to figure 3.
Code ECC2 and data RVSD2 after upset, and decoder 2144 can be checked and be corrected with correcting code ECC2 according to error checking
Data RVSD2 after upset is finally exported and decoded has been decoded codeword data RVSD2.Having decoded codeword data RVSD2 can be passed
It send to descrambler 2142, to carry out unscrambling operation.
Fig. 4 A please be return, after acquisition has decoded codeword data RVSD2, in step S53, such as the arrow in Fig. 2, Fig. 3 A
Shown in head A22, descrambler 2142 executes unscrambling operation to the codeword data RVSD2 that decoded, and upsets preceding number to obtain
According to RVD2.In addition, data RVD2 can be transmitted to inspection unit 2140 before upsetting, to carry out inspection operation.
Before obtaining upset after data RVD2, in step S54, inspection unit 2140 identifies data RVD2 before the upset
In verify data VD2 and initial data RD2 (as shown in Figure 3B).
Then, in step S55, inspection unit 2140 obtains the corresponding initial data RD2 from reading instruction
One or more the first system data.That is, inspection unit 2140, which can directly be read from reading instruction, can check verifying
The whether correct system data of data VD2.The system data can be one or more target logics of storage initial data RD2
Location.Below by way of Fig. 5 B, the more details of detailed description step S55 and the system data.
Fig. 5 B is the flow chart of the step S55 in Fig. 5 A according to one embodiment of the invention.B referring to figure 5.,
In the present embodiment, in step 551, inspection unit 2140 reads the more of the corresponding initial data of identification in instruction from described
A second system data.In the present embodiment, the multiple second system data are the multiple the in above-mentioned encoding operation
One system data, that is, correspond to the general designation of the various system datas of initial data, and reading instruction include instruction description with
And the multiple second system data.Wherein, the described instruction description for reading instruction to indicate processor 211 from one or
Initial data RD2 is read in multiple destination logical address.Then, processor 211 according to logic turn entity table can find out to
One or more the target entity addresses for the codeword data that storage is obtained via the coding initial data.The second system number
According to whether can be used to check via the decoding program for executing codeword data initial data RD2 obtained from reading
Instruct the destination logical address to be read.
Then, in step S553, inspection unit 2140 determines the verify data VD2 according to preset checking ability
Length.This step is identical to step S423.
Then, in step S555, inspection unit 2140 is according to the length of the verify data from the multiple
One or more the first system data are selected in two system data, combine one or more selected described the first system data
At the verify data, wherein the total data length of selected one or more the first system data is equal to the verifying number
According to the length.Specifically, it is similar to the explanation of above-mentioned steps S425, in the decoding program described in the present embodiment,
One or more described selected described the first system data be in coded program described in selecting one or more the
Two system data are used to be selected and read according to the length of preset verify data, to be combined into verify data.It changes
Yan Zhi, in step S555, inspection unit 2140 can be identified according to the length of verify data VD2, be read described in instruction
Answering in multiple second system data described is which system data (in the present embodiment, referred to as the first system data) to form
State verify data.In this way, via the explanation of Fig. 4 B, it is to be understood that processor 211 can be directly from the correspondence initial data
It reads in instruction and reads system data, checked via the comparison with verify data VD2 from codeword data CD2 original obtained
Beginning, whether data RD2 was correct.In addition the above-mentioned system data to compare with verify data VD2 is not needed via consuming resource
It could be obtained to calculate or decode.
Fig. 5 A is gone back to, then, in step S56, inspection unit 2140 is via one or more described the first systems of comparison
Data judge whether the initial data RD2 is correct with the verify data VD2, wherein if the verify data is equal to described
One or more the first system data determine that the initial data RD2 is correct.Specifically, identify it is described one or more the
After one system data, inspection unit 2140 can go comparison data VD2 whether be equal to identified it is described one or more
The first system data are (that is, whether the total data bit of inspection unit 2140 is equal to one or more described the first system data institutes
Multiple data bit elements made of sequence).If equal, inspection unit 2140 can determine that initial data RD2 is correct.
Then, in step S57, when it is correct for determining the initial data RD2, determine that the codeword data is decoded into
Function, error checking and correcting circuit 214 transmit the initial data RD2, to complete the execution for reading instruction.
Specifically, after determining that initial data RD2 is correct, error checking and correcting circuit 214 can response handlers
The decoding program of 211 corresponding codeword data CD2 has been completed, and obtains corresponding initial data RD2.The initial data
RD2 is the corresponding initial data for reading instruction.In addition, processor 211 can respond host system 10 be stored in described one or
The initial data RD2 of multiple logical addresses, which has been read, to be finished, and the initial data RD2 is back to host system
10, to complete the execution for reading instruction.
It should be noted that in the above-described embodiments, reading instruction is transmitted by host system, to be read as user's data
Initial data.However, in another embodiment, reading instruction can be used to execute processor 211 also in order to manage and be stored
The corresponding data read operation executed of the management operation (e.g., data union operation, garbage collection operation etc.) of data.
It should be noted that the operation of each element of above-mentioned error checking and correcting circuit 214 also can be considered error checking with
Operation performed by correcting circuit 214.
Data-encoding scheme, data decoding method and the storage control for implementing the method illustrated according to above-described embodiment
Device processed, it may be unnecessary in the case where CRC is arranged, can still check whether decoded data are correct.
However, another combinable existing CRC technological means and above-mentioned data-encoding scheme and data can be reintroduced below
Another embodiment of coding/decoding method place different from above-described embodiment.
Specifically, in coded program, after the verify data for obtaining corresponding initial data, 2140 pairs of institutes of inspection unit
It states verify data and the initial data executes cyclic redundancy check operation, to obtain cyclic redundancy check code.Then, checklist
Member 2140 executes mutual exclusion or operation according to the cyclic redundancy check code and the verify data, to verify number after being adjusted
According to.Then, adding the verify data to the initial data in above-mentioned inspection unit 2140 becomes the running of the preceding data of upset
In (as shown in arrow A11), inspection unit 2140 by verify data after the adjustment replace the verify data to be attached to
Initial data is stated as data before the upset.
On the other hand, in decoding program, after identifying one or more described the first system data, inspection unit 2140
Cyclic redundancy check operation is executed to one or more described the first system data and the initial data, to obtain cyclic redundancy school
Test code.Then, inspection unit 2140 executes mutual exclusion or operation according to the cyclic redundancy check code and the verify data, to obtain
Verify data after must adjusting.Then, next with the verify data via one or more described the first system data are compared above-mentioned
In judging whether the initial data correctly operates, inspection unit 2140 is changed to verify data after adjusting and replaces verify data
To be compared with one or more described the first system data.If verify data is equal to one or more described the first systems after adjustment
Data, then inspection unit 2140 determines that the initial data RD2 is correct.In this way, can be by being obtained via CRC operation
Adjustment after verify data replace verify data to reinforce the reliability of coded program and decoding program.
In conclusion data-encoding scheme, data decoding method provided by the embodiment of the present invention and storage control,
In encoding operation, verify data can be obtained according to the write instruction of corresponding initial data, with additional authentication data to original
Data execute encoding operation again, and do not need attached cyclic redundancy check code to initial data, and then reduce whole code word
The consuming space of data.In addition, in decoding operate, can according to the reading instruction identification of corresponding codeword data one or more first
System data, and original obtained after decoding is judged according to one or more described the first system data and the verify data
Whether beginning data are correct.In particular, above-mentioned coding/decoding operation can save consuming in the money of cyclic redundancy check code operation
Source/calculation amount.In this way, which decoded data can still be checked in the case where not needing via cyclic redundancy check code
It is whether correct, so can solve the problems, such as approximate code word and the storage device that is enhanced in the case where saving resource encode/
The whole efficiency of decoding data.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection of the invention
Subject to range ought be defined depending on claim.
Claims (16)
1. a kind of data-encoding scheme, suitable for encoding the original number for being intended to store to reproducible nonvolatile memorizer module
According to, which is characterized in that the reproducible nonvolatile memorizer module has multiple solid elements, and the multiple entity
Each solid element of unit includes multiple entity subelements, and plurality of physical address is configured to the multiple entity
Unit, which comprises
Start to execute write instruction, wherein the initial data is written into the multiple physical address in said write instruction instruction
One or more target entity addresses；
The verify data of the corresponding initial data is obtained from said write instruction；
Adding the verify data to the initial data becomes data before upset；
Data before the upset are executed and upset operation, with data after being upset；
Encoding operation is executed to data after the upset, to obtain codeword data；And
After obtaining the codeword data, the codeword data is written to one or more described target entity addresses, to complete
State the execution of write instruction.
2. data-encoding scheme according to claim 1, which is characterized in that obtain the corresponding original in said write instruction
The step of verify data of beginning data includes:
Multiple the first system data of the corresponding initial data of identification from said write instruction；
The length of the verify data is determined according to a preset checking ability；And
One or more second system numbers are selected from the multiple the first system data according to the length of the verify data
According to one or more selected described second system data being combined into the verify data, wherein selected described one
Or the total data length of multiple second system data is equal to the length of the verify data.
3. data-encoding scheme according to claim 2, which is characterized in that
The multiple the first system data include one or more destination logical address to store the initial data；To deposit
Store up one or more target entity addresses of the initial data；And the target entity unit to store the initial data
Solid element information.
4. data-encoding scheme according to claim 3, which is characterized in that further include:
After the verify data for obtaining the corresponding initial data, the verify data and initial data execution are followed
Ring redundancy check operation, to obtain cyclic redundancy check code；
Mutual exclusion or operation are executed according to the cyclic redundancy check code and the verify data, with verify data after being adjusted；
And
In adding the step of verify data becomes data before the upset to the initial data, by the adjustment posteriority
Card data replace the verify data to be attached to the initial data as data before the upset.
5. a kind of data decoding method, for decoding the codeword data being stored in reproducible nonvolatile memorizer module,
It is characterized in that, the reproducible nonvolatile memorizer module has multiple solid elements, and the multiple entity list
Each solid element of member includes multiple entity subelements, and it is single that plurality of physical address is configured to the multiple entity
Member, which comprises
Start to execute and read instruction, and is real according to described one or more targets for reading instruction from the multiple physical address
Read the codeword data in body address；
Decoding operate is executed to the codeword data, has decoded codeword data to obtain；
Unscrambling operation is executed to the codeword data that decoded, upsets preceding data to obtain；
Identify the verify data and initial data before the upset in data；
One or more the first system data for corresponding to the initial data are obtained in instruction from described read；
Judge whether the initial data is correct with the verify data via one or more described the first system data of comparison,
If wherein the verify data is equal to one or more described the first system data, determine that the initial data is correct；And
When it is correct for determining the initial data, determines the codeword data successfully decoded, the initial data is transmitted, with complete
At the execution for reading instruction.
6. data decoding method according to claim 5, which is characterized in that the reading instruction identification corresponds to described original
The step of one or more described the first system data of data includes:
From the multiple second system data for reading the corresponding initial data of identification in instruction；
The length of the verify data is determined according to preset checking ability；And
According to the length of the verify data identify in the multiple second system data described in one or more first systems
System data, wherein the total data length of one or more the first system data is equal to the length of the verify data.
7. data decoding method according to claim 6, which is characterized in that
The multiple second system data include one or more destination logical address to store the initial data；To deposit
Store up one or more target entity addresses of the initial data；And the target entity unit to store the initial data
Solid element information.
8. data decoding method according to claim 7, which is characterized in that further include:
After identifying one or more described the first system data, to one or more described the first system data and the original number
According to cyclic redundancy check operation is executed, to obtain cyclic redundancy check code；
Mutual exclusion or operation are executed according to the cyclic redundancy check code and the verify data, with verify data after being adjusted；
And
Judge that the initial data is with the verify data via one or more described the first system data of comparison above-mentioned
In no correct step, by verify data after the adjustment replace the verify data with one or more described the first system numbers
According to comparison.
9. a kind of storage control, special for controlling the storage device for being configured with reproducible nonvolatile memorizer module
Sign is that the reproducible nonvolatile memorizer module has multiple solid elements, wherein the duplicative is non-volatile
Property memory module there are multiple solid elements, and each solid element of the multiple solid element includes multiple entities
Subelement, plurality of physical address are configured to the multiple entity subelement, and the storage control includes:
Memory interface control circuit, to be coupled to the reproducible nonvolatile memorizer module；
Error checking and correcting circuit, to encode the original number for being intended to store to the reproducible nonvolatile memorizer module
According to；And
Processor is coupled to the memory interface control circuit and the error checking and correcting circuit,
Wherein the processor executes write instruction to start, and the initial data is sent to the error checking and correction
Circuit, wherein it is real that one or more targets of the initial data into the multiple physical address are written in said write instruction instruction
Body address,
The wherein verifying of the error checking and correcting circuit to instruct the corresponding initial data of acquisition according to said write
Data,
Wherein the error checking and correcting circuit are also to add before the verify data to the initial data becomes and upset
Data,
Wherein the error checking and correcting circuit also upset operation to execute to data before the upset, after being upset
Data,
Wherein the error checking and correcting circuit are also to execute encoding operation to data after the upset, to obtain code word number
According to, and the codeword data encoded completion that the processor corresponds to the initial data is responded,
Wherein the processor is also to be written the codeword data to one or more described target entity addresses, described in completing
The execution of write instruction.
10. storage control according to claim 9, which is characterized in that the error checking and correcting circuit also to
In the running for instructing the verify data for obtaining the corresponding initial data according to said write,
The error checking and correcting circuit are according to multiple the first systems of the corresponding initial data of said write instruction identification
Data,
Wherein the error checking and correcting circuit determine the length of the verify data according to preset checking ability,
Wherein the error checking and correcting circuit are according to the length of the verify data from the multiple the first system number
According to middle one or more second system data of selection, one or more selected described second system data are combined into described test
Data are demonstrate,proved, wherein the total data length of selected one or more second system data is equal to the length of the verify data
Degree.
11. storage control according to claim 10, which is characterized in that
The multiple the first system data include one or more destination logical address to store the initial data；To deposit
Store up one or more target entity addresses of the initial data；And the target entity unit to store the initial data
Solid element information.
12. storage control according to claim 11, which is characterized in that
After the verify data for obtaining the corresponding initial data, the error checking and correcting circuit are to the verifying number
Cyclic redundancy check operation is executed according to the initial data, to obtain cyclic redundancy check code,
Wherein the error checking and correcting circuit according to the cyclic redundancy check code and the verify data execute mutual exclusion or
Operation, with verify data after being adjusted,
Wherein the error checking is also disturbed to the initial data as described to add the verify data with correcting circuit
Before unrest in the running of data, the error checking and correcting circuit by verify data after the adjustment replace the verify data with
The initial data is attached to as data before the upset.
13. a kind of storage control, special for controlling the storage device for being configured with reproducible nonvolatile memorizer module
Sign is that the reproducible nonvolatile memorizer module has multiple solid elements, wherein the duplicative is non-volatile
Property memory module there are multiple solid elements, and each solid element of the multiple solid element includes multiple entities
Subelement, plurality of physical address are configured to the multiple entity subelement, and the storage control includes:
Memory interface control circuit, to be coupled to the reproducible nonvolatile memorizer module；
Error checking and correcting circuit, for decoding the code word number being stored in the reproducible nonvolatile memorizer module
According to；And
Processor is coupled to the memory interface control circuit and the error checking and correcting circuit,
Wherein the processor reads instruction to start to execute, according to reading instruction from the multiple physical address
The codeword data is read in one or more target entity addresses, and the codeword data is sent to the error checking and school
Positive circuit,
Wherein the error checking and correcting circuit have decoded code word to execute decoding operate to the codeword data to obtain
Data,
Wherein the error checking and correcting circuit are also to execute unscrambling operation to the codeword data that decoded, to obtain
Data before upsetting,
Wherein the error checking and correcting circuit be also to identify verify data and initial data before the upset in data,
Wherein the error checking and correcting circuit are also to according to the one of the corresponding initial data of the reading instruction identification
Or multiple the first system data,
Wherein the error checking and correcting circuit with described also to test via comparing one or more described the first system data
Data are demonstrate,proved to judge whether the initial data is correct, wherein if the verify data is equal to one or more described the first system numbers
According to, the error checking determines that the initial data is correct with correcting circuit,
Wherein when it is correct for determining the initial data, the error checking and correcting circuit determine that the codeword data decodes
Success, transmits the initial data, and responds the processor and correspond to the initial data of the codeword data and solved
Code success, to complete the execution for reading instruction.
14. storage control according to claim 13, which is characterized in that in error checking described above and correcting circuit
Also to be corresponded in the running of one or more the first system data described in the initial data according to the reading instruction identification,
The error checking and correcting circuit are according to multiple second systems of the corresponding initial data of said write instruction identification
Data,
Wherein the error checking and correcting circuit determine the length of the verify data according to preset checking ability,
Wherein the error checking and correcting circuit are according to the multiple second system of the length of verify data identification
One or more described the first system data in data, wherein the total data length of one or more the first system data is equal to
The length of the verify data.
15. storage control according to claim 14, which is characterized in that
The multiple second system data include one or more destination logical address to store the initial data；To deposit
Store up one or more target entity addresses of the initial data；And the target entity unit to store the initial data
Solid element information.
16. storage control according to claim 15, which is characterized in that
After identifying one or more described the first system data, the error checking and correcting circuit to it is described one or more the
One system data and the initial data execute cyclic redundancy check operation, to obtain cyclic redundancy check code,
Wherein the error checking and correcting circuit according to the cyclic redundancy check code and the verify data execute mutual exclusion or
Operation, with verify data after being adjusted,
Wherein the original number is judged via one or more described the first system data and the verify data is compared above-mentioned
Correctly whether according in running, verify data after the adjustment is replaced the verify data by the error checking and correcting circuit
With with one or more described the first system comparings.
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| CN112099985A (en) * | 2019-06-17 | 2020-12-18 | 慧荣科技股份有限公司 | Data storage device and non-volatile memory control method |
| CN113053451A (en) * | 2021-03-05 | 2021-06-29 | 深圳三地一芯电子有限责任公司 | Method, system, host and storage medium for generating softbit in Nandflash |
| CN114860170A (en) * | 2022-05-17 | 2022-08-05 | 深圳宏芯宇电子股份有限公司 | Data access method, memory storage device and memory controller |
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| CN112099985A (en) * | 2019-06-17 | 2020-12-18 | 慧荣科技股份有限公司 | Data storage device and non-volatile memory control method |
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| CN113053451A (en) * | 2021-03-05 | 2021-06-29 | 深圳三地一芯电子有限责任公司 | Method, system, host and storage medium for generating softbit in Nandflash |
| CN113053451B (en) * | 2021-03-05 | 2022-05-10 | 深圳三地一芯电子有限责任公司 | Method, system, host and storage medium for generating softbit in Nandflash |
| CN114860170A (en) * | 2022-05-17 | 2022-08-05 | 深圳宏芯宇电子股份有限公司 | Data access method, memory storage device and memory controller |
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