CN114860170A - Data access method, memory storage device and memory controller - Google Patents

Abstract

The invention provides a data access method, a memory storage device and a memory controller. The method comprises the following steps: receiving first data from a host system; encoding first data to generate second data, wherein the second data includes an error correction code corresponding to the first data; performing data scrambling on the second data by a plurality of data scrambling modules respectively to generate a plurality of third data; selecting one of the plurality of third data as fourth data according to the states of the plurality of third data; and storing the fourth data to a first physical unit in a memory module. Therefore, the disturbance degree of the written data can be improved, and the reliability of the data read later is further improved.

Description

Data access method, memory storage device and memory controller

Technical Field

The present disclosure relates to memory control technologies, and more particularly, to a data access method, a memory storage device and a memory controller.

Background

Rewritable non-volatile memory (rewritable non-volatile memory) has characteristics such as data non-volatility, power saving, small size, and no mechanical structure, and is widely used in various electronic devices. The rewritable nonvolatile memory has a plurality of physical blocks (physical blocks), and each physical block has a plurality of physical pages (physical pages). The physical block is the minimum unit for data erasing, and the physical page is the minimum unit for data writing.

With the progress of semiconductor processing, the current technology has developed flash (flash) memory modules having memory cells capable of storing multiple bits of data. Specifically, data writing (or programming) of a flash memory module is accomplished by applying voltages to specific terminals of the flash memory device (e.g., a control gate voltage changes the amount of electrons in a charge trapping layer in the gate), thereby changing the conduction state of the channel of the memory cell to assume different memory states. For example, in a Multi-Level Cell (MLC) NAND flash memory, when the lower page data is 1 and the upper page data is 1, the control circuit controls the word line control circuit to keep the memory state of the memory Cell at "11" without changing the gate voltage of the memory Cell; when the lower page data is 1 and the upper page data is 0, the word line control circuit changes the gate voltage of the memory cell under the control of the control circuit, so as to change the storage state of the memory cell to "10"; when the lower page data is 0 and the upper page data is 0, the word line control circuit changes the gate voltage in the memory cell under the control of the control circuit, so as to change the memory state of the memory cell to "00"; and, when the lower page data is 0 and the upper page data is 1, the word line control circuit changes the gate voltage of the memory cell under the control of the control circuit, so as to change the storage state of the memory cell to "01". That is, when reading data, the control circuit identifies the memory state of the memory cell according to the gate voltage of the memory cell.

However, in the architecture in which one memory cell can store multiple bits, if the data stored in the memory cells on the same word line is not random enough, the data may be read incorrectly (i.e. read error) due to the factors of uneven data distribution, offset of read voltage, or uneven resistance of bit line. Therefore, how to effectively disturb the written data when writing the data to the rewritable non-volatile memory module is one of the goals addressed by those skilled in the art.

Disclosure of Invention

In view of the above, the present invention provides a data access method, a memory storage device and a memory controller, which can improve the disturbance degree of the written data and further improve the reliability of the data read later.

An embodiment of the present invention provides a data access method for accessing a memory module, the data access method including: receiving first data from a host system; encoding the first data to generate second data, wherein the second data comprises an error correction code corresponding to the first data; performing data scrambling on the second data by a plurality of data scrambling modules respectively to generate a plurality of third data; selecting one of the plurality of third data as fourth data according to the states of the plurality of third data; and storing the fourth data to a first physical unit in the memory module.

An embodiment of the present invention further provides a memory storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used for connecting to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is to: receiving first data from the host system; encoding the first data to generate second data, wherein the second data comprises an error correction code corresponding to the first data; performing data scrambling on the second data by a plurality of data scrambling modules respectively to generate a plurality of third data; selecting one of the plurality of third data as fourth data according to the states of the plurality of third data; and sending a write command sequence to instruct storage of the fourth data to the first physical unit in the memory module.

An embodiment of the present invention further provides a memory controller, which includes a host interface, a memory interface, an error checking and correcting circuit, a plurality of data scrambling modules, and a memory control circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to a memory module. The memory control circuit is connected to the host interface, the memory interface, the error checking and correcting circuit, and the plurality of data scrambling modules. The memory control circuitry is to: receiving first data from the host system; encoding, by the error checking and correction circuit, the first data to generate second data, wherein the second data includes an error correction code corresponding to the first data; performing data scrambling on the second data by the plurality of data scrambling modules respectively to generate a plurality of third data; selecting one of the plurality of third data as fourth data according to the states of the plurality of third data; and sending a write command sequence to instruct storage of the fourth data to the first physical unit in the memory module.

Based on the above, after receiving the first data from the host system, the first data may be encoded to generate second data including error correction codes, and a plurality of third data may be generated by performing data scrambling on the second data by a plurality of data scrambling modules, respectively. One of the plurality of third data may be selected as fourth data according to a state of the plurality of third data. Thereafter, the fourth data may be stored to the first physical unit in the memory module. Therefore, the disturbance degree of the written data can be improved, and the reliability of the data read later is further improved.

Drawings

FIG. 1 is a schematic diagram of a memory storage device shown in accordance with an embodiment of the present invention;

FIG. 2 is a schematic block diagram of a memory controller according to an embodiment of the present invention;

FIG. 3 is a schematic block diagram of a data processing circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a data scrambling and storing flow according to an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating a data scrambling and storing flow according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating data with different levels of data scrambling and corresponding evaluation values, according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a data read and restore process according to an embodiment of the invention;

FIG. 8 is a flow chart illustrating a data access method according to an embodiment of the present invention;

FIG. 9 is a flow chart illustrating a data access method according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a memory storage system shown in accordance with an embodiment of the present invention. Referring to fig. 1, a memory storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 may be any type of computer system. For example. The host system 11 can be various electronic systems such as a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, and a digital camera. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 may include a solid state disk, a U-disk, a memory card, or other type of non-volatile storage device. The host system 11 may be electrically connected to the memory storage device 12 through a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect local Bus (PCI Express), a Universal Serial Bus (USB), or other types of connection interfaces. Thus, the host system 11 may store data to the memory storage device 12 and/or read data from the memory storage device 12.

Memory storage device 12 may include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, the connection interface 121 may support connection interface standards such as SATA, PCI Express, or USB. The memory storage device 12 may communicate with the host system 11 through the connection interface 121.

The memory module 122 is used to store data. The memory module 122 may include a rewritable nonvolatile memory module, and the rewritable nonvolatile memory module may include a plurality of memory cell arrays. The memory cells in the memory module 122 store data in the form of voltages. For example, the memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a two-Level Cell (MLC) NAND flash memory module, a three-Level Cell (TLC) NAND flash memory module, a four-Level Cell (QLC) NAND flash memory module, or other memory modules with similar characteristics.

The memory controller 123 is connected to the connection interface 121 and the memory module 122. Memory controller 123 may be used to control memory storage device 12. For example, the memory controller 123 can control the connection interface 121 and the memory module 122 for data access and data management. For example, the memory controller 123 may include a Central Processing Unit (CPU), or other Programmable general purpose or special purpose microprocessor, Digital Signal Processor (DSP), Programmable controller, Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), or other similar Device or combination thereof.

In one embodiment, memory controller 123 is also referred to as a flash memory controller. In one embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 can receive a sequence of instructions from the memory controller 123 and access the memory cells according to the sequence of instructions.

FIG. 2 is a schematic block diagram of a memory controller according to an embodiment of the present invention. Referring to fig. 2, the memory controller 123 includes a host interface 21, a memory control circuit 22, and a memory interface 23.

The memory control circuit 22 is used to control the overall operation of the memory controller 123. For example, memory control circuitry 22 may have a plurality of control instructions that are executed to perform data writing, reading, and erasing operations during operation of memory storage device 12. When the operation of the memory control circuit 22 is explained below, it is equivalent to the operation of the memory controller 123.

In the present embodiment, the control instructions of the memory control circuit 22 are operated in a firmware manner. For example, the memory control circuit 22 has a microprocessor unit (not shown) and a read only memory (not shown), and the control command is burned into the read only memory. When the memory storage device 12 is in operation, the control instructions are executed by the microprocessor unit to perform data writing, reading, and erasing operations.

In another embodiment, the control instructions of memory control circuitry 22 may also be stored in the form of program code in a particular area of memory module 122 (e.g., a system area of the memory module dedicated to storing system data). Further, the memory control circuit 22 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory controller 123 is enabled, the MCU first executes the boot code to load the control instructions stored in the memory module 122 into the RAM of the memory control circuit 22. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another embodiment, the control instructions of the memory control circuit 22 can also be operated in a hardware manner. For example, the memory control circuit 22 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the memory module 122. The memory write circuit is configured to issue a write command sequence to the memory module 122 to write data into the memory module 122. The memory read circuit is used to issue a sequence of read commands to the memory module 122 to read data from the memory module 122. The memory erase circuit is used for issuing an erase command sequence to the memory module 122 to erase data from the memory module 122. The data processing circuit is used for processing data to be written into the memory module 122 and data read from the memory module 122. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes, respectively, and are used to instruct the memory module 122 to perform corresponding write, read, and erase operations. In one embodiment, the memory control circuitry 22 may also issue other types of instruction sequences to the memory module 122 to instruct the corresponding operations to be performed.

The host interface 21 is electrically connected to the memory control circuit 22 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted from the host system 11 are transmitted to the memory control circuit 22 through the host interface 21. The host interface 21 is compatible with the connection interface standard such as SATA, PCI Express, or USB.

The memory interface 23 is electrically connected to the memory control circuit 22 and is used for accessing the memory module 122. That is, the data to be written into the memory module 122 is converted into a format accepted by the memory module 122 through the memory interface 23. Specifically, if the memory control circuit 22 accesses the memory module 122, the memory interface 23 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence indicating to write data, a read instruction sequence indicating to read data, an erase instruction sequence indicating to erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These instruction sequences are generated by, for example, memory control circuitry 22 and are communicated to memory module 122 via memory interface 23. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

In this embodiment, the memory controller 123 may perform single-frame (single-frame) encoding on data stored in the same physical page, or may perform multi-frame (multi-frame) encoding on data stored in a plurality of physical pages. Depending on the encoding algorithm used, the memory controller 123 may encode the data to be protected to generate corresponding error correction codes and/or error check codes.

In one embodiment, the memory controller 123 also includes an error checking and correction circuit 24, a power management circuit 25, and a buffer memory 26.

The error checking and correcting circuit 24 is electrically connected to the memory control circuit 22 and is used for performing error checking and correcting operations to ensure the correctness of data.

Specifically, when the memory control circuit 22 receives a write command from the host system 11, the error checking and correcting circuit 24 generates a corresponding Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory control circuit 22 writes the data corresponding to the write command and the corresponding error correcting code and/or error detecting code into the memory module 122. Thereafter, when the memory control circuit 22 reads data from the memory module 122, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 24 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code. For convenience of description, the error correction codes are referred to as including error correction codes and/or error check codes.

The power management circuit 25 is electrically connected to the memory control circuit 22 and is used for controlling the power of the memory storage device 12.

The buffer memory 26 is electrically connected to the memory control circuit 22 and is used for temporarily storing data and instructions from the host system 11 or data from the memory module 122.

In one embodiment, memory controller 123 also includes data processing circuitry 27. The data processing circuit 27 is electrically connected to the memory management circuit 22 and can be used to improve the way data is written into the memory module 122. For example, data processing circuit 27 may be used to scramble data to be written to memory module 122 and to restore (i.e., unscramble) data read from memory module 122.

Specifically, in order to make the data written into the memory module 122 in an irregular scattered state, the data is first scrambled (e.g. edited, calculated or rearranged) by the data processing circuit 27 and then written into the memory module 122, so that the data actually written into the memory module 122 is sufficiently scrambled, thereby avoiding data identification errors during reading due to factors such as uneven data distribution, offset of reading voltage or uneven resistance of bit lines. It should be noted that, in this embodiment, the original data is subjected to the scrambling processing by the data processing circuit 27 to obtain new data, and the new data subjected to the scrambling processing is different from the original data before the scrambling. But the ratio of 0 to 1 in the new data is the same as the ratio of 0 to 1 in the original data. Illustratively, the raw data is "101011001", and the ratio of 0 to 1 in the raw data is 4: 5, i.e. comprising 5 1's and 4 0's. The ratio of 0 to 1 in the new data after the scrambling process is also 4: 5, 4 pieces of 1, 5 pieces of 0 or other ratios of 0 to 1 cannot be used, and if other ratios of 0 to 1 are used, it means that the scramble processing has failed. In addition, since the data actually written into the memory module 122 is scrambled, the data read from the memory module 122 is also restored to the original data by the restoration processing performed by the data processing circuit 27.

FIG. 3 is a schematic block diagram of a data processing circuit according to an embodiment of the present invention. Referring to FIG. 3, the data processing circuit 27 may include data scrambling modules 31-34 and a data selecting module 35. It should be noted that the number of the data scrambling modules 31 to 34 in the embodiment of the present invention is not limited to 4, and the number thereof may also be N, where N is any positive integer greater than 1. This example lists 4 for convenience of explanation of the invention.

In the present embodiment, it is assumed that the data scrambling modules 31 to 34 and the data selecting module 35 are all implemented as hardware circuits, but the invention is not limited thereto. In another embodiment, the data scrambling modules 31 to 34 and/or the data selecting module 35 can also be implemented as software or firmware modules, but the invention is not limited thereto.

In the present embodiment, data (also referred to as first data) from the host system 11 can be encoded by the error checking and correcting circuit 24 of FIG. 2 to generate encoded data (also referred to as second data). For example, the second data may include an error correction code corresponding to the first data.

Further, referring to fig. 3, the data scrambling modules 31 to 34 can scramble the second data and output the corresponding scrambled data (also referred to as third data). In one embodiment, the data scrambling modules 31-34 can receive different random numbers from the memory controller of FIG. 2 respectively (for example, FIG. 2 includes a random number generator, not shown in FIG. 2). The data scrambling modules 31-34 can perform data scrambling (e.g., randomizing) on the received data (i.e., the original data or the second data) using the received random numbers as seeds to generate a plurality of corresponding third data.

In the embodiment, the data scrambling modules 31 to 34 are operated in parallel, that is, when the second data is inputted to the data processing circuit 27, the data scrambling modules 31 to 34 generate the corresponding third data according to the second data. Alternatively, in another embodiment, the data scrambling modules 31 to 34 may output the third data in sequence according to the second data instead of operating in parallel.

The data selection module 35 is electrically connected to the data scrambling modules 31 to 34. The data selection module 35 is used for receiving the third data generated by each of the analysis data scrambling modules 31-34. In particular, the data selection module 35 can select one of the third data generated by the data scrambling modules 31 to 34 as the output data (also referred to as the fourth data) of the data processing circuit 27 according to the states of the third data. Alternatively, it can be regarded that the data selection module 35 can generate the fourth data according to the selected third data. The state of the third data may reflect a data scrambling degree (also referred to as a data scrambling degree) of each of the plurality of third data.

In an embodiment, the data selecting module 35 may select the third data with the highest data scrambling degree (i.e. the highest data scattering degree) from the plurality of third data as the fourth data according to the data content (e.g. the distribution of bits "0" and "1") of the third data generated by each of the data scrambling modules 31 to 34. That is, the data selection module 35 may select data with the best scrambling effect from the plurality of third data as the output data (i.e., the fourth data) of the data processing circuit 27.

FIG. 4 is a diagram illustrating a data scrambling and storing flow according to an embodiment of the present invention. Referring to FIG. 4, in one embodiment, the memory control circuit 22 receives data 401 from the host system 11 and inputs the data 401 to the data scrambling modules 31 to 34. The data scrambling modules 31 to 34 can scramble data 401 and output scrambled data 402 to 405. That is, the data 402-405 are generated by the data scrambling modules 31-34 scrambling the same data 401. In particular, the data 402-405 may have varying degrees of data scrambling. For example, data 402 may have a different degree of data scrambling than data 403, data 403 may have a different degree of data scrambling than data 404, and so on.

The data selection module 35 can select one of the data 402-405 according to the state of the data 402-405 and generate the data 406 according to the selected data. For example, the data selection module 35 can select the data with the highest disorder degree from the data 402-405 according to the data content of the data 402-405 and generate the data 406 according to the selected data. For example, assuming that data 403 is more disturbed than the remaining data 402, 404, and 405, data selection module 35 may select data 403 and generate data 406 from data 403. In addition, the remaining unselected data 402, 404, and 405 may be discarded or ignored.

Error checking and correction circuitry 24 may encode data 406 to produce encoded data 407. For example, the data 407 may have an error correction code corresponding to the data 406 to correct the error bits read later when the data 406 is read. Then, the memory control circuit 22 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store the data 407 to the physical unit (also referred to as a first physical unit) 41 in the memory module 122. For example, physical unit 41 may include a physical block of memory module 122 for storing data 407.

FIG. 5 is a diagram illustrating a data scrambling and storing flow according to an embodiment of the present invention. Referring to fig. 5, in one embodiment, the memory control circuit 22 may receive data 501 (i.e., the first data) from the host system 11 and input the data 501 to the error checking and correcting circuit 24. The error checking and correcting circuit 24 may encode the data 501 to generate encoded data 502 (i.e., second data). For example, the data 502 may have an error correction code corresponding to the data 501 to correct the error bits read later when the data 502 is read. Next, the data 502 can be input to the data scrambling modules 31-34.

The data scrambling modules 31 to 34 can perform data scrambling on the data 502 and output the scrambled data 503 to 506 (i.e., the third data), respectively. That is, the data 503-506 are generated by the data scrambling modules 31-34 respectively scrambling the same data 502. In particular, the data 503-506 may have varying degrees of data scrambling. For example, data 503 may have a different degree of data scrambling than data 504, and data 504 may have a different degree of data scrambling than data 505, and so on.

The data selection module 35 can select one of the data 503-506 according to the status of the data 503-506 and generate data 507 (i.e. fourth data) according to the selected data. For example, the data selection module 35 may select the data with the highest degree of data disorder from the data 503-506 according to the data content of the data 503-506 and generate the data 507 according to the selected data. For example, assuming that data 504 is more data-scrambled than the remaining data 503, 505, and 506, data selection module 35 may select data 504 and generate data 507 from data 504. In addition, the remaining unselected data 503, 505, and 506 may be discarded or ignored.

The memory control circuit 22 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store the data 507 to the physical unit 51 (i.e., the first physical unit) in the memory module 122. For example, the physical unit 51 may include a physical block of the memory module 122 for storing the data 507.

In an embodiment, the data selecting module 35 may perform a logic operation on the plurality of third data respectively and evaluate the data scrambling degree of each third data according to an operation result of the logic operation. For example, the data selection module 35 may perform an exclusive or (XOR) or other logic operation on the data bits in the third data to obtain a plurality of evaluation values. The evaluation value may reflect a degree of data scrambling of each third data. Then, the data selection module 35 may select one of the plurality of third data as the fourth data based on the obtained evaluation value.

FIG. 6 is a diagram illustrating data with different levels of data scrambling and corresponding evaluation values, according to an embodiment of the present invention. Referring to FIG. 6, assume that the data 503-506 in FIG. 5 respectively include data 601-604. The data selection module 35 can perform an exclusive-or (XOR) logic operation on the data 601-604 to obtain a plurality of evaluation values 611-614.

Taking the data 601 as an example, the data selection module 35 may sequentially perform an exclusive-or (XOR) operation on two adjacent bits in the data 601 and accumulate the obtained operation values. The data selection module 35 may obtain the evaluation value 611 corresponding to the data 601 from the accumulation result of the operation values. The magnitude of the evaluation value 611 may be positively correlated to the degree of data scrambling of the data 601. For example, when the numerical value of the evaluation value 611 is larger, it indicates that the distribution of bits 0 and 1 in the data 601 is more even and the data scrambling effect of the data 601 is better. By analogy, the evaluation values 611 to 614 can respectively reflect the data scrambling degree of the data 601 to 604. In particular, regardless of the distribution of bits 0 and 1 in the scrambled data, the ratio of 0 to 1 in the scrambled data is the same as the ratio of 0 to 1 in the original data (i.e., the data before scrambling).

The data selection module 35 can evaluate the data scrambling degree of the data 601-604 according to the evaluation values 611-614. Taking fig. 6 as an example, the value of the evaluation value 612 (i.e., 24) is greater than the values of the remaining evaluation values 611, 613, and 614, indicating that the data 602 is more disturbed than the remaining data 601, 603, and 604. Therefore, the data selection module 35 can determine that the data scrambling degree of the data 602 is higher than that of the remaining data 601, 603, and 604 according to the magnitude relationship between the evaluation values 611-614 (i.e. the value of the evaluation value 612 is larger than the values of the remaining evaluation values 611, 613, and 614). Then, the data selection module 35 determines the data 602 corresponding to the evaluation value 612 (i.e. the set of data with the most average distribution of bits 0 and 1, the highest data scrambling degree, and/or the best data scrambling effect) as the fourth data. Thereafter, the data 602 (i.e., the fourth data) may be stored in the first entity unit instead of the original data (i.e., the first data) instructed to be stored by the host system 11.

It should be noted that the exclusive-or (XOR) operation is only an example of one logic operation for evaluating the data scrambling degree, and the invention is not limited thereto. In other embodiments, other types of logic operations may be employed to evaluate the degree of data corruption of particular data, and the invention is not limited.

It should be noted that, in order to correctly restore the original data when reading the data, when storing the fourth data, the write command sequence may actually instruct the memory module 122 to store the fourth data together with the identification information into the first physical unit. In particular, the identification information may correspond to one of the data scrambling modules 31 to 34 (also referred to as a first data scrambling module). For example, the identification information may carry a number corresponding to one of the data scrambling modules 31 to 34 (i.e., the first data scrambling module). Taking fig. 5 as an example, assuming that the data 507 is generated according to the data 504, when the data 507 is written into the entity unit 51, the identification information corresponding to the data scrambling module 32 (i.e., the first data scrambling module) can be stored into the entity unit 51 together. Through the identification information, subsequently, when the data 507 is read, the data 507 may be processed (e.g., anti-scrambled) again by the data scrambling module 32 (i.e., the first data scrambling module) to restore the original data (i.e., the data 502) corresponding to the data 507.

In one embodiment, the memory control circuitry 22 may receive a read instruction from the host system 11. The memory control circuit 22 may send a read instruction sequence to the memory module 122 according to the read instruction to instruct the memory module 122 to read the fourth data from the first physical unit. After reading the fourth data, the memory control circuit 22 may restore the third data to the original data (i.e., the second data) through one of the data scrambling modules 31 to 34 (i.e., the first data scrambling module). Then, the memory control circuit 22 may decode the second data through the error checking and correcting circuit 24 to generate decoded data (i.e., first data) and transmit the first data to the host system 11 in response to the read command.

In an embodiment, the read command sequence may further instruct to read the fourth data from the first entity unit together with the originally stored identification information. Thereby, according to the identification information, a data scrambling module (i.e. the first data scrambling module) which is originally used for scrambling the second data to generate the fourth data can be determined and used for restoring (e.g. performing anti-scrambling) the currently read fourth data.

FIG. 7 is a schematic diagram of a data reading and restoring process according to an embodiment of the invention. It should be noted that, in the embodiment of fig. 5, the data 507 (i.e., the fourth data) is generated according to the data 504 output by the data scrambling module 32 (i.e., the first data scrambling module).

Referring to fig. 7, following the embodiment of fig. 5, according to a read command from the host system 11, data 701 (i.e., fourth data) and identification information corresponding to the data scrambling module 32 can be read from the entity unit 51. From the identification information, data scrambling module 32 may be determined and data 701 may be input to data scrambling module 32. Data scrambling module 32 may perform data descrambling on data 701 to restore data 702. For example, data 702 may be viewed as raw data corresponding to data 701. Then, the error checking and correcting circuit 24 can decode the data 702 (e.g., correct error bits in the data 702) to generate the data 703. The data 703 may then be transmitted to the host system 11 in response to a read command from the host system 11.

FIG. 8 is a flow chart illustrating a data access method according to an embodiment of the invention. Referring to fig. 8, in step S801, first data is received from a host system. In step S802, the first data is encoded to generate second data, wherein the second data includes an error correction code corresponding to the first data. In step S803, data scrambling is performed on the second data by a plurality of data scrambling modules, respectively, to generate a plurality of third data. In step S804, one of the plurality of third data is selected as fourth data according to the states of the plurality of third data. In step S805, the fourth data is stored to the first entity unit in the memory module.

FIG. 9 is a flow chart illustrating a data access method according to an embodiment of the invention. Referring to fig. 9, in step S901, a read command is received from a host system. In step S902, the fourth data is read from the first entity unit according to the read instruction. In step S903, the fourth data is restored to the second data by one of the data scrambling modules (i.e., the first data scrambling module). In step S904, the second data is decoded to generate the first data. In step S905, the first data is transmitted to a host system in response to the read command.

However, the steps in fig. 8 and fig. 9 have been described in detail above, and are not repeated herein. It is noted that the steps shown in fig. 8 and fig. 9 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the methods of fig. 8 and 9 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, according to the embodiments of the present invention, when writing data, the data scrambling modules can be used to scramble the same encoded data and output a plurality of scrambled data. Then, the output scrambled data with the highest data scrambling degree can be stored in the memory module instead of the original data, and the other scrambled data with the lower data scrambling degree can be discarded or ignored (i.e. not stored in the memory module). Therefore, the disturbance degree of the written data can be effectively improved, and the reliability of the data read backwards is further improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (21)

1. A data access method for a memory module, the data access method comprising:

receiving first data from a host system;

encoding the first data to generate second data, wherein the second data comprises an error correction code corresponding to the first data;

performing data scrambling on the second data by a plurality of data scrambling modules respectively to generate a plurality of third data;

selecting one of the plurality of third data as fourth data according to the states of the plurality of third data; and

storing the fourth data to a first physical unit in the memory module.

2. The data access method of claim 1, wherein the plurality of data scrambling modules comprises a first data scrambling module and a second data scrambling module, and wherein a degree of data scrambling of the third data generated by the first data scrambling module is different from a degree of data scrambling of the third data generated by the second data scrambling module.

3. The data access method of claim 1, wherein the state of the plurality of third data reflects a degree of data scrambling of each of the plurality of third data.

4. The data access method of claim 3, wherein the step of selecting the one of the plurality of third data as the fourth data according to the state of the plurality of third data comprises:

selecting, as the fourth data, third data having the highest degree of data shuffling among the plurality of third data.

5. The data access method of claim 1, wherein the step of storing the fourth data to the first entity unit comprises:

storing the fourth data into the first entity unit together with identification information, wherein the identification information corresponds to a first data scrambling module of the plurality of data scrambling modules, and the fourth data is generated by the first data scrambling module.

6. The data access method of claim 1, further comprising:

receiving a read instruction from the host system;

reading the fourth data from the first entity unit according to the reading instruction;

restoring, by a first data obfuscation module of the plurality of data obfuscation modules, the fourth data to the second data;

decoding the second data to produce the first data; and

and transmitting the first data to the host system to respond to the reading instruction.

7. The data access method of claim 6, wherein the step of reading the fourth data from the first physical unit comprises:

and reading the fourth data and identification information from the first entity unit, wherein the identification information corresponds to the first data scrambling module.

8. A memory storage device, comprising:

a connection interface for connecting to a host system;

a memory module; and

a memory controller connected to the connection interface and the memory module,

wherein the memory controller is to:

receiving first data from the host system;

encoding the first data to generate second data, wherein the second data comprises an error correction code corresponding to the first data;

performing data scrambling on the second data by a plurality of data scrambling modules respectively to generate a plurality of third data;

selecting one of the plurality of third data as fourth data according to the states of the plurality of third data; and

sending a write command sequence to instruct storage of the fourth data to a first physical unit in the memory module.

9. The memory storage device of claim 8, wherein the plurality of data scrambling modules comprises a first data scrambling module and a second data scrambling module, and wherein a degree of data scrambling of the third data generated by the first data scrambling module is different from a degree of data scrambling of the third data generated by the second data scrambling module.

10. The memory storage device of claim 8, wherein the state of the plurality of third data reflects a degree of data scrambling of each of the plurality of third data.

11. The memory storage device of claim 10, wherein the operation of selecting said one of said plurality of third data as said fourth data according to said state of said plurality of third data comprises:

selecting, as the fourth data, third data having the highest degree of data shuffling among the plurality of third data.

12. The memory storage device of claim 8, wherein the write instruction sequence indicates that the fourth data is to be stored in the first physical unit with identification information, the identification information corresponds to a first data scrambling module of the plurality of data scrambling modules, and the fourth data is generated by the first data scrambling module.

13. The memory storage device of claim 8, wherein the memory controller is further configured to:

receiving a read instruction from the host system;

sending a reading instruction sequence according to the reading instruction to indicate that the fourth data is read from the first entity unit;

restoring the fourth data into second data through a first data scrambling module in the plurality of data scrambling modules;

decoding the second data to produce the first data; and

and transmitting the first data to a host system to respond to the reading instruction.

14. The memory storage device of claim 13, wherein the sequence of read instructions indicates that the fourth data is to be read out from the first physical unit along with identification information, and the identification information corresponds to the first data obfuscation module.

15. A memory controller, comprising:

a host interface for connecting to a host system;

a memory interface to connect to a memory module;

an error checking and correcting circuit;

a plurality of data obfuscation modules; and

a memory control circuit connected to the host interface, the memory interface, the error checking and correcting circuit, and the plurality of data scrambling modules,

wherein the memory control circuitry is to:

receiving first data from the host system;

encoding, by the error checking and correction circuit, the first data to generate second data, wherein the second data includes an error correction code corresponding to the first data;

performing data scrambling on the second data by the plurality of data scrambling modules respectively to generate a plurality of third data;

selecting one of the plurality of third data as fourth data according to the states of the plurality of third data; and

sending a write command sequence to instruct storage of the fourth data to a first physical unit in the memory module.

16. The memory controller according to claim 15, wherein the plurality of data scrambling modules includes a first data scrambling module and a second data scrambling module, and a degree of data scrambling of the third data generated by the first data scrambling module is different from a degree of data scrambling of the third data generated by the second data scrambling module.

17. The memory controller according to claim 15, wherein the state of the plurality of third data reflects a degree of data scrambling of each of the plurality of third data.

18. The memory controller according to claim 17, wherein the operation of selecting the one of the plurality of third data as the fourth data according to the state of the plurality of third data comprises:

selecting, as the fourth data, third data having the highest degree of data shuffling among the plurality of third data.

19. The memory controller of claim 15, wherein the write command sequence indicates that the fourth data is to be stored in the first physical unit together with identification information, the identification information corresponds to a first data scrambling module of the plurality of data scrambling modules, and the fourth data is generated by the first data scrambling module.

20. The memory controller of claim 15, wherein the memory control circuitry is further configured to:

receiving a read instruction from the host system;

sending a reading instruction sequence according to the reading instruction to indicate that the fourth data is read from the first entity unit;

restoring the fourth data into second data through a first data scrambling module in the plurality of data scrambling modules;

decoding, by the error checking and correction circuit, the second data to produce the first data; and

and transmitting the first data to a host system to respond to the reading instruction.

21. The memory controller according to claim 20, wherein the read instruction sequence indicates that the fourth data is read out from the first physical unit together with identification information, and the identification information corresponds to the first data scrambling module.

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