CN110100236B

CN110100236B - Data reading method and flash memory device

Info

Publication number: CN110100236B
Application number: CN201680091823.7A
Authority: CN
Inventors: 常乐; 石亮; 李乔; 王元钢
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-12-29
Filing date: 2016-12-29
Publication date: 2021-03-23
Anticipated expiration: 2036-12-29
Also published as: WO2018119900A1; CN110100236A

Abstract

When the read data has errors, the flash memory device (1000) preferentially increases the reference voltage between adjacent states with higher error rate, so that the number of the reference voltages can be reduced as much as possible on the basis of ensuring the probability of reading correct data, the voltage comparison times in the data reading process can be reduced, the time of reading correct data is shortened, and the execution time of reading operation is shortened.

Description

Data reading method and flash memory device

Technical Field

The present invention relates to the field of storage technologies, and in particular, to a data reading method and a flash memory device.

Background

In recent years, flash memory technology has been rapidly developed, the storage density has been developed from single bit memory cells to the nearest multi-bit memory cells, such as 6 bits, and the manufacturing process has been developed from 65 nm to the nearest 10 nm. These developments have resulted in a rapid increase in the storage density of flash memory, as well as a substantial decrease in the reliability of flash memory, and therefore require error correction codes with greater error correction capabilities to correctly encode and decode data.

To solve the reliability problem of the flash memory, a currently widely adopted solution is to use a Low Density Parity Check Code (LDPC) error correction mechanism. The LDPC decoding is realized by a belief propagation algorithm and is divided into hard decision decoding and soft decision decoding. When the LDPC is used as the check code, the read request time is associated with the error rate, and the time required for the data read request with high error rate is longer. The read request time comprises two parts: one part is to distinguish the comparison time of the adjacent state compared with a plurality of reference voltages, and the other part is that the increased area needs more bits of bit information to represent, so that the time for transmitting the bit information from the flash memory chip to the controller is longer. The hard decision decoding efficiency is high, the required reading time and decoding time are both short, but only data with low error rate can be decoded. The soft decision can realize correct decoding on data with higher error rate, but needs longer reading time delay and decoding time delay. Therefore, although LDPC can solve the reliability problem of increasingly degraded flash memory, flash memory performance is affected accordingly.

Disclosure of Invention

The application provides a data reading method and a flash memory device, which can reduce the data reading time on the basis of improving the data decoding rate and improve the reading operation performance of the flash memory device.

In a first aspect, the present application provides a data reading method. The method is applied to the flash memory device and is used for reading data in the flash memory device. In the method, after a flash memory device receives a read request for reading a target flash memory page in the flash memory device, the flash memory device reads first data from the target flash memory page according to a reference voltage in a first set of reference voltages. Wherein the target flash page includes a plurality of memory cells, each memory cell for storing data. In the first reference voltage set, the number of reference voltages of a first region is not more than the number of reference voltages of a second region, the reference voltages of the first region are used for distinguishing whether the voltage state in the memory cell is a first state or a second state, the reference voltages of the second region are used for distinguishing whether the voltage state in the memory cell is a third state or a fourth state, the first state, the second state, the third state and the fourth state are set voltage states of the memory cell, and the data error rate between the third state and the fourth state is higher than the data error rate between the first state and the second state. When the flash memory device determines that the first data is error data, the flash memory device reads data from the target flash memory page according to a reference voltage in a second set of reference voltages. Wherein the second set of reference voltages increases the number of reference voltages of the second region on the basis of the first set of reference voltages without increasing the number of reference voltages of the first region.

In the data reading method provided by the embodiment of the invention, in consideration of the asymmetry of errors among different states, when errors occur in read data in the flash memory device, the same number of reference voltages are not simultaneously increased among different adjacent states, but the reference voltages among the adjacent states with higher error rates are preferentially increased. Therefore, the number of reference voltages can be reduced as much as possible on the basis of ensuring the probability of reading correct data, so that the voltage comparison times can be reduced, and the time for reading the correct data can be shortened. Moreover, since the number of reference voltages is small, the state intervals of the voltages of the memory cells are small, and therefore, the time for transmitting the state information is relatively short. Therefore, the execution time of the read operation is shortened.

In one possible implementation, in the second reference voltage set, the number of reference voltages of the second region is greater than the number of reference voltages of the first region.

In yet another possible implementation manner, the number of reference voltages of the first region is not more than 7, and the number of reference voltages of the second region is not more than 7.

In yet another possible implementation manner, the flash memory device further checks the first data according to a low density check code LDPC to determine whether the first data is correct data.

In a second aspect, the present application provides a flash memory device. The flash memory device includes a controller and a flash memory chip connected to the controller. The flash memory chip includes a plurality of flash memory pages for storing data. The controller is configured to execute the data reading method described in the foregoing first aspect and any one of the possible implementation manners of the first aspect.

In a third aspect, the present application provides yet another flash memory device. The flash memory device includes a receiving module and a reading module. The receiving module is used for receiving a read request for reading a target flash memory page in the flash memory device. Wherein the target flash page includes a plurality of memory cells, each memory cell for storing data. The read module is to read first data from the target flash memory page according to a reference voltage of the first set of reference voltages. Wherein, in the first reference voltage set, the number of reference voltages of the first region is not more than the number of reference voltages of the second region. The reference voltage of the first region is used to distinguish whether a voltage state in the memory cell is a first state or a second state. The reference voltage of the second region is used to distinguish whether the voltage state in the memory cell is a third state or a fourth state. The first state, the second state, the third state and the fourth state are voltage states of the set memory cell. A data error rate between the third state and the fourth state is higher than a data error rate between the first state and the second state. The read module is further configured to read data from the target flash memory page according to a reference voltage of a second set of reference voltages when the first data is determined to be erroneous data. Wherein the second set of reference voltages increases the number of reference voltages of the second region on the basis of the first set of reference voltages without increasing the number of reference voltages of the first region.

In one possible implementation, the flash memory device further includes a reference voltage management module and a verification module. The reference voltage management module is configured to set a reference voltage of the first set of reference voltages and a reference voltage of the second set of reference voltages. The check module is used for checking the first data according to a low density check code (LDPC) to determine whether the first data is correct data.

In yet another possible implementation manner, in the second reference voltage set, the number of reference voltages of the second region is greater than the number of reference voltages of the first region.

In a fourth aspect, the present application provides a computer program product comprising a computer readable storage medium storing program code comprising instructions for executing the method of the first aspect as well as any one of the possible implementations of the first aspect.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention.

Fig. 1 is a schematic structural diagram of a flash memory device according to an embodiment of the present invention;

fig. 2 is a schematic diagram of reference voltages in a hard decision decoding process according to an embodiment of the present invention;

fig. 3 is a schematic diagram of reference voltages in a soft-decision decoding process according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a flash memory array according to an embodiment of the present invention;

FIG. 5-A is a diagram illustrating a read status of reading an LSB page in a flash memory device according to an embodiment of the present invention;

FIG. 5-B is a diagram illustrating read states for reading MSB pages in a flash memory device according to an embodiment of the present invention;

FIG. 6 is a flowchart of a data reading method according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a reference voltage according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a reference voltage setting according to an embodiment of the present invention;

FIG. 9-A is a schematic diagram of another reference voltage setting provided by an embodiment of the present invention;

FIG. 9-B is a schematic diagram illustrating another reference voltage setting according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a flash memory device according to an embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

Fig. 1 is a hardware structure diagram of another flash memory device according to an embodiment of the present invention. The flash memory device is a flash memory based storage device, and may be a Solid State Drive (SSD), for example. As shown in fig. 1, the flash memory device 100 may include a controller 102, a host interface 106, and a flash memory array 108.

The host interface 106 is used to connect to and communicate with a host. For example, for receiving an I/O request issued by the host, or for returning data read from the flash array 108 to the host. The host interface 106 may include a Serial Advanced Technology Attachment (SATA) interface, a Universal Serial Bus (USB) interface, a Fibre Channel (FC) interface, or a Peripheral Component Interconnect Express (PCI-E) interface.

And a flash memory array 108 for storing data. Flash array 108 may be comprised of a plurality of memory cells. In the embodiment of the present invention, the flash memory array 108 may also be referred to as a flash memory chip, and the memory cell in the flash memory array 108 refers to a minimum storage medium unit for storing data. The flash memory array 108 may use Single-level cells (SLC) or Multi-level cells (MLC), where each SLC cell stores 1bit of information and each MLC cell stores more than 1bit of data. In the embodiment of the present invention, the memory cells in the flash memory array 108 are MLCs. For example, MLC in which each memory cell stores 2-bit data may be included, and third-order memory cells (TLC) in which each cell stores 3-bit data may also be included.

The controller 102 mainly includes a processor (processor)1022, a cache 1024, and a flash interface 1026. Processor 1022, cache 1024, and flash interface 1026 communicate with one another via a communication bus.

Cache 1024 is a temporary storage memory located between processor 1022 and memory that is smaller in size but faster in switching speed than memory. The cache 1024 is used to cache data to be written by the processor 1022 to the flash array 108 or data read from the flash array 108 for memory transfer.

A flash interface 1026 coupled to the flash array 108 for communicating with the flash array 108 and controlling data transfer with the flash array 108. For example, it may be used to manage access commands to flash array 108 issued by processor 1022 and to perform data transfers. It will be appreciated that multiple communication channels may be included in flash interface 1026 for connecting different memory cells in flash array 108.

Processor 1022 may be a central processing unit CPU, or an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits configured to implement embodiments of the present invention. A software program is installed in the processor 1022, and different software programs can be regarded as one processing module and have different functions. Processor 1022 may implement access requests to flash array 108, or manage data in flash array 108, and the like. For example, the processor 1022 may receive an input/output I/O request forwarded by the host interface 106 through the communication bus, and access the flash memory array 108 through the flash memory interface 1026 according to the I/O request issued by the host, and write data into the flash memory array 108 or read data from the flash memory array 108.

As will be appreciated by those skilled in the art, to ensure the accuracy of data, a parity error correction mechanism is provided in the flash memory device. For example, processor 1022 may include a check and error correction module to perform error detection and correction during data reading. Specifically, when data is written, a check and error correction module within the processor 1022 may generate an ECC signature from the data. The ECC signature is typically saved in a Spare Area (SA) at the back of the flash page. When data is read from the flash memory page, the ECC signature is read by the check error correction module, and whether a data error occurs is judged according to the read data and the ECC signature. If it is detected that the read data contains erroneous bits, an ECC algorithm needs to be used to correct the detected errors. Generally, the ECC algorithm may be BCH encoding or LDPC encoding, etc. The embodiment of the present invention describes and illustrates a scheme by LDPC coding, but it should be understood that the embodiment of the present invention does not limit a coding algorithm adopted by ECC.

The hardware structure of the flash memory device 100 is briefly described above. As is known to those skilled in the art, a flash memory cell represents data by storing an amount of charge. For example, for an MLC storing 2 bits of data, the voltage of a memory cell can be divided into 4 different states: s0, S1, S2 and S3. Specifically, in one case, S0 is used to indicate the voltage state of the memory cell when the data is 11, S1 is used to indicate the voltage state of the memory cell when the data is 10, S2 is used to indicate the voltage state of the memory cell when the data is 00, and S3 is used to indicate the voltage state of the memory cell when the data is 01. In another case, S0 is used to indicate the voltage state of the memory cell when the data is 11, S1 is used to indicate the voltage state of the memory cell when the data is 10, S2 can be used to indicate the voltage state of the memory cell when the data is 01, and S3 is used to indicate the voltage state of the memory cell when the data is 00. The specific encoding method is not limited in the embodiment of the present invention.

As shown in fig. 2, when there is no error in the data stored in the memory cell, the four voltage states are separated from each other without crossing. However, under the influence of retention time, program disturb, etc., the voltage in the flash memory cell may change, and the voltage state shifts to an adjacent state, in which case, errors in the read data may occur. As shown in fig. 3. For example, there may be a crossover between the two voltage states S0 and S1, causing data errors. Similarly, there will also be intersections between S1 and S2 and S2 and S3. Research shows that data errors in the flash memory device have asymmetric characteristics, and error probability of different voltage states is different. As shown in FIG. 3, the error rate is lowest between states S0 and S1 and highest between states S2 and S3.

In order to improve the accuracy of data, an LDPC error correction mechanism is generally used to correct errors of read data in the process of reading data in the prior art. The example is given by using LDPC coding as the check code, and storing 2-bit data in the unit storage unit. In practical application, the scheme of read operation is to firstly adopt LDPC hard decision decoding. Fig. 2 shows reference voltage distribution of LDPC hard decision, where there are only 1 reference voltage between two adjacent states, and there are 3 reference voltages in total between 4 states: v1, V2 and V3. In a read operation, the voltage of each memory cell of the read data page is compared with the three reference voltages to determine the state of the voltage in the memory cell. After reading out the data, if the verification is successful, the reading is successful. If the check is unsuccessful, the decoding needs to be performed again by using soft decision. Fig. 3 is a reference voltage distribution of LDPC soft decision. As shown in fig. 3, there may be multiple reference voltages between two adjacent states. Illustrated in fig. 3 with 5 reference voltages between the two states, there are 15 reference voltages for the four states. These 15 reference voltages divide the voltage of the memory cell into 16 regions. In a read operation, the voltage of each memory cell of a page of data being read is compared to 15 reference voltages to determine the state of the voltage in the memory cell.

For clarity of description, a detailed description of how the flash memory array 108 reads data in the memory cells according to the set reference voltage will be described below. Those skilled in the art will appreciate that the three basic operations of a flash memory device are a read operation, a write operation, and an erase operation. The read operation and the write operation are performed in a page (page) basic unit of operation, and the erase operation is performed in a block (block) basic unit of operation.

Fig. 4 is a schematic diagram illustrating an organization structure of flash memory blocks in the flash memory array 108 according to an embodiment of the present invention. It is understood that the flash array 108 may be in the form of flash chips. As shown in fig. 4, a flash block may be formed of an array of a plurality of memory cells. One row of memory cells is connected to one Word Line (WL), and one column of memory cells is connected to one Bit Line (BL). A row of memory cells may contain one or more pages. In this manner, a flash block may include a plurality of pages, and each page may include a plurality of memory cells. For flash memory arrays using SLC, each cell stores 1bit of information and a row of cells represents a page. For a flash memory array using MLCs, each cell can store at least 2 bits of information, and a row of cells can represent two pages: LSB page and MSB page. In the embodiment of the present invention, the MLC storing 2-bit information in each memory cell is mainly used as an example for description.

As shown in fig. 4, each BL is connected to an amplifier (SA), and data in a memory cell on the BL can be read from the amplifier connected to each BL. When data of a certain page needs to be read, a reference voltage V needs to be added to a word line WL connected with a row of memory cells to be read_ref(reference voltage), and a voltage V is applied to the WL of the other row_pass. Wherein, V_passIs a voltage set higher than the voltage values in all memory cells. Since the voltage values in the memory cells of the other rows are not higher than V_passTherefore, the memory cells in the other rows do not have current to pass to the amplifier, and data cannot be read from the memory cells in the other rows. For a row of memory cells to be read, when the voltage in a certain memory cell is less than V_refWhen it is time, then its BL has no current to the amplifier. When the voltage in a certain memory cell is greater than V_refThen the BL where it is located will have current to the amplifier. In this way, the state of the voltage in the memory cell can be obtained, and the data stored in the memory cell of the row can be read out according to the obtained voltage state and the set encoding mode.

As is known to those skilled in the art, in a flash memory device using the MLC, reference voltage values required when reading the LSB page and the MSB page are different. FIGS. 5-A and 5-B are schematic diagrams of a read operation voltage according to an embodiment of the present invention. As shown in fig. 5-a, when reading data in the LSB page, since the lower bits of data are stored in the LSB page, data represented when the voltage state in the memory cell is in the state S0 and the state S1 are the same, and data represented when the voltage state in the memory cell is in the state S2 and the state S3 are the same. For example, when the voltage states in the memory cells are the S0 and S1 states, the data in the memory cells are both "1"; when the voltage states in the memory cell are the S2 and S3 states, the data in the memory cell is both "1". . An error in the data in the memory cell between the S1 and S2 states may result in an inability to identify whether the memory cell is in the S1 state or the S2 state. Thus, for the data of the LSB page, only the reference voltage between the S1 and S2 states (e.g., pass through) is requiredSuch as V in 5-A_b) It can be determined in which state the voltage of the memory cell is, and the data stored in the memory cell can be read according to the set encoding scheme.

In connection with FIG. 4, assuming that the data of the LSB page connected to WL2 is now to be read, V is set_refThe voltage may be V_b(e.g., V)_b3.159V), voltage V is applied to all other WLs_passIs 5V. The voltage of the memory cell connected with BL1 and BL4 on WL2 is higher than V_refAnd the voltage of the memory cell connected with BL2 and BL3 on WL2 is lower than V_refThus, by increasing the reference voltage V_bIt may be determined that the voltage of the memory cell connected to BL1 and BL4 is in state S2 or state S3, and the voltage of the memory cell connected to BL2 and BL3 is in state S0 or state S1. Furthermore, according to the predetermined encoding method, the data of the LSB page connected to WL2 can be read as 0110.

For MLC, since the data stored in the MSB page is the upper bits of the data stored in the memory cell. As shown in fig. 5-B, if the encoding method is: for example, state S0 indicates 11 data is stored, state S1 indicates 10 data is stored, state S2 indicates 00 data is stored and state S2 indicates 01 data is stored. The data stored in the MSB page: respectively "1", "0" and "1". Since the data represented by state S0 and state S1 are different and the data represented by state S2 and state S3 are different in the MSB page shown in FIG. 5-B, a memory cell may experience an error between state S0 and state S1 and an error between state S2 and state S3. Thus, in actual practice, in order to correctly read the data of the MSB page, the reference voltage between state S0 and state S1 (e.g., V in FIG. 5-B) needs to be increased_a) To distinguish whether the voltage in the memory cell is in the S0 state or the S1 state. Also, the reference voltage between state S2 and state S3 (e.g., V in FIG. 5-B) needs to be increased_c) To distinguish whether the voltage in the memory cell is in the S2 state or the S3 state.

Specifically, when it is necessary to read the data of the MSB page, V_refV in FIG. 5-B can be taken first_aGet V again_c. As shown in the figure5-B, when the voltage in a memory cell is below Va, the data in the memory cell can be judged to be "1". When the voltage in the memory cell is higher than Va, it cannot be determined that the reference voltage V needs to be passed again_cAnd further judging. If the voltage in the memory cell is less than V_cDetermining the data in the memory cell to be "0" if the voltage in the memory cell is greater than V_cThe data in the memory cell is determined to be "1". In another expression, when the voltage in a memory cell is smaller than Va when reading data of the MSB page, the data in the memory cell is determined to be "1". When the voltage in the memory cell is greater than Va and less than V_cIf so, the data in the memory cell is judged to be 0. When the voltage in the memory cell is greater than Vc, the data in the memory cell is determined to be "1".

It can be understood that if the encoding method is: for example, state S0 indicates 11 data is stored, state S1 indicates 10 data is stored, state S2 indicates 01 data is stored and state S2 indicates 00 data is stored, then the data stored in the MSB page: respectively "1", "0", "1" and "0". According to this encoding scheme, the data represented by state S0 and state S1 are different, the data represented by state S1 and state S2 are different, and the data represented by state S2 and state S3 are different, so that the memory cell may have an error between state S0 and state S1, an error between state S1 and state S2, and an error between state S2 and state S3. In this case, when reading data of the MSB page, it may be necessary to determine what state the voltage in the memory cell is in by 3 reference voltages. The specific data reading manner is similar to the method for reading the data of the MSB page shown in fig. 5-B, and is not described herein again.

The following description will be made of how to read the data of the MSB page in particular, taking as an example reading the data of the MSB page connected to WL2 in fig. 4. Assuming Va 2.549V and Vc 3.605V, the flash array 108 first adds Va to WL2, and since the voltage of the memory cell connected to BL3 is 2.3V and lower than 2.549V, the data stored in the memory cell connected to WL2 and BL3 can be determinedThe number 1 is not determined for the data of other memory cells. Flash array 108 then sets V_refVc is applied to WL2 to read data of memory cells that have not been read by reference voltage Va. In this way, data in the memory cells connected to BL1, BL2 and BL4 on WL2 can be read according to the reference voltage Vc. Specifically, since the voltages of the memory cells connected to BL1 and BL2 are both smaller than Vc (Vc ═ 3.605V), comparing the voltages in the memory cells with Vc results in that the data of the memory cells connected to BL1 and BL2 are 0. Since the voltage of the memory cell connected to BL4 is 4.2V, the value of the memory cell is 1. By setting the voltages Va and Vc to WL2, respectively, the data connecting the MSB page of WL2 can be obtained as: 0011.

as one skilled in the art will appreciate, the time for a read operation includes mainly both the read time of the data and the transfer time of the data. As can be seen from the above description, the read time is positively correlated to the number of reference voltages, and the transmission time is positively correlated to the amount of data transmitted. Assuming that N reference voltages are set, dividing the voltage value in the flash memory cell into N +1 regions requires ceil (Log)₂(N +1)) bits to represent N +1 voltage regions. Wherein, the reading time is in positive correlation with N, the transmission time is in positive correlation with ceil (Log2(N +1)), and ceil () represents rounding up. In the case of LDPC hard decision decoding, as shown in fig. 2, since there are only three reference voltages, the read time is short. Ceil (Log) is required because the voltage of the memory cell is divided into 4 states₂(4) 2 bits to record information, and the transmission time is short. Under the condition of adopting LDPC soft-decision decoding, the reading time is longer when the decoding is carried out through the soft-decision because the compared voltage is more. As shown in FIG. 3, ceil (Log) is required since the voltage of the memory cell is divided into 16 states₂(16) 4 bits to record information, and the time to transmit status information is relatively long. If the read data still fails to be decoded, the reading precision can be improved by gradually increasing the number of reference voltages between adjacent states until the data to be read is correctly decoded.

It is understood that softThe decided reference voltage distribution is not limited to the example in fig. 3, and the number of reference voltages between adjacent two states is variable. In practice, a maximum of 7 reference voltages can be set between the two states. When 7 reference voltages are set between two states, the total number of the four states is 21, and the 21 reference voltages can divide the voltage of the memory cell into 22 regions, so that ceil (Log) is required in total₂(22) 5 bits) to record information. The number of reference voltages between two adjacent states determines the error rate of data that can be tolerated by LDPC decoding. The larger the number of reference voltages, the higher the tolerable error rate and the higher the probability of correct decoding. However, as described above, in reading data of the MSB page, at least two regions of reference voltages are required, and the larger the number of reference voltages, the longer the read operation time. In order to optimize the read operation performance of the flash memory device, particularly to optimize the read operation performance of reading the MSB page in the flash memory device using the MLC, the present application provides a method for reading data, which can shorten the read operation time on the basis of improving the accuracy of the data. The method for reading data in the present application can be implemented by the processor 1022 in fig. 1. The data reading method in the present application will be described in detail below with reference to fig. 1.

Fig. 6 is a flowchart of a data reading method according to an embodiment of the present invention, which can be specifically executed by the flash memory device 100 shown in fig. 1. As shown in fig. 6, the method may include the following steps.

In step 602, flash memory device 100 receives a read request. One skilled in the art will recognize that the basic unit of a read operation of flash memory device 100 is a page (page). In practice, when flash memory device 100 receives a read request, flash memory device 100 may translate the logical address to be accessed in the read request into a physical address. Therefore, the flash memory device can determine the flash memory page to be accessed in the reading operation according to the physical address obtained by conversion.

As described above, the flash memory device reads data by comparing the voltage of each memory cell in a flash memory page to be read with a set reference voltage, respectively. Upon receipt of the read request, step 604, the flash memory device 100 may be based on the set reference voltage set SV_iReading data D in flash memory page by reference voltage in (1)_i. Wherein i is used for expressing the number of times of reading data, i is a natural number not less than 1, SV_iFor expressing the ith set of reference voltages, D_iFor indicating the data read for the ith time. Specifically, the processor 1022 in the flash memory device 100 may select a reference voltage required for reading data this time according to a preset reference voltage value, and send the selected reference voltage to the flash memory array 108, so that the flash memory array 108 compares the voltage in the memory cell in the flash memory page to be read with the set reference voltage to read the data in the memory cell, and transmits the read data to the processor 1022. As previously described, when data of the MSB page needs to be read, at least two reference voltages are required. For the sake of description, the reference voltages set by the processor 1022 are referred to as a reference voltage set in the embodiment of the present invention. Wherein, at least two reference voltages are included in one reference voltage set.

In practical applications, the reference voltage value required during the read operation may be preset in the processor 1022. The processor 1022 may set the reference voltage required for the read operation according to a preset reference voltage value. Fig. 7 is an example of a reference voltage value according to an embodiment of the present invention. As shown in fig. 7, an example provided in the embodiment of the present invention includes 15 reference voltage values, and the 15 reference voltage values can divide the voltage of the memory cell into 16 states. As described above, since the data error rates occurring between different states are different, in the embodiment of the present invention, the set reference voltage values are mainly concentrated in the crossing regions between adjacent states, and the values of the reference voltages are non-uniformly set. As described above, since the data of the LSB page and the MSB page are read, the values of the reference voltages required to be selected are different. Therefore, in practical applications, when setting the reference voltage, the processor 1022 may select the corresponding reference voltage according to whether the data to be read is the data of the LSB page or the data of the MSB page. Reading the data of the MSB page is taken as an example in the embodiment of the present invention.

As can be seen from the above description, when the processor 1022 determines that data in the MSB needs to be read, the reference voltage selected by the processor 1022 needs to include at least two regions of reference voltages in step 404: such as the first region and the second region shown in fig. 5-B. Wherein the reference voltage of the first region is used to distinguish whether the voltage in the memory cell is in the S0 state or the S1 state, and the reference voltage of the second region is used to distinguish whether the voltage in the memory cell is in the S2 state or the S3 state.

In the embodiment of the present invention, the reference voltage SV1 set by the processor 1022 includes two references: 2.549V and 3.605V are examples. Wherein 2.549 is the reference voltage of the first region, and 3.605 is the reference voltage of the second region. In this step, the flash memory array 108 may apply 2.549V and 3.605V to the word line connected to the flash memory page to be read, respectively, to read the data D1 in the flash memory page to be read.

In step 606, the flash memory device 100 determines whether the read data Di is correct. For example, after the flash array 108 reads the data D1 from the flash array according to the reference voltage set by the processor 1022, the flash array 108 may transmit the read data D1 to the processor 1022, so that the error correction checking module in the processor 1022 may check and correct the data D1 read this time by using the ECC algorithm to determine whether the data D1 is correct data. In the embodiment of the present invention, the read first data may be decoded by using an LDPC decoding method to determine whether the first data is correct data. In the embodiment of the present invention, a specific decoding method is not limited.

As shown in FIG. 6, in step 606, when the read data D is determined_iIf the data is correct, the method proceeds to step 608, and the reading operation is ended. When the read data D is determined_iIf the data is erroneous, i is made to be i +1, the method returns to step 604, and the processor 1022 resets the set of reference voltages SV_iAnd the flash array 108 reads data from the flash page to be read according to the reference voltage in the reset reference voltage set SVi.

In the embodiment of the present invention, the probability of error between states S3 and S2 is greater because of the consideration of the asymmetry of error between different states, and because of research findings. Therefore, in order to correctly read data, the processor 1022 needs to increase the number of reference voltages. However, to reduce the read time, in an embodiment of the present invention, processor 1022 does not simultaneously increase the same amount of voltage between all states when resetting the reference voltage. Specifically, the processor 1022 may preferentially increase the reference voltage for distinguishing the states S3 and S2 without simultaneously increasing the reference voltage for distinguishing the states S0 and S1. Stated another way, the processor 1022 may preferentially increase the reference voltage of the second region as shown in fig. 5-B. According to this manner, in the embodiment of the present invention, when the processor determines that the read data error requires resetting of the reference voltages, the number of reference voltages for distinguishing the states S3 and S2 is greater than the number of reference voltages for distinguishing the states S0 and S1 in the reset reference voltage set. How to increase the reference voltage in the embodiment of the present invention will be described in detail with reference to fig. 8 and 6.

As shown in fig. 6, when the processor 1022 determines that the read data Di is error data in step 606, the flash memory device 100 reads data in a flash memory page to be accessed according to the reference voltage in the reset reference voltage set. For clarity of description, in the embodiment of the present invention, the set of reference voltages set by the processor at the ith time is referred to as a first set of reference voltages, and the set of reference voltages set by the processor at the (i +1) th time is referred to as a second set of reference voltages. As shown in fig. 8, in the embodiment of the present invention, the processor 1022 sets a reference voltage in each of the first area and the second area for the first time. When the method returns to step 604, the processor 1022 may only increase the number of reference voltages of the second area without increasing the number of reference voltages of the first area. Stated another way, in the process of setting the reference voltage set for the second time, the processor 1022 sets the second reference voltage set to include reference voltages of 2 second regions and reference voltages of 1 first region. For example, in the set second set of reference voltages, reference voltages may be included: 2.549V, 3.605V and 3.503V. As shown in detail in fig. 9-a.

In the embodiment of the invention, in order to reduce the number of voltage comparison and shorten the time for reading data, when the reference voltage is increased, at most one reference voltage can be increased in one area each time. Of course, in practical application, it is also possible to increase at most two reference voltages in one region at a time according to practical situations. In the embodiment of the present invention, the increased voltage value is not specifically limited, and may be a voltage in a corresponding region.

In step 604, the flash array 108 will again access the data in the flash page according to the reference voltages in the second set of reference voltages set by the processor 1022. A specific method of reading data may be referred to the foregoing description of the method of reading data of the MSB page. In an embodiment of the present invention, the data read by the flash memory device 108 according to the reference voltages in the second set of reference voltages may be referred to as second data.

The method proceeds to step 606 again, the processor 1022 determines whether the read second data is correct, if so, the reading operation is ended, and if not, the method returns to step 604, and the processor sets the reference voltage again. For convenience of description, the set of reference voltages set by the processor 1022 at the (i + 2) th time is referred to as a third set of reference voltages. In the third set of reference voltages, processor 1022 may increase the reference voltages of the first region and the second region at the same time. For example, in the third set of reference voltages, the processor may set the reference voltages: 2.549V, 2.665V, 3.605V, 3.503V and 3.72V. Then, the flash array 108 reads the data D3 in the flash page to be read according to the set third set of reference voltages. And in step 606, the processor determines whether the read data D3 is correct data. If not, the method can also proceed to step 604, where the flash memory device 100 again resets the reference voltage, e.g., the reset reference voltage can be as shown in FIG. 9-B, and reads data based on the reset reference voltage. In an embodiment of the present invention, if the data is incorrect, steps 604 and 606 may be performed in a loop until the correct data is read and the read operation ends.

As mentioned above, the reference voltage of each region can be increased by 7 at most. In the embodiment of the present invention, how the processor 1022 sets the reference voltages of the different regions may be as shown in fig. 8. In the sequence of increasing the reference voltage shown in fig. 8, the reference voltage of the second region is increased every time, but the reference voltage of the first region is not increased every time. While the reference voltage of the second region may be increased, the reference voltage of the first region may be increased once every other time. For example, the reference voltage of the first region is increased only at

times

3, 5, and 7. After the reference voltages of the second area are all increased, if the data is still incorrect, the reference voltages of the first area may be sequentially increased. It is understood that the sequence and number of increasing the reference voltages shown in fig. 8 are only an example, and in practical applications, the reference voltages of the first region may be increased in other sequences as long as the reference voltages of the second region are preferentially increased. In other words, in the embodiment of the present invention, when increasing the reference voltage, it is only necessary to preferentially increase the reference voltage of the second region, and there may be a plurality of increasing manners for the reference voltage of the first region. In this way, the number of reference voltages of the second region may be more than the number of reference voltages of the first region in resetting the reference voltages.

In the data reading method provided by the embodiment of the invention, in consideration of the asymmetry of errors between different states, when reading data in the flash memory device, the reference voltages between different adjacent states are preferentially increased rather than the reference voltages between adjacent states with higher error rates, which are increased by the same number at the same time. Therefore, the number of reference voltages can be reduced as much as possible on the basis of ensuring the probability of reading correct data, so that the voltage comparison times can be reduced, and the time for reading the correct data can be shortened. Moreover, since the number of reference voltages is small, the state intervals of the voltages of the memory cells are small, and therefore, the time for transmitting the state information is relatively short. Therefore, the execution time of the read operation is shortened.

Fig. 10 is a schematic structural diagram of another flash memory device according to an embodiment of the present invention. As shown in FIG. 10, the flash memory device 1000 includes a receiving module 1002, a reference voltage management module 1004, a reading module 1006, and a verifying module 1008. The receiving module 1002 is configured to receive a read request for reading a target flash memory page in the flash memory device. Wherein the target flash page includes a plurality of memory cells, each memory cell for storing data.

The reference voltage management module 1004 is configured to set a reference voltage in a first set of reference voltages required for a read operation performed according to the read request. Wherein, in the first reference voltage set, the number of reference voltages of the first region is not more than the number of reference voltages of the second region. The reference voltage of the first region is used to distinguish whether a voltage state in the memory cell is a first state or a second state. The reference voltage of the second region is used to distinguish whether the voltage state in the memory cell is a third state or a fourth state. The first state, the second state, the third state and the fourth state are voltage states of the set memory cell. A data error rate between the third state and the fourth state is higher than a data error rate between the first state and the second state.

The read module 1004 is used to read first data from the target flash memory page according to a reference voltage of a first set of reference voltages.

The checking module 1008 is configured to check the first data read by the reading module 1004 to determine whether the first data is correct data. Specifically, the checking module 1005 may check the read data by using ECC encoding. In this embodiment of the present invention, the checking module 1005 may check the first data according to a low density check code LDPC to determine whether the first data is correct data.

The reference voltage management module 1004 is further configured to set a reference voltage in a second reference voltage set when the verification module 1008 determines that the first data is error data. Wherein the second set of reference voltages increases the number of reference voltages of the second region on the basis of the first set of reference voltages without increasing the number of reference voltages of the first region.

The read module 1006 is also configured to read data from the target flash memory page according to the reference voltages in the second set of reference voltages when the check module 1008 determines that the first data is erroneous data.

It is understood that the respective modules in the flash memory device 1000 are respectively used for performing the respective steps in the foregoing respective method embodiments. For a detailed description of the modules in the flash memory device 1000, reference may be made to the detailed description of the steps in the foregoing method embodiments.

It should be noted that the expressions "first", "second", and the like in the embodiment of the present invention are only for distinguishing different objects, and do not limit the embodiment of the present invention otherwise.

An embodiment of the present invention further provides a computer program product of a data reading method, including a computer-readable storage medium storing a program code, where the program code includes instructions for executing the method flow described in any one of the foregoing method embodiments. It will be understood by those of ordinary skill in the art that the foregoing storage media include: various non-transitory machine-readable media that can store program code, such as a U-Disk, a removable hard Disk, a magnetic Disk, an optical Disk, a Random-Access Memory (RAM), a Solid State Disk (SSD), or a non-volatile Memory (non-volatile Memory).

It should be noted that the examples provided in this application are only illustrative. For example, the division of the components in the above embodiments may be implemented in other ways. For example, multiple modules or components may be combined or may be integrated into another device, or some features may be omitted, or not implemented. In addition, the coupling or direct coupling or communication connection between the components shown or discussed may be an indirect coupling or communication connection through some communication interfaces, modules, and may include an electrical connection, a mechanical connection, or other forms of connection.

It will be clear to those skilled in the art that, for convenience and brevity of description, the description of each embodiment has been given with emphasis on the description of the embodiments, and some parts not described in detail in a certain embodiment may be referred to the related description of other embodiments. The features disclosed in the embodiments of the invention, in the claims and in the drawings may be present independently or in combination. Features described in hardware in embodiments of the invention may be implemented by software and vice versa. And are not limited herein.

Claims

1. A data reading method for reading data in a flash memory device, the method comprising:

receiving a read request for reading a target flash page in the flash memory device, wherein the target flash page comprises a plurality of memory cells, each memory cell for storing data;

reading first data from the target flash memory page according to reference voltages in a first reference voltage set, wherein in the first reference voltage set, the number of reference voltages of a first region is not more than the number of reference voltages of a second region, the reference voltages of the first region are used for distinguishing whether the voltage state in the memory cell is a first state or a second state, the reference voltages of the second region are used for distinguishing whether the voltage state in the memory cell is a third state or a fourth state, the first state, the second state, the third state and the fourth state are set voltage states of the memory cell, and the data error rate between the third state and the fourth state is higher than the data error rate between the first state and the second state;

and when the first data is error data, reading data from the target flash memory page according to reference voltages in a second reference voltage set, wherein the second reference voltage set is increased by the number of reference voltages of a second area on the basis of the first reference voltage set without increasing the number of reference voltages of a first area.

2. The method of claim 1, wherein:

in the second reference voltage set, the number of reference voltages of the second region is greater than the number of reference voltages of the first region.

3. The method according to claim 1 or 2, characterized in that:

the number of reference voltages of the first region is not more than 7, and the number of reference voltages of the second region is not more than 7.

4. The method of claim 1 or 2, further comprising:

and checking the first data according to a low density check code (LDPC) to determine whether the first data is correct data.

5. A flash memory device comprises a controller and a flash memory chip connected with the controller, and is characterized in that the flash memory chip comprises a plurality of flash memory pages for storing data;

the controller is configured to:

receiving a read request for reading a target flash memory page in the flash memory device, wherein the target flash memory page comprises a plurality of memory cells, each memory cell is used for storing data, and the target flash memory page is one of the plurality of flash memory pages;

6. The flash memory device of claim 5, wherein:

7. The flash memory device of claim 5 or 6, wherein the controller is further configured to:

8. The flash memory device of claim 5 or 6, wherein:

9. A flash memory device, comprising:

a receiving module, configured to receive a read request for reading a target flash memory page in the flash memory device, where the target flash memory page includes a plurality of memory units, and each memory unit is used for storing data;

a reading module, configured to read first data from the target flash memory page according to a reference voltage in a first reference voltage set, where in the first reference voltage set, the number of reference voltages of a first region is not more than the number of reference voltages of a second region, the reference voltage of the first region is used to distinguish whether a voltage state in a memory cell is a first state or a second state, the reference voltage of the second region is used to distinguish whether a voltage state in a memory cell is a third state or a fourth state, the first state, the second state, the third state and the fourth state are set voltage states of the memory cell, and a data error rate between the third state and the fourth state is higher than a data error rate between the first state and the second state;

the reading module is further configured to read data from the target flash memory page according to reference voltages in a second set of reference voltages when the first data is error data, wherein the second set of reference voltages is increased by the number of reference voltages of the second area on the basis of the first set of reference voltages without increasing the number of reference voltages of the first area.

10. The flash memory device of claim 9, further comprising:

a reference voltage management module to set reference voltages in the first set of reference voltages and reference voltages in the second set of reference voltages;

and the checking module is used for checking the first data according to a low density check code (LDPC) to determine whether the first data is correct data.

11. The flash memory device of claim 9 or 10, wherein:

12. The flash memory device of claim 9 or 10, wherein:

13. A computer-readable storage medium, characterized in that the computer-readable storage medium is configured to store a program code comprising instructions for performing the method according to any of the claims 1-4.