CN116185309B - Data processing method and data storage device - Google Patents
Data processing method and data storage device Download PDFInfo
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- CN116185309B CN116185309B CN202310465181.4A CN202310465181A CN116185309B CN 116185309 B CN116185309 B CN 116185309B CN 202310465181 A CN202310465181 A CN 202310465181A CN 116185309 B CN116185309 B CN 116185309B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a data processing method and data storage equipment, and belongs to the technical field of storage. The data processing method comprises the following steps: establishing a decoding map, wherein the decoding map identifies the decoding state of each data unit in a flash memory page; acquiring a read voltage, and decoding the data units in the flash memory page under the read voltage; if the data unit which is successfully decoded exists under the reading voltage, carrying out data transmission according to the decoding state of the data unit; if the data unit which is successfully decoded does not exist, updating a reading voltage, and decoding the data unit in the flash memory page under the updated reading voltage until the transmission of the data unit in the flash memory page is completed or all the reading voltages are traversed. The data processing method provided by the invention can improve the data reading capability and efficiency.
Description
Technical Field
The invention belongs to the technical field of storage, and particularly relates to a data processing method and data storage equipment.
Background
During the working process of the data storage device, the data can be in error due to the problems of aging, read-write interference, temperature difference and the like of the data storage device. Therefore, during the process of writing data, the data and the error correction code (Error Correcting Code, ECC) codes are written into the flash memory cells, and during the process of reading data, the data is decoded according to the ECC codes.
Because the flash memory is in different environments, the erasing times and the reading times of each data unit in the flash memory page are different, and the charge loss degree is different, the optimal reading voltage of each data unit is different during decoding. At one read voltage, a portion of the data cells within the flash page are read successfully, but a portion of the data cells fail to read. Resulting in low data reading efficiency and poor reading capability.
Disclosure of Invention
The invention aims to provide a data processing method and data storage equipment, which solve the problems of low reading efficiency and poor reading capability.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a data processing method, which at least comprises the following steps:
establishing a decoding map, wherein the decoding map identifies the decoding state of each data unit in a flash memory page;
acquiring a read voltage, and decoding the data units in the flash memory page under the read voltage;
if the data unit which is successfully decoded exists under the reading voltage, carrying out data transmission according to the decoding state of the data unit; if the data unit which is successfully decoded does not exist, updating a reading voltage, and decoding the data unit in the flash memory page under the updated reading voltage until the transmission of the data unit in the flash memory page is completed or all the reading voltages are traversed.
In an embodiment of the present invention, the data transmission according to the decoding status of the data unit includes the following steps: and transmitting the data in the data unit which is successfully decoded to a host computer, and updating the decoding map.
In an embodiment of the present invention, the data processing method further includes the steps of:
judging whether the data unit in the flash memory page is decoded, if yes, ending the flow, and if not, judging whether the unused read voltage exists.
In an embodiment of the present invention, the data processing method further includes creating an optimal decoding voltage array and a voltage length array, where an element in the optimal decoding voltage array records an optimal reading voltage of the data unit, and an element in the voltage length array records the data unit corresponding to the optimal reading voltage and a number of consecutive data units covered by the optimal reading voltage after the data unit.
In an embodiment of the present invention, the data transmission according to the decoding status of the data unit includes the following steps: updating the decoding map, the optimal decoding voltage array and the voltage length array.
In an embodiment of the present invention, the data transmission according to the decoding status of the data unit further includes the following steps: judging whether the optimal reading voltage exists in each data unit in the flash memory page, and if the optimal reading voltage exists in each data unit, reading the data in each data unit in the flash memory page according to the optimal decoding voltage array and the voltage length array.
In one embodiment of the present invention, updating the decoding map, the optimal decoding voltage array, and the voltage length array includes the steps of:
and positioning a data unit according to the arrangement sequence of the data units, and judging whether the data unit is successfully decoded or not.
In an embodiment of the present invention, when the data unit is successfully decoded, a first element corresponding to the data unit in the voltage length array of the flash memory page under the current read voltage and a second element corresponding to the data unit in the voltage length array of the flash memory page under the previous read voltage are obtained.
In an embodiment of the present invention, when the first element is greater than or equal to the second element, the second element is covered with the first element in the array of voltage lengths of the flash memory page, and the previous read voltage is covered with the current read voltage in the array of best decoding voltages of the flash memory page.
In an embodiment of the present invention, when the first element is smaller than the second element, the second element is kept unchanged in the voltage length array of the flash memory page, and the previous read voltage is kept unchanged in the optimal decoding voltage array of the flash memory page.
The invention also provides a data storage device having stored thereon a computer program which, when executed by a processor, implements a data processing method as described above.
As described above, the data processing method and the data storage device provided by the invention decode the data unit in the flash memory page under different read voltages. And data transmission is carried out on the data units in one flash memory page under different reading voltages, so that the data units in the flash memory page can finish data transmission under one, two or more reading voltages. The decoding capability and decoding efficiency are improved. And the optimal reading voltage of each data unit is obtained by setting the optimal decoding voltage array and the voltage length array, so that the host has the minimum reading times when reading the data in the flash memory page, and the decoding efficiency is further improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a data storage device in the present application.
Fig. 2 is a flowchart of a data processing method in the present application.
FIG. 3 is a flow chart of another data processing method in the present application.
FIG. 4 is a flow chart of updating the voltage array and the voltage length array for optimal decoding of each data unit in the present application.
FIG. 5 is a diagram illustrating a flash memory page composition and decoding map structure according to the present application.
FIG. 6 is a state diagram of the decoding map, the best decoding voltage array and the voltage length array at the 0 th set of read voltages in the present application.
FIG. 7 is a state diagram of the decoding map, the best decoding voltage array and the voltage length array at the 1 st set of read voltages in the present application.
FIG. 8 is a state diagram of the decoding map, the best decoding voltage array and the voltage length array at the 2 nd set of read voltages in the present application.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, an electronic device is provided, and includes a host 200 and a data storage device 100. Wherein the host 200 and the data storage device 100 may be implemented as separate chips, modules, or devices, or may be included in a single device. For example, the data storage device 100 may be an integrated single storage device that is then connected to the host 200. However, the present disclosure is not limited to this example. That is, in another example, host 200 and data storage device 100 may be integrated into a single device.
Referring to FIG. 1, in some embodiments, a data storage device 100 is connected to a host 200 (e.g., an information processing apparatus) via an interface and a power line. The host 200 is constituted by, for example, a personal computer, a CPU core, a server connected to a network, or the like. The host 200 performs data access control on the data storage device 100, for example, by sending a write request, a read request, and a delete request to the data storage device 100, and performs writing, reading, and deleting of data to the data storage device 100.
Referring to fig. 1, in some embodiments, the data storage device 100 may be, for example, a Solid State Disk (SSD). And the data storage device 100 may include a controller 110 and a nonvolatile memory unit 120. The nonvolatile memory cell 120 is a nonvolatile memory cell 120 (non-transitory memory) that does not lose data even if power is turned off, and the nonvolatile memory cell 120 may be a NAND flash memory, a vertical NAND (VNAND) memory, a NOR flash memory, a Resistive Random Access Memory (RRAM), a phase change memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), or a spin transfer torque random access memory (STT-RAM). The nonvolatile memory cells 120 may include a memory cell array block connected to word lines, string select lines, ground select lines, and bit lines. The nonvolatile memory unit 120 may include a super block including a plurality of memory blocks. The plurality of memory blocks may include a plurality of pages. The nonvolatile memory cells 120 may include a two-dimensional (2D) memory array block or a three-dimensional (3D) memory array block. Other types of nonvolatile memory cells 120 may also be used. In the present embodiment, the NAND type flash memory is described as an example, and it is understood that other nonvolatile memory cell 120 structures may be used in other embodiments.
Referring to fig. 1, in some embodiments, the nonvolatile memory unit 120 is electrically connected to the controller 110 and is used for storing data written by the host 200. The nonvolatile memory unit 120 has a flash memory block therein. The flash memory blocks may belong to the same memory die (die) or to different memory dies. Each flash block has a plurality of flash pages, and each flash page has at least one physical sector, wherein the flash pages belonging to the same flash block can be independently written and simultaneously erased. For example, each flash block is made up of 128 flash pages. In another embodiment, each flash block may be composed of 64 flash pages, 256 flash pages, or any other flash pages.
Referring to FIG. 1, a flash block (block) is the minimum unit of erase. That is, each flash block contains a minimum number of memory cells that are erased together. A flash page may be the smallest unit that is programmable. That is, a flash page is the smallest unit of read data and write data. However, in some embodiments, the written data and the smallest unit of writing may also be a smaller memory unit. Each flash page typically includes a data bit region and a redundancy bit region. The data bit region is used to store user data, and the redundant bit region is used to store system data (e.g., error checking and correction codes).
Referring to fig. 1, in some embodiments, during the process of writing data by the host, the data and error correction code (Error Correcting Code, ECC) codes are written into the flash memory cells, and during the process of reading the data, the data is decoded according to the ECC codes. In this embodiment, when encoding or decoding data, the length of encoding or decoding is 2KB or 4KB. In this application, a unit that is encoded or decoded simultaneously is referred to as a data unit (CW), that is, a size of 2KB or 4KB for the data unit. In other embodiments, the size of the data units may also be set depending on the length of the encoding or decoding. In this application, a data unit may be defined as a programmable minimum unit. That is, a data unit is the smallest unit of read data and write data.
Referring to FIG. 1, in some embodiments, the nonvolatile memory Cell 120 is a Multi Level Cell (MLC) NAND flash memory module. In other embodiments, the nonvolatile memory Cell 120 may also be a single-Level memory Cell (Single Level Cell, SLC) NAND flash memory module, a triple-Level Cell (TLC) NAND flash memory module, a Quad-Level Cell (QLC) NAND flash memory module, a five-Level Cell (PLC) NAND flash memory module, other flash memory modules, or other memory modules having the same characteristics.
Referring to fig. 1, in an embodiment of the present invention, a logical address to physical address (L2P) mapping table and data are stored in the nonvolatile memory unit 120, and each logical address to physical address mapping table stores a physical address corresponding to each logical address. When reading data, a specific physical address of the required data in the nonvolatile memory unit 120 can be searched according to the logical address to physical address mapping table.
Referring to fig. 1, in an embodiment of the present invention, a buffer 111 is configured in the controller 110, and the buffer 111 may be a volatile memory capable of writing or reading data at a high speed, such as a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), a latch, a flip-flop, or a register.
Referring to fig. 1, in an embodiment of the present invention, a control unit 112 is further disposed in the controller 110, and the control unit 112 is configured to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type, and perform operations of writing, reading, erasing, etc. of data in the nonvolatile memory unit 120 according to the instructions of the host 200.
Referring to fig. 1 to 2, the data storage device 100 provided by the present invention is a computer readable storage device, and a computer program is stored on the data storage device 100, and when the computer program is executed by the controller 110, the data processing method according to the present invention is implemented. The data processing method provided by the invention comprises steps S101 to S109.
Step S101, a decoding map is established.
Referring to fig. 1 and 2, in an embodiment of the present invention, a decoding map may be established in the buffer 111 for each flash page to be read, where the decoding map may identify whether the data unit in the flash page is successfully decoded. At least one byte is arranged in the decoding map, and the number of identification bits in the decoding map is equal to the number of data units in the flash memory page. Each identification bit in the decoding map is set corresponding to a data unit in the flash memory page, and each identification bit represents the decoding state of one data unit.
Referring to fig. 5, in an embodiment of the present invention, a flash page is, for example, 32KB in size, and a data unit is, for example, 4KB in size, and then 8 data units are included in a flash page. The decoding map corresponding to the flash page is one byte long and includes 8 bits, each bit being an identification bit, each identification bit representing the decoding status of one data unit. When one identification bit is set to the first data, the current data unit is not successfully decoded, and when one identification bit is set to the second data, the current data unit is successfully decoded or the host does not need to read the data. In this embodiment, the first data is, for example, 1, and the second data is, for example, 0.
Step S102, obtaining a reading voltage.
In one embodiment of the present invention, the read voltage may include a default read voltage for a plurality of gears of the data storage device. In other embodiments of the present invention, the read voltage may also include a plurality of gear read voltages set according to the historical read voltage range. In still other embodiments of the present invention, the read voltage may further include a read voltage for a plurality of gears set according to a temperature, a number of erasures, a number of reads, and a charge loss level of the flash memory.
Step S103, decoding the data unit in the flash page under a read voltage.
In an embodiment of the present invention, in step S103, the read voltage is any one of the read voltages of the plurality of gear positions acquired in step S102. When decoding data cells in a flash page at a read voltage, only cells in the flash page that are not read are decoded. I.e. only the data unit corresponding to the bit set to the first data is decoded.
Step S104, judging whether the data unit which is successfully decoded exists, if so, executing step S105 to step S107, and if not, executing step S108.
Step S105, the data in the successfully decoded data unit is transferred to the host.
Step S106, updating the decoding map.
Step S107, judging whether the decoding of the data unit in the flash memory page is completed, if so, indicating that the reading is successful, and ending the flow. If there are still undecoded data units, step S108 is performed.
Referring to fig. 2, in an embodiment of the present invention, when in step S104, at a certain read voltage, there is a data unit that is successfully decoded, step S105 and step S106 are performed first, and data in the data unit that is successfully decoded is transferred to the host, so as to complete the transfer of the data in the data unit. And updating the decoding map when there is a successfully decoded data unit. I.e. the identification bit corresponding to the data unit for which the decoding is completed in step S104 is modified from the first data to the second data. In this application, step S105 and step S106 may be performed simultaneously or sequentially. When the steps S105 and S106 are executed before and after each other, the order of the steps S105 and S106 is not limited, and the steps S105 and S106 may be executed first, or the steps S106 may be executed first, and then the steps S105 may be executed.
Referring to fig. 2, in an embodiment of the invention, after the identification bit corresponding to the data unit is modified from the first data to the second data, the identification bit is not cleared. At this time, when the read voltage is updated, the second data is not read again at the previous read voltage, and the decoding efficiency is further improved.
Referring to fig. 2, in an embodiment of the present invention, after the data in the successfully decoded data unit is transferred to the host and the decoding map is updated, step S107 is executed to determine whether the decoding of the data unit in the flash memory page is completed. In the present application, whether the decoding of the data unit in the flash memory page is completed can be determined by determining whether all the identification bits in the decoding map are the second data. And if the identification bits in the decoding map have the first data, the data unit to be decoded still exists in the flash memory page. When the decoding of the data unit in the flash memory page is completed, the reading is successful, and the process is finished. If there are data units to be decoded in the flash page, the read voltage needs to be adjusted to decode the data units in the flash page again.
Step S108, judging whether there is an unused read voltage, if there is no unused voltage, indicating that the read has failed, and if there is an unused voltage, executing step S109.
Step S109, update the read voltage, and return to step S103.
In one embodiment of the present invention, in step S104, there is no data unit successfully decoded, and in step S107, when decoding of the data unit in the flash page is not completed, step S108 is performed to determine whether there is an unused read voltage. The unused read voltage is the read voltage acquired in step S103 and is not used when decoding the flash page. I.e. the unused read voltage is the read voltage acquired in step S103 and not selected in step S103 or in the loop step S109.
In an embodiment of the present invention, if there is still an unused voltage, step S109 is performed to update the read voltage. That is, a read voltage is selected among the unused read voltages, and steps S103 to S109 are performed again. If there is no unused read voltage, it indicates that the read voltage acquired in step S103 is used up and that there is still an undecoded data unit in the flash page, and at this time, it indicates that the read of the flash page fails.
Referring to fig. 2, in step S101 to step S109, after decoding of a data unit is completed, data in the successfully decoded data unit is transferred to the host. In transferring data to a host, a direct memory access (Direct Memory Access, DMA) is required to be initiated to transfer the data in the successfully decoded data unit to the host. Each time DMA is started, the hint location and length of the data unit that needs to be transferred need to be configured. When the successfully decoded data units in the flash page are discontinuous, the DMA needs to be started for multiple times according to the division of the data units. As shown in fig. 5, once decoding successful data cell CW4 and data cell CW6 requires two DMA starts to transfer the data in both data cells to the host. And in the process of transmitting the data to the host for many times, if the data unit which cannot be decoded exists at last, the data transmitted to the host in the early stage cannot be used, and resource waste can be caused.
In another embodiment of the present invention, referring to fig. 3, a data processing method is further provided, and the data processing method includes steps S201 to S209.
Step S201, a decoding map, an optimal decoding voltage array and a voltage length array are established.
Referring to fig. 3, in another embodiment of the present invention, the decoding map in step S201 is the same as the decoding map in step S101, and it can be identified whether the data unit in the flash memory page is successfully decoded. Each identification bit in the decoding map represents the decoding status of one data unit. When one identification bit is set to be the first data, the current data unit is not successfully decoded under the reading voltage, and when one identification bit is set to be the second data, the current data unit is successfully decoded under the reading voltage or the host does not need to read the data.
Referring to fig. 3, in another embodiment of the present invention, after the identification bit corresponding to the data unit is modified from the first data to the second data, the identification bit is cleared (the identification bit is set to the first data) when the read voltage is updated. The identification in the decoded map is given a decoding status at a different read voltage. In this embodiment, when the read voltages are updated, the data cells are re-read at each read voltage because the identification bits are cleared first.
Referring to fig. 1 and 3, in another embodiment of the present invention, an optimal decoding voltage array and a voltage length array are also established in the buffer 111. The optimal decoding voltage array and the voltage length array comprise a plurality of elements, and each element in the optimal decoding voltage array and the voltage length array corresponds to one data unit in the flash memory page. The elements in the optimal decoding voltage array record the optimal reading voltage corresponding to the data units, and the elements in the voltage length array record the data units corresponding to the optimal reading voltage and the number of continuous data units covered by the optimal reading voltage after the data units.
Referring to FIG. 6, in another embodiment of the present invention, when the flash page is read using the 0 th set of read voltages, and the data cell CW4 and the data cell CW6 of the flash page are decoded. Then in the decoding map corresponding to the 0 th set of read voltages, the identification bit of the data cell CW4 and the data cell CW6 is set to the second data, i.e., 0. The identification bit of the other data unit is considered as the first data, i.e. 1. In the optimal decoding voltage array at this time, the element corresponding to the data cell CW4 and the data cell CW6 is set to 0, which means that the 0 th set of read voltages is the optimal read voltage for the data cell CW4 and the data cell CW 6. In the voltage length array at this time, the element corresponding to the data cell CW4 and the data cell CW6 is set to 1, which means that at the 0 th set of read voltages (optimum read voltages), only the data cell CW4 and the data cell CW6 can be decoded, and no other data cell after the data cell CW4 and the data cell CW6 can be decoded at the 0 th set of read voltages, the number is 1.
Step S202, obtaining a reading voltage.
Referring to fig. 3, in another embodiment of the present invention, the read voltage may include a default read voltage for a plurality of gears of the data storage device. In other embodiments of the present invention, the read voltage may also include a plurality of gear read voltages set according to the historical read voltage range. In still other embodiments of the present invention, the read voltage may further include a read voltage for a plurality of gears set according to a temperature, a number of erasures, a number of reads, and a charge loss level of the flash memory.
Step S203 decodes the data unit in the flash page under a read voltage.
Referring to fig. 3, in another embodiment of the present invention, in step S203, the read voltage is any one of the read voltages of the plurality of gears acquired in step S202. When decoding read cells in a flash page at a read voltage, cells in the flash page that are not read are decoded. I.e. only the data unit corresponding to the bit set to the first data is decoded.
Step S204, judging whether the data unit which is successfully decoded exists, if so, executing step S205 to step S207, and if not, executing step S108.
Step S205, updating the decoding map, the optimal decoding voltage array and the voltage length array.
Referring to fig. 6 to 8, in another embodiment of the present invention, when updating the decoding map, a decoding map is corresponding to each read voltage, which indicates the decoding status of each data unit in the flash memory page at the current read voltage.
Referring to fig. 4, in an embodiment of the invention, updating the best decoding voltage array and the voltage length array includes steps S2051 to S2058.
S2051, positioning a data unit according to the data unit arrangement sequence.
Referring to fig. 1, in another embodiment of the present invention, a data unit may be first located according to the data unit arrangement order. In this embodiment, the data cell CW0 may be located first. In other embodiments, the data cell CW7 may be located first.
Step 2052, determining whether the data unit is successfully decoded at the read voltage, if so, executing steps S2053 to S2055, and if not, executing step S2056.
Referring to fig. 1, in another embodiment of the present invention, whether the identification bit corresponding to the data unit is the second data can be determined according to the current decoding map, so as to determine whether the current data unit is successfully decoded under the read voltage. If the data unit is successfully decoded at the read voltage, steps S2053 to S2056 are performed, and if the data unit is not successfully decoded at the read voltage, step S2057 is performed.
S2053, obtaining a first element corresponding to the data unit in the voltage length array of the flash memory page under the current read voltage, and a second element corresponding to the data unit in the voltage length array of the flash memory page under the previous read voltage.
S2054, judging whether the first element is larger than or equal to the second element, if the first element is larger than or equal to the second element, executing step S2055, and if the first element is smaller than the second element, executing step S2056.
S2055, in the voltage length array, the second element is covered by the first element, and in the best decoding voltage array, the previous read voltage is covered by the current read voltage.
S2056, keeping the optimal decoding voltage array and the voltage length array unchanged.
S2057, judging whether the current data unit is the last data unit, and ending the flow if the current data unit is the last data unit. If the current data unit is not the last data unit, step S2058 is performed, the next data unit is switched, and step S2052 is returned.
Referring to fig. 4, in an embodiment of the present invention, if the first element is greater than or equal to the second element, the acquired read voltage and voltage length are used as the elements of the data unit in the optimal decoding voltage array and voltage length array under the current read voltage. If the first element is smaller than the second element, the obtained read voltage and voltage length are used as the elements of the data unit in the optimal decoding voltage array and the voltage length array under the previous read voltage.
Referring to FIG. 6, in another embodiment of the present invention, first, the flash memory page is read using the 0 th set of read voltages. At this time, the data cell CW4 and the data cell CW6 of the flash page are decoded. Then in the decoding map corresponding to the 0 th set of read voltages, the identification bit of the data cell CW4 and the data cell CW6 is set to 0 and the identification bits of the other data cells are set to 1. Then in the loop, in the best decoding voltage array and the voltage length array, only the elements corresponding to data element CW4 and data element CW6 are updated, and the elements corresponding to data element CW0, data element CW1, data element CW2, data element CW3, data element CW5 and data element CW7 are not updated.
Referring to fig. 6, in another embodiment of the present invention, when updating the data cell CW4 and the data cell CW6, the first element corresponding to the data cell CW4 and the data cell CW6 in the voltage length array of the flash memory page is 1 at the current read voltage (the 0 th set of read voltages). Since there is no previous read voltage, the second element corresponding to data cell CW4 and data cell CW6 in the array of voltage lengths of the flash page at the previous read voltage is 0. At this time, if the first element 1 is greater than the second element 0, the elements corresponding to the data unit CW4 and the data unit CW6 in the voltage length array are all covered with the second element, i.e. modified to 1. In the optimal decoding voltage array, the element corresponding to data cell CW4 and data cell CW6 is modified to the current read voltage, i.e., 0. The optimal read voltage for data cell CW4 and data cell CW6 is shown as group 0 read voltage.
Referring to fig. 6 to 7, in another embodiment of the present invention, the flash memory pages are then read using the 1 st set of read voltages. At this time, the data cells CW2, CW3, CW4, CW6, and CW7 of the flash page are decoded. Then in the decoding map corresponding to the 1 st set of read voltages, the identification bits of data cell CW2, data cell CW3, data cell CW4, data cell CW6, and data cell CW7 are set to 0, and the identification bits of the other data cells are set to 1. Then in the loop, in the best decoding voltage array and the voltage length array, the elements corresponding to data cell CW2, data cell CW3, data cell CW4, data cell CW6, and data cell CW7 are updated, and the elements corresponding to data cell CW0, data cell CW1, and data cell CW5 are not updated.
Referring to fig. 6 to 7, in another embodiment of the present invention, elements corresponding to the data cells CW2, CW3, CW4, CW6 and CW7 are updated. At the current read voltage (the 1 st set of read voltages), in the array of the voltage length of the flash memory page, the first element corresponding to the data cell CW2 is 3, the first element corresponding to the data cell CW3 is 2, the first element corresponding to the data cell CW4 is 1, the first element corresponding to the data cell CW6 is 2, and the first element corresponding to the data cell CW7 is 1. At the previous read voltage (group 0 read voltage), the second element corresponding to data cell CW4 and data cell CW6 in the array of voltage lengths of the flash page is 1, and the second element corresponding to data cell CW2, data cell CW3 and data cell CW6 is 0. At this time, in the voltage length array, the first element of the data cell CW2 is larger than the second element, the first element of the data cell CW3 is larger than the second element, the first element of the data cell CW4 is equal to the second element, the first element of the data cell CW6 is larger than the second element, and the first element of the data cell CW7 is equal to the second element. Then the elements corresponding to data cell CW2, data cell CW3, data cell CW4, data cell CW6, and data cell CW7 in the array of voltage lengths are all overlaid with the first element. That is, in the voltage length array, the element corresponding to the data cell CW2 is 3, the element corresponding to the data cell CW3 is 2, the element corresponding to the data cell CW4 is 1, the element corresponding to the data cell CW6 is 2, and the element corresponding to the data cell CW7 is 1. And in the optimal decoding voltage array, modifying the corresponding elements of the data unit CW2, the data unit CW3, the data unit CW4, the data unit CW6 and the data unit CW7 to the current reading voltage, namely 1. The optimal read voltages for data cell CW2, data cell CW3, data cell CW4, data cell CW6, and data cell CW7 are indicated as group 1 read voltages.
Referring to fig. 7 to 8, in another embodiment of the present invention, the flash memory pages are then read using the group 2 read voltage. At this time, the data cells CW0, CW1, CW5, CW6, and CW7 of the flash page are decoded. Then in the decoding map corresponding to the 1 st set of read voltages, the identification bits of data cell CW0, data cell CW1, data cell CW5, data cell CW6, and data cell CW7 are set to 0, and the identification bits of the other data cells are set to 1. Then in the loop, in the best decoding voltage array and the voltage length array, the elements corresponding to data cell CW0, data cell CW1, data cell CW5, data cell CW6, and data cell CW7 are updated, and the elements corresponding to data cell CW2, data cell CW3, and data cell CW4 are not updated.
Referring to fig. 7 to 8, in another embodiment of the present invention, elements corresponding to the data cells CW0, CW1, CW5, CW6 and CW7 are updated. At the current read voltage (the 2 nd set of read voltages), in the array of voltage lengths of the flash memory page, the first element corresponding to the data cell CW0 is 2, the first element corresponding to the data cell CW1 is 1, the first element corresponding to the data cell CW5 is 3, the first element corresponding to the data cell CW6 is 2, and the first element corresponding to the data cell CW7 is 1. At the previous read voltage (group 1 read voltage), the second element corresponding to data cell CW0 is 0, the second element corresponding to data cell CW1 is 0, the second element corresponding to data cell CW5 is 0, the second element corresponding to data cell CW6 is 2, and the second element corresponding to data cell CW7 is 1 in the array of voltage lengths of the flash memory pages. At this time, in the voltage length array, the first element of the data cell CW0 is larger than the second element, the first element of the data cell CW1 is larger than the second element, the first element of the data cell CW5 is equal to the second element, the first element of the data cell CW6 is equal to the second element, and the first element of the data cell CW7 is equal to the second element. Then the elements corresponding to data cell CW0, data cell CW1, data cell CW5, data cell CW6, and data cell CW7 in the array of voltage lengths will all be overlaid with the first element. That is, in the voltage length array, the element corresponding to the data cell CW0 is 2, the element corresponding to the data cell CW1 is 2, the element corresponding to the data cell CW5 is 3, the element corresponding to the data cell CW6 is 2, and the element corresponding to the data cell CW7 is 1. And in the optimal decoding voltage array, modifying the elements corresponding to the data unit CW0, the data unit CW1, the data unit CW5, the data unit CW6 and the data unit CW7 into the current reading voltage, namely 2. The optimal read voltages for data cell CW0, data cell CW1, data cell CW5, data cell CW6, and data cell CW7 are indicated as group 2 read voltages.
Step S206, judging whether each data unit has the best reading voltage, if so, executing step S207, and if not, executing step S208.
Step S207, reading the data in each data unit in the flash memory page according to the optimal decoding voltage array and the voltage length array.
Step S208, it is determined whether or not there is an unused read voltage, and if there is no unused voltage, it indicates that the read has failed, and if there is an unused voltage, step S209 is performed.
Step S209, update the read voltage, and return to step S203.
Referring to fig. 4, in another embodiment of the present invention, in step S207, when an optimal read voltage exists for each data cell, each data cell representing the flash page can be decoded under the existing read voltage. The data in each data cell in the flash page is read according to the optimal decoding voltage array and the voltage length array. At this time, each data unit may be decoded according to the elements in the optimal decoding voltage array and the voltage length array, that is, the corresponding data unit may be decoded using the read voltage recorded in the optimal decoding voltage array.
Referring to fig. 4, in another embodiment of the present invention, in step 204, there is no data unit successfully decoded, and in step S206, when there is not an optimal read voltage for each data unit, step S208 is performed to determine whether there is an unused read voltage. The unused read voltage is the read voltage acquired in step S203 and is not used when decoding the flash page. I.e. the unused read voltage is the read voltage acquired in step S203 and not selected in step S203 or in the loop step S209.
Referring to fig. 4, in another embodiment of the present invention, if there is still an unused voltage, step S209 is performed to update the read voltage. That is, a read voltage is selected among the unused read voltages, and steps S203 to S209 are performed again. If there is no unused read voltage, it indicates that the read voltage acquired in step S203 is exhausted, and that there is still an undecoded data unit in the flash page, and at this time, it indicates that the read of the flash page fails.
Referring to fig. 6 to 8, when one flash page is read using the same read voltage, the flash page shown in fig. 6 to 8 fails to be read at a plurality of read voltages, and cannot be read. When the flash page is read using the data processing method shown in fig. 2, three reads are required, the first read data cell CW4 and data cell CW6, the second read data cell CW2, data cell CW3 and data cell CW7, and the third read data cell CW0, data cell CW1 and data cell CW5. By using the data processing method shown in fig. 2, the data reading capability can be increased, and the reading efficiency can be improved. When the flash page is read using the data processing method shown in fig. 3, only the second reading is required, the first reading of data cell CW2, data cell CW3 and data cell CW4, and the second reading of data cell CW0, data cell CW1, data cell CW5, data cell CW6 and data cell CW7. The reading efficiency can be further improved by using the data processing method as shown in fig. 3.
In summary, in the management method of the data storage device provided by the present invention, firstly, a decoding map is established, then a read voltage is obtained, and a data unit in a flash memory page is decoded under a read voltage. And under the reading voltage, if the data unit which is successfully decoded exists, carrying out data transmission according to the decoding state of the data unit. If the data unit which is successfully decoded does not exist, the reading voltage is updated, and the data unit in the flash memory page is decoded under the updated reading voltage until the transmission of the data unit in the flash memory page is completed or all the reading voltages are traversed.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A data processing method, comprising at least the steps of:
establishing a decoding map, wherein the decoding map identifies the decoding state of each data unit in a flash memory page;
acquiring a read voltage, and decoding the data units in the flash memory page under the read voltage;
if the data unit which is successfully decoded exists under the reading voltage, carrying out data transmission according to the decoding state of the data unit; if the data unit which is successfully decoded does not exist, updating a reading voltage, and decoding the data unit which is not read in the flash memory page under the updated reading voltage until the transmission of the data unit in the flash memory page is completed or all the reading voltages are traversed;
and establishing an optimal decoding voltage array and a voltage length array, wherein the elements in the optimal decoding voltage array record the optimal reading voltage of the data unit, and the elements in the voltage length array record the data unit corresponding to the optimal reading voltage and the number of continuous data units covered by the optimal reading voltage after the data unit.
2. The data processing method according to claim 1, wherein the data transmission according to the decoding status of the data unit comprises the steps of: and transmitting the data in the data unit which is successfully decoded to a host computer, and updating the decoding map.
3. The data processing method according to claim 1, characterized in that the data processing method further comprises the steps of:
judging whether the data unit in the flash memory page is decoded, if yes, ending the flow, and if not, judging whether the unused read voltage exists.
4. The data processing method according to claim 1, wherein the data transmission according to the decoding status of the data unit comprises the steps of: updating the decoding map, the optimal decoding voltage array and the voltage length array.
5. The data processing method according to claim 4, wherein the data transmission according to the decoding status of the data unit further comprises the steps of: judging whether each data unit in the flash memory page has the optimal reading voltage or not, and if each data unit has the optimal reading voltage, reading the data in each data unit in the flash memory page according to the optimal decoding voltage array and the voltage length array.
6. The data processing method of claim 4, wherein updating the decoding map, the optimal decoding voltage array, and the voltage length array comprises the steps of:
and positioning a data unit according to the arrangement sequence of the data units, and judging whether the data unit is successfully decoded or not.
7. The method of claim 6, wherein when the data unit is successfully decoded, a first element corresponding to the data unit in the array of voltage lengths of the flash memory page at a current read voltage and a second element corresponding to the data unit in the array of voltage lengths of the flash memory page at a previous read voltage are obtained.
8. The data processing method of claim 7, wherein when the first element is greater than or equal to the second element, the second element is overlaid with the first element in a voltage length array of the flash page, and a previous read voltage is overlaid with a current read voltage in an optimal decoding voltage array of the flash page.
9. The data processing method of claim 7, wherein when the first element is smaller than the second element, the second element is kept unchanged in a voltage length array of the flash memory page, and a previous read voltage is kept unchanged in an optimal decoding voltage array of the flash memory page.
10. A data storage device having stored thereon a computer program which when executed by a processor implements the data processing method of claim 1.
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