KR20130102397A

KR20130102397A - Flash memory and reading method of flash memory

Info

Publication number: KR20130102397A
Application number: KR1020120023597A
Authority: KR
Inventors: 이상훈; 윤석민; 유선미; 이종열
Original assignee: 삼성전자주식회사
Priority date: 2012-03-07
Filing date: 2012-03-07
Publication date: 2013-09-17

Abstract

PURPOSE: A flash memory and a reading method of the flash memory improve the error correction capability at the flash memory which does not support soft decision. CONSTITUTION: Hard data about a first target page is sensed using a first hard read voltage (S120). Soft data about the first target page is generated by using a pair of soft read voltages whose voltage level is different from that of the first hard read voltage while a flash memory performs a first operation for the sensed hard data (S140). [Reference numerals] (S120) Hard data about a first target page is sensed using a first hard read voltage; (S140) Soft data about the first target page is generated by using a pair of soft read voltages whose voltage level is different from that of the first hard read voltage while a flash memory performs a first operation for the sensed hard data

Description

Read method of flash memory and flash memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory and a read method in a flash memory, and more particularly, to a flash memory and a read method in a flash memory capable of improving error correction capability even in a flash memory not supporting soft decision.

Flash memory is scaled down according to the demand for high integration, and the number of bits stored in each memory cell is increasing. Thus, the lead margin between each program state is decreasing. Therefore, read errors occur frequently. Therefore, methods for accurately and quickly performing read error correction have been discussed. However, as logic for correcting a read error is added to the flash memory, a problem such as a large chip size of the flash memory may occur.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a flash memory and a read method in a flash memory capable of improving error correction capability even in a flash memory not supporting soft decision.

According to at least one example embodiment of the inventive concepts, a method of reading a flash memory may include: sensing hard data for a first target page at a first hard read voltage; And generating soft data for the first target page using at least one pair of soft read voltages having different voltage levels from the first hard read voltage while the first operation is performed on the hard data.

The pair of first soft read voltages may be set by changing the voltage level of the first hard read voltage twice.

The pair of first soft read voltages may be set by changing a voltage level of a second hard read voltage for a second target page programmed with a number of bits different from the first target page.

The pair of first soft read voltages may be set by changing voltage levels of the pair of second hard read voltages with respect to the second target page, respectively.

The pair of first soft read voltages may be set by changing a voltage level of one second hard read voltage twice for the second target page.

The voltage level of the pair of soft read voltages may be set in a ready state for the array of flash memories.

Generating soft data for the first target page may include: detecting state information indicating a program state of the first target page from the hard data; And changing the status information to correspond to a read mode for the second target page.

The changing of the state information may be performed by using a test mode command of the flash memory.

The first target page may be a page programmed with a single bit.

The generating of the soft data for the first target page may include: transmitting a first soft value of sensing the first target page to one of the pair of soft read voltages to a first latch; And cooking a second soft value obtained by sensing the first target page with another one of the pair of soft read voltages and the first soft value of the first latch.

The cooking of the first soft value and the second soft value may include performing a bitwise operation on the first soft value and the second soft value to perform a first bit value of the first soft value. The bit value having the value may be changed to the second value.

Cooking the first soft value and the second soft value may be performed using a test mode command of the flash memory.

The first target page may be a page programmed to be multi-bit, and the first hard read voltage may be set to two or more different voltage levels corresponding to the number of the multi-bits.

The generating of the soft data for the first target page may include: a first soft value of sensing the first target page by one of the first pair of soft read voltages with respect to the first voltage level of the first hard read voltage; Is transmitted to a first latch and cooks the second soft value sensing the first target page with another one of the soft read voltages of the first pair and the first soft value of the first latch. Transmitting a third soft value due to the soft read voltage of the second latch value; And transmits a first soft value of sensing the first target page to the first latch as one of the soft read voltages of the second pair corresponding to the second voltage level of the first hard read voltage. Cooking a second soft value sensing the first target page with the other one of the soft read voltages and the first soft value of the first latch to obtain a third soft value by the second soft read voltages; ; And cooking a third soft value by the second pair of soft read voltages and a third soft value of the second latch to change the third soft value of the second latch.

Obtaining the third soft value sequentially for all of the voltage levels of the first hard read voltage, and changing the third soft value of the second latch; And outputting the third soft value of the second latch as the soft data.

The first operation may be an operation of outputting the sensed hard data from the flash memory.

The first operation may be an operation of backing up the sensed hard data stored in one of a plurality of latches of a buffer unit of the flash memory to another latch of the buffer unit.

The method may further include continuously outputting the backed up hard data and the soft data.

The flash memory includes a plurality of memory cell arrays, each of the memory cell arrays including the first target page, and sensing of the hard data and generation of the soft data for each of the first target pages. Can be performed.

Sequentially outputting the backed up hard data of the first target page of each of the memory cell arrays and the soft data of the first target page of each of the memory cell arrays sequentially to the memory cell array. It may be further provided.

The generating of the soft data may be performed when a read error of the first target page exists or when a read error of the first target page is not corrected.

The generating of the soft data is performed when a read retry for correcting a read error of the first target page fails, and the read retry for the first target page is performed by the flash. With reference to a wear-out table indexing each block of the memory, among the read retry tables provided differently for each endurance state section of the flash memory, a corresponding read retry table (read Starting from a read level included in one of the indices of the retry table, it may be repeated up to the last read level of the last index.

The wear degree table may have an ISPE loop count (Incremental Step Pulse Erase Loop Count) value required to erase blocks of the flash memory in response to an erase command.

The flash memory does not have separate logic for generating the soft data, and may generate the soft data using a command set in the flash memory.

A read method for a multi-level cell NAND flash memory according to an embodiment of the present invention may include: sensing hard data for a first target page using a first hard read voltage; At least one pair of pages for the pages programmed with a greater number of bits than the first target page while the hard data is backed up from the first latch to the second latch among the plurality of latches included in the buffer unit of the flash memory. Sensing soft data by changing the voltage level of the second hard read voltage, and storing the soft data in a third latch; And continuously outputting the soft data and the backed up hard data.

A solid state drive according to an exemplary embodiment of the present invention performs a read operation on the flash memory using the read method of claim 1.

According to the flash memory and the read method in the flash memory according to the embodiment of the present invention, there is an advantage that the error correction capability can be efficiently improved even in the flash memory that does not support the soft decision.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.
1 is a flowchart illustrating a read method in a flash memory according to an exemplary embodiment of the present invention.
2 is a block diagram illustrating a flash memory according to an exemplary embodiment of the present invention.
3A to 3C are diagrams illustrating an example of a memory cell array of the flash memory of FIG. 2.
4A through 4E are diagrams showing distributions of memory cells of the flash memory of FIG. 2.
5 is a diagram illustrating an example of a read error.
FIG. 6 is a diagram illustrating an example of a reading method of FIG. 1 with respect to a first target page included in an SLC region.
7 and 8 are diagrams showing an example of a method of generating soft data.
FIG. 9 is a diagram illustrating an example of a read method for a case in which a first target page of an MLC region is an LSB page of FIG. 4D or 4E.
10 is a flowchart illustrating generation and change of state information.
FIG. 11 is a diagram illustrating an example of a method of detecting state information indicating a program state of a first target page from the sensed hard data of FIG. 10.
12 is a diagram illustrating an example of a read method when the first target page is programmed with higher bits of a multi-bit.
FIG. 13 is a flowchart illustrating a method of generating soft data for the first target page of FIG. 12, and FIG. 14 is a diagram illustrating an operation of generating soft data according to the method of FIG. 13.
FIG. 15 shows an example of a read method when the first target page is an MSB page of 3-bit MLC.
16 is a flowchart illustrating a method of generating soft data when the first hard read voltage is provided at a plurality of levels.
17A, 17B, and 18 are diagrams illustrating examples in which soft data and hard data are output in a read method for a flash memory according to an embodiment of the present invention.
FIG. 19 is a diagram illustrating a flash memory according to an exemplary embodiment of the present invention having a plurality of memory cell arrays, and FIG. 20 is a diagram illustrating an example of output of hard data and soft data in FIG. 19. It is a figure which shows the example of the read retry table which concerns on embodiment of this invention.
22 is a view for explaining a failure of a read retry according to an embodiment of the present invention.
23 and 24 illustrate an ECC decoding method according to an embodiment of the present invention.
25 is a diagram illustrating an example of a wear table according to an embodiment of the present invention.
FIG. 26 is a view for explaining a method of updating a wear table of FIG. 25.
FIG. 27 is a diagram illustrating another example of the read retry table of FIG. 21.
28 is a block diagram illustrating a computing system device in accordance with an embodiment of the present invention.
29 is a block diagram illustrating a memory card according to an embodiment of the present invention.
FIG. 30 illustrates a solid state drive (SSD) according to an embodiment of the present invention.
31 is a diagram illustrating a server system and a network system including an SSD.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art, and the following embodiments may be modified in various other forms, The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an," and "the" include plural forms unless the context clearly dictates otherwise. Also, " comprise " and / or " comprising " when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups. As used herein, the term " and / or " includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various elements, regions and / or regions, it should be understood that these elements, components, regions, layers and / Do. These terms are not intended to be in any particular order, up or down, or top-down, and are used only to distinguish one member, region or region from another member, region or region. Thus, the first member, region or region described below may refer to a second member, region or region without departing from the teachings of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing embodiments of the present invention. In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions illustrated herein, including, for example, variations in shape resulting from manufacturing.

1 is a flowchart illustrating a read method for a flash memory according to an embodiment of the present invention, and FIG. 2 is a block diagram illustrating a flash memory according to an embodiment of the present invention.

1 and 2, in the read method according to the embodiment of the present invention, the read method for the flash memory according to the embodiment of the present invention may include a first target page TPGA1 at a first hard read voltage HRV. The first hard read voltage HRV and the voltage may be sensed during the step S120 of sensing the hard data HD for the second data) and the first operation on the hard data HD sensed by the flash memory MEM. In operation S140, the soft data SD of the first target page TPGA1 is generated using at least one pair of soft read voltages SRV having different levels. The first operation may be an operation of outputting the sensed hard data HD from the flash memory MEM. Alternatively, the first operation may be an operation of backing up the sensed hard data stored in one of the plurality of latches of the buffer unit of the flash memory MEM to another latch of the buffer unit. A detailed description thereof will be described later.

The flash memory MEM according to the embodiment of the present invention may be a NAND flash memory. In addition, memory cells (not shown) of the flash memory MEM according to the exemplary embodiment of the present invention may be programmed with at least one or more bits. Various examples thereof are described in FIG. 4 described below.

The flash memory MEM includes a memory cell array MA including a first target page TPGA1 and a buffer unit BFU including a plurality of latches LAT1 to LATn. can do. The plurality of latches LAT1 to LATn may be referred to as a plurality of page buffers or a plurality of data registers. The flash memory MEM according to an embodiment of the present invention includes a plurality of latches LAT1 to LATn, while an arbitrary operation on the hard data HD sensed by the flash memory MEM is performed. Generation of the soft data SD for the first target page TPGA1 may be performed at the same time. A detailed description thereof will be described later.

The flash memory MEM according to the embodiment of the present invention may further include a read unit RU. The flash memory MEM may further include a control logic (not shown), an input / output unit (not shown), a power generation unit (not shown), etc., but a description thereof will be omitted.

The read unit RU of FIG. 2 may be a component in which a function of a read among control logic, an input / output unit, and a power generation unit that may be included in the flash memory MEM is conceptually combined. For example, the function of receiving the read command CMD_RD from the outside of the flash memory MEM among the input / output units and the function of outputting the read result RST_RD corresponding to the read command CMD_RD to the outside is the read unit RU. Can be included. The read command CMD_RD may be transmitted from the memory controller Ctrl of FIG. 26 and the like, and the read result RST_RD may be transmitted to the memory controller Ctrl.

The read unit RU outputs the read result RST_RD of the first target page TPAG1 sensed by the buffer unit BFU from the memory cell array MA in response to the read command CMD_RD. In detail, the read unit RU applies the read voltage RV corresponding to the read command CMD_RD to the first target page TPAG1 corresponding to the address Addr of the read command CMD_RD. The address Addr and the read voltage RV included in the read command CMD_RD may be set by the memory controller Ctrl described later.

The voltage level of the read voltage RV applied to the first target page TPAG1 or the second target page TPAG2 may be set based on various read situations. For example, during initial read, the read voltage RV may be set to the initial read voltage. When the read error is checked in the initial read, read retry may be performed. In this case, the read voltage RV may be set to a read retry voltage adjusted from the initial read voltage. In addition, when a page of a single-level cell (SLC) flash memory as shown in FIG. 4A is read, the read voltage RV is distributed and the program state P corresponding to the erased state E. FIG. Can be set to the voltage RV0 between the distributions of Alternatively, when the LSB (Least Significant Bit) is read from the 2-bit multi-level cell flash memory as shown in FIG. 4B, the read voltage RV corresponds to the first program state P. FIG. The voltage RV1 between the dispersion and the dispersion corresponding to the second program state P2 may be set.

2, as described above, the read unit RU may transmit a read result RST_RD for the first target page TPAG1 to, for example, the memory controller Ctrl. The read result RST_RD of the first target page TPAG1 includes hard data HD and soft data SD. Furthermore, in the case of a multi-level cell flash memory, state information Inf_ST in which each page is programmed may be included. A more detailed description of the state information Inf_ST will be described later.

The first target page TPAG1 may include memory cells connected to a word line of the memory cell array MA. In order to more clearly describe the first target page TPAG1 and the reading method according to the embodiment of the present invention, first, the structure and operation of the flash memory according to the embodiment of the present invention will be described.

The memory cell array MA of the flash memory MEM according to the exemplary embodiment of the present invention may be provided with the structure shown in FIG. 3A. The memory cell array MA includes a (a is an integer of 2 or more) blocks BLK0 to BLKa-1, and each of the blocks BLK0 to BLKa-1 is b And the pages PAG0 to PAGb-1 may include c (c is an integer of 2 or more) sectors (SEC0 to SECc-1). In FIG. 3A, the pages PAG0 to PAGb-1 and the sectors SEC0 to SECC-1 are shown for the block BLK0 only for convenience of illustration, but the other blocks BLK1 to BLKa-1 also block BLK0. It may have the same structure as.

When the memory cell array MA according to the embodiment of the present invention is a memory cell array of a NAND flash memory, the blocks BLK0 to BLKa-1 of FIG. 3A may be the same as the example of FIG. 3B. It may be provided. Referring to FIG. 3B, each of the blocks BLK0 to BLKa-1 has a number of d (d is an integer of 2 or more) in which eight memory cells MCEL are connected in series in the bit lines BLO to BLD-1. It may be provided as a string (STR). Each string STR may also include a drain select transistor Str1 and a source select transistor Str2 which are connected to both ends of memory cells MCEL connected in series.

The NAND flash memory having the structure as shown in FIG. 3B is erased in block units, and performs a program in units of pages PAG corresponding to each word line WL0 to WL7. The page PAG of FIG. 3B may be a first target page TPAG1.

3B shows an example in which eight pages PAG for eight word lines WL0 to WL7 are provided in one block. However, the blocks BLK0 to BLKa-1 of the memory cell array MA according to the embodiment of the present invention may have a different number of memory cells than the number of memory cells MCEL and pages PAG shown in FIG. It may be provided with a page. For example, the blocks BLK0 to BLKa-1 of the memory cell array MA according to the embodiment of the present invention may include 64 word lines. In addition, the flash memory MEM of FIG. 2 may include a plurality of memory cell arrays that perform the same operation in the same structure as the memory cell array MA described above.

Referring to FIG. 3C, a memory cell array MA according to an embodiment of the present invention may include only a single-level cell (SLC) region in which memory cells are programmed to represent one bit, or may represent a plurality of bits. Only the MLC area may be programmed. The memory cells of the MLC region may be programmed to represent the same number of bits, or may be programmed to represent different numbers of bits. For example, memory cells in the MLC region may be programmed to represent one of two and three bits.

Alternatively, the memory cell array MA may include an SLC region and an MLC region. In this case, the SLC region and the MLC region may be physically divided or logically divided by the read command CMD_RD.

Each of the memory cells may have a threshold voltage Vth included in one of the distributions shown in FIG. 4 according to the number of programmed bits. FIG. 4A shows a cell distribution in a SLC (Single-Level Cell) flash memory in which memory cells MCEL are programmed to represent one bit each, and FIG. 4B shows two bits each for memory cells MCEL. Cell scatter in a 2-bit multi-level cell (MLC) flash memory that is programmed to be able to be programmed. Indicates.

In detail, each of the memory cells MCEL in the SLC region has a threshold voltage included in one of an erased state E and a program state P of FIG. 4A, according to a value of programmed data. Alternatively, each of the memory cells MCEL of the 2-bit MLC region, in which the memory cells may each represent two bits, has an erased state E and a first program state P1 to a third program state (Fig. 4B). Has a threshold voltage included in one of the states of P3). Alternatively, each of the memory cells MCEL of the 3-bit MLC region, in which the memory cells may each represent two bits, has an erased state E and a first program state P1 to a seventh program state (Fig. 4C). Has a threshold voltage included in one of the states of P7).

However, the present invention is not limited thereto, and each of the memory cells MCEL of the memory cell array MA of FIG. 3B may be programmed with 4 bits or more, although not shown in FIG. 4. In addition, the flash memory MEM according to the embodiment of the present invention may include memory cells MCEL programmed with different numbers of bits.

The MLC area may include pages having different program states. For example, as shown in FIG. 4D, the 2-bit MLC region may include a least-significant bit (LSB) page programmed up to a lower bit and a most-significant bit (MSB) page programmed up to an upper bit. Alternatively, the 3-bit MLC region may include a LSB page, an MSB page, and a Central Significant Bit (CSB) page programmed up to an intermediate bit as shown in FIG. 4E.

Referring back to FIG. 2, a read error may be included in the read result RST_RD. The presence or absence of a read error may be checked and corrected by the ECC engine of the controller Ctrl. The read error may occur when the distribution of each memory cell is distorted as shown in FIG. 5 due to a change in the read environment of the flash memory MEM. For example, a value of a bit or data programmed into a memory cell having a threshold voltage Vth of an overlapped region between adjacent dispersions of FIG. 5 may be misidentified. For example, in the example in which the dispersion of the cell is shifted as shown in FIGS. 5A to 5C, when the lead voltages RV0 to RV7 set for the dispersion of FIGS. 4A to 4C are read, FIG. The hatched portion of 5 (a) or 5 (c) may cause a read error to be read with data different from the programmed data. The change in the read environment may be caused by the retention characteristics of the flash memory or the read disturb phenomenon.

Hereinafter, in the flash memory MEM according to the embodiment of the present invention, a soft decision on the first target page TPGA1 using existing instructions of the flash memory without having any separate hardware logic is performed. The method of correcting read errors by performing a decision will be described in more detail. First, the reading method for the first target page TPGA1 included in the SLC region will be described, and then the reading method for the first target page TPGA1 included in the MLC region will be described.

FIG. 6 is a diagram illustrating an example of a reading method of FIG. 1 with respect to a first target page included in an SLC region.

Referring to FIG. 6, each of the memory cells included in the first target page TPGA1 may be programmed with a single bit. In this case, the first target page TPGA1 may sense the hard data HD with the first hard read voltage RV0. The voltage level of the pair of soft read voltages RV0a and RV0b may be set by changing the voltage level of the first hard read voltage RV0 twice.

The voltage levels of the soft read voltages RV0a and RV0b may be set in a ready state with respect to the memory cell array MA of the flash memory MEM. A ready state (for example, the logic level of the Array RnB signal is logic high) of the memory cell array MA is a state in which reads, programs, and the like of the memory cell array MA are not performed. In the read operation for the first target page of the MLC region, which will be described later, the voltage level of the soft read voltage may be performed in the ready state for the memory cell array MA, and thus redundant description thereof will be omitted.

7 and 8 are diagrams showing an example of a method of generating soft data.

6 through 8, in operation S140a of generating the soft data SD for the first target page TPGA1 included in the SLC region, the pair of soft reads of the first target page TPGA1 may be performed. Transmitting the first soft value SV1 sensed by one of the voltages RV0a and RV0b to the first latch LATa (S720) and the first target page TPGA1 by a pair of soft read voltages. And cooking (S740) the second soft value SV2 sensed by the other one of the (RV0a and RV0b) and the first soft value SV1 of the first latch. . The first latch LATa may be one of the latches LAT1 to LATn of FIG. 2.

As illustrated in FIG. 8, a memory cell having a threshold voltage smaller than one soft read voltage RV0a is sensed as 1 and a memory cell having a large threshold voltage is sensed as 0 to become a first soft value SV1. Similarly, the memory cell having the threshold voltage smaller than the other soft read voltage RV0b is sensed as 1 and the memory cell having the large threshold voltage is sensed as 0 to become the second soft value SV2.

The soft data SD may be generated by cooking the first soft value SV1 and the second soft value SV2. Cooking may be performed by bitwise operation on the first soft value and the second soft value. In the example of FIG. 8, the first soft value SV1 and the second soft value SV2 are XNOR-operated to generate soft data SD.

Cooking of the first soft value SV1 and the second soft value SV2 may be performed using a test mode command of the flash memory MEM. In the read operation for the first target page of the MLC region, which will be described later, the cooking may be performed using the test mode command, and thus redundant description will be omitted.

In the above manner, hard data and soft data for the first target page of the SLC region are sensed or generated. However, description of the output of the sensed hard data and the generated soft data has been omitted, which may be identical to the method described in the first target page of the MLC region, which will be described later.

Hereinafter, a reading method for the first target page of the MLC area will be described.

FIG. 9 is a diagram illustrating an example of a read method for a case in which a first target page of an MLC region is an LSB page of FIG. 4D or 4E.

Referring to FIG. 9, the first target page TPGA1 is an LSB page in which a lower bit is programmed. In this case, the hard data HD and the soft data SD are the same as in the case of FIG. 6 described above. However, as shown in FIG. 9, the first hard read voltage RV1 is a read voltage in which the LSB of FIG. 4B or 4C can be identified.

The soft read voltage of the first target page of the MLC region may correspond to a voltage level of the second hard read voltage of the second target page programmed by a number different from the number of bits programmed in each of the memory cells of the first target page. Can be set by changing. In the example of FIG. 9, the second target page may be the MSB page of FIG. 4D or 4E, or the CSB page of FIG. 4E. The second hard read voltage may be read voltages RV2 and RV3 in which the MSB of FIG. 4B or the CSB of FIG. 4C can be identified. The pair of soft read voltages RV2a and RV3a in FIG. 9 are set by changing the voltage levels of the second hard read voltages RV2 and RV3 of the second target page (MSB page or CSB page).

In the above, the second target page has been described as a page in which higher bits (a larger number of bits) are programmed than the first target page, but is not limited thereto. In addition, the soft read voltage may be set by changing the voltage level of one second hard read voltage twice for the second target page instead of a pair.

However, referring to FIG. 10, in generating soft data for the first target page which is the LSB page, the soft read voltage is changed by changing the voltage level of the second hard read voltage of the second target page as in the example of FIG. 9. When generating, detecting the state information Inf_ST of FIG. 2 representing the program state of the first target page from the sensed hard data (S1020) and the state information Inf_ST corresponding to the read mode for the second target page. The step S1040 may be added to change it.

FIG. 11 is a diagram illustrating an example of a method of detecting state information indicating a program state of a first target page from the sensed hard data of FIG. 10.

Referring to FIG. 11, the state information Inf_ST of FIG. 2 may be detected according to the type and value of a flag cell. For example, in performing a read on the first target page TPGA1 of the 2-bit MLC region, as illustrated in FIG. 11A, a flag cell FC having a value of 1 is detected from the sensed hard data. If so, the first target page TPAG1 may be identified as being an LSB page. On the contrary, as shown in FIG. 21B, if the flag cell FC having a value of 0 is detected from the sensed hard data, the first target page TPAG1 may be identified as being an MSB page. The flag cell FC may be provided in plurality in the first target page TPGA1.

However, detection of the state information Inf_ST is not limited to the case of using a flag cell. For example, detection of the state information Inf_ST may be detected by counting any program state of the first target page TPGA1. For example, in detecting state information on the program state of the first target page TPGA1 of the 3-bit MLC region, the number of the seventh program states P7 of FIG. 4C included in the first target page TPGA1. Can be counted. If the number of the seventh program states P7 included in the first target page TPGA1 is close to zero, it can be seen that the first target page TPGA1 is not an MSB page.

The detected state information Inf_ST may be stored in any register (not shown). The flash memory MEM according to an exemplary embodiment of the present invention may be changed using a test mode command. For example, by changing the state information Inf_ST indicating that the first target page TPGA1 is an LSB page, the control may recognize that the first target page TPGA1 is an MSB page. Therefore, the second hard read voltage of the second target page may be used for the first target page TPGA1.

Steps S1020 and S1040 of FIG. 10 described above may be performed after the hard data is sensed and before setting the soft read voltage. Steps S1020 and S1040 of FIG. 10 may be equally applied to the case where the first target page to be described later is an MSB page, and thus redundant description will be omitted.

12 is a diagram illustrating an example of a read method when the first target page is programmed with higher bits of a multi-bit.

Referring to FIG. 12, for example, the first target page TPGA1 may be a page in which a most significant bit for two bits of program data is programmed. In this case, the first hard read voltage may be set to two or more different voltage levels corresponding to the number of multi-bits. 12 illustrates an example in which the first target page TPGA1 is an MSB page for a 2-bit MLC, so that the first hard read voltages RV2 and RV3 of two different voltage levels are set. 12 shows an example in which the soft read voltages RV2a and RV3a, RV2 \ b and RV3b are set by changing the voltage levels of the first hard read voltages RV2 and RV3 twice. However, in the read method when the first target page is programmed with higher bits of the multi-bit, the soft read voltage may be set to one of the various embodiments described above.

In the method of generating the soft data SD of FIG. 12, the memory cell is sensed as 1 or 0 as the voltage level of the soft read voltage and the threshold voltage of the memory cell are larger and smaller as in FIGS. 6 to 8. The first soft value SV1 and the second soft value SV2 are formed. 6 to 8, the soft data SD is generated by bit operation of one first soft value SV1 and the second soft value SV2, respectively. The soft data SD of FIG. The soft value SV1 and the second soft value SV2 are generated using the third soft values SV3 obtained by bitwise computing the second soft value SV2. This will be described.

FIG. 13 is a flowchart illustrating a method of generating soft data for the first target page of FIG. 12, and FIG. 14 is a diagram illustrating an operation of generating soft data according to the method of FIG. 13.

12 to 14C, a method (S140b) of generating soft data for a first target page TPGA1 in which multi-bit higher bits (eg, MSB of 2-bit MLC) is programmed may be performed. Generating a third soft value SV3-1 for the first voltage level RV2 of the hard read voltages RV2 and RV3 (S1320), and the first voltage level of the first hard read voltages RV2 and RV3. Generating a third soft value SV3-2 for (RV3) (S1340) and a third soft value SV3-1 for the first voltage level (RV2) of the first hard read voltages (RV2, RV3). ) And cooking the third soft value SV3-2 with respect to the first voltage level RV3 of the first hard read voltages RV2 and RV3 (S1360).

For example, generating the third soft value SV3-1 for the first voltage level RV2 of the first hard read voltages RV2 and RV3 (S1320) may be performed by the process of FIG. 14A. . In detail, the first target page TPGA1 is sensed by one of the first pair of soft read voltages RV2a and RV3a with respect to the first voltage level RV2 of the first hard read voltages RV2 and RV3. The first soft value SV1-1 is transmitted to the first latch LATa (S1322), and the other one RV3a of the first pair of soft read voltages RV2a and RV3a is applied to the first target page TPGA1. The first pair of the first soft value SV1-1 of the second soft value SV2-1 and the first latch LATa is cooked by sensing the second soft value SV2-1 with respect to the second soft value SV2-1. And transmitting the third soft value SV3-1 by the soft read voltages RV2a and RV3a to the second latch LATb (S3126).

Each of the first latch LATa and the second latch LATb may be one of the latches of FIG. 2. At this time, there is no limitation on the physical position of the first latch LATa and the second latch LATb in the plurality of latches of FIG. 2. The same is applied hereinafter.

In operation S1340, the third soft value SV3-2 for the second voltage level RV3 of the first hard read voltages RV2 and RV3 may be generated by the process of FIG. 14B. Specifically, the first target page TPGA1 is sensed by one of the second pair of soft read voltages RV2b and RV3b with respect to the second voltage level RV3 of the first hard read voltages RV2 and RV3. The first soft value SV1-2 is transferred to the first latch LATa (S1342), and the other one of the third pair of soft read voltages RV2b and RV3b is transferred to the first target page TPGA1. A second pair of the second soft value SV2-2 sensed (S1344) to cook the second soft value SV2-b and the first soft value SV1-2 of the first latch LATa. The third soft value SV3-2 of the soft read voltages RV2b and RV3b may be transmitted to the second latch LATb (S3146).

The third soft values SV3-1 and SV3-2 generated by the above process are bit-operated, as shown in FIG. 14C. At this time, in step S1360, when the third soft value SV3-2 of step S1346 is transmitted to the second latch LATb, the third soft value SV3-1 stored in the second latch LATb by step S1326. Bit operations may be performed on. The bit operations of FIGS. 14A to 14C may be XNOR operations as described above with reference to FIGS. 6 and 8.

Referring to FIG. 14D, the result of bitwise operation of the three soft values SV3-1 and SV3-2 in operation S1360 is stored in the second latch LATb.

In the above, the case where the 1st target page TPGA1 is an MSB page of 2-bit MLC was demonstrated. However, the present invention is not limited thereto. As described above, the first target page TPGA1 may be an MSB page or CSB page of MLC of 3 bits or more. In this case, the first hard read voltages for the first target page TPGA1 may be generated at various voltage levels than in the case of FIG. 12.

15 shows an example in which the first target page TPGA1 is an MSB page of a 3 bit MLC. For convenience of illustration, only the first hard read voltage HRV of four voltage levels of the first target page TPGA1 and the soft data SD corresponding to each first hard read voltage HRV are illustrated in FIG. 15. do.

15 and 16, a read method according to an exemplary embodiment of the present invention sequentially sequentially applies a third soft value for all of the plurality of voltage levels of the first hard read voltages RV4, RV5, RV6, and RV7. Obtaining SV3-1, SV3-2, SV3-3, SV3-4, and changing the third soft value of the second latch LATb (LATb-1-> LATb-2-> LATb-3) In operation S1640, the method may further include outputting the third soft value LATb-3 of the second latch LATb as the soft data SD (S1640). In this case, a method of obtaining the third soft values SV3-1, SV3-2, SV3-3, and SV3-4 for each of the first hard read voltages RV4, RV5, RV6, and RV7 may be obtained from FIGS. 12 to 14D. May be as described.

17A and 17B illustrate an example of outputting soft data in a read method for a flash memory according to an embodiment of the present invention.

17A and 17B, after sensing the hard data HD for the first target page of the memory cell array HD sen, the sensed hard data HD is stored in the backup latch LATr from the backup latch LATr. During back-up (HD bu) to the LATbu, the soft data SD for the first target page of the memory cell array may be sensed. However, before the hard data HD is sensed (HD sen) and before the soft data SD is sensed (SD sen), the above-described level change of the soft read voltage, detection and change of state information Inf_ST, and the like may be performed. Can be performed.

However, the present invention is not limited thereto, and the hard data HD may be output to the outside of the flash memory MEM during sensing of the soft data SD. As described above, a cache read may be referred to as a read method for simultaneously sensing soft data while the flash memory performs a different operation on the sensed hard data.

The soft data SD of FIG. 17A may be output from the output latch LATo at time t = i. Referring to FIG. 18, the backed up hard data HD may be output from the output latch LATo at t = i + 1 subsequent to the soft data SD.

However, the present invention is not limited thereto. Unlike FIGS. 17A and 18, the hard data HD may be output first, and then the soft data SD may be output. In addition, the physical positions of the reception latch LATr, the backup latch LATbu, and the output latch LATo are not limited to the examples of FIGS. 17A, 17B, and 18. The reception latch LATr, the backup latch LATbu, and the output latch LATo may be one of the plurality of latches LAT1 to LATn of FIG. 2, respectively.

FIG. 19 is a diagram illustrating a flash memory according to an exemplary embodiment of the present invention having a plurality of memory cell arrays, and FIG. 20 is a diagram illustrating an example of output of hard data and soft data in FIG. 19.

19 and 20, the flash memory MEM may include a plurality of memory cell arrays MA1 to MAm and buffer units BUF1 to BUFm. In this case, each of the memory cell arrays MA1 to MAm includes the first target page TPGA1 described above, and the hard data HD1 to the first target page TPGA1 according to the above-described various embodiments of the present disclosure. HDm) sensing and soft data SD1 to SDm may be generated.

The hard data HD1 to HDm and the soft data SD1 to SDm sensed or generated in each of the memory cell arrays MA1 to MAm may be continuously output as shown in FIGS. 17A and 18. In particular, as shown in FIG. 20, the hard data HD and the soft data SD may be sequentially output to the plurality of memory cell arrays MA1 to MAm. For example, after the hard data HD1 and the soft data SD1 for the first memory cell array MA1 are output, the hard data HD2 and the soft data SD2 for the second memory cell array MA2 are output. ) May be output (b direction). Or after the hard data HD2 and the soft data SD2 for the second memory cell array MA2 are output, the hard data HD1 and the soft data SD1 for the first memory cell array MA1 are output. As such, as the hard data HD1 to HDm and the soft data SD1 to SDm are sequentially output for the plurality of memory cell arrays MA1 to MAm, the memory controller that receives the data is configured to all the memory cell arrays. It is not necessary to have a buffer for hard data and soft data, and by only providing a buffer for hard data and soft data for one memory cell array, the size of the memory controller may be reduced. However, the present invention is not limited thereto.

As described above, the read method in the flash memory according to the embodiment of the present invention utilizes a preset command (lead command, test mode command, etc.) even if the logic of the soft decision is not provided. Can be done. In addition, the read method of the flash memory according to the embodiment of the present invention, by using the cache read (cache read) method as described in Figure 17b can be performed by sensing the soft read voltage to prevent the overhead. Further, as described with reference to FIG. 20 and the like, by improving the output scheme of the hard data and the soft data, the read method in the flash memory according to the embodiment of the present invention can determine the size of the memory controller (the number of buffers required for the memory controller). Can be reduced.

The hard data and soft data sensed or generated from the flash memory and output in the above manner may be combined by the memory controller to correct a read error. However, the generation of the soft data may be performed when a read error for the first target page occurs. Alternatively, the read error may be performed when the read error for the first target page is not corrected by a method described below.

21 is a diagram illustrating an example of a read retry table according to an embodiment of the present invention.

Referring to FIG. 21, the read retry table RTAB includes read levels for each index. In addition, each index of the read retry table RTAB may include a plurality of read levels. FIG. 21 illustrates an example of including three read levels REVL1, REVL2, and REVL3 in each index. . For example, index 0 of the read retry table RTAB of FIG. 21 includes read levels REVL1, REVL2, and REVL3 of values of RV11, RV12, and RV13, respectively, and index 1 corresponds to RV21, RV22, respectively. And read levels REVL1, REVL2, and REVL3 of the value of RV23. This is because MLC flash memory requires multiple read levels to read the MLC. For example, three different read level values are required to distinguish four states (cell distribution) as shown in FIG. 4B.

The flash memory according to the embodiment of the present invention performs a read retry operation by sequentially changing the read level from the read level of one index to the read level of the next index until the read error is corrected. For example, when a read retry is performed with the read levels RV11, RV12, and RV13 of the index 0 of the read retry table RTAB, but the error is not corrected, the read level RV21 of the index 1 of the read retry table RTAB, Read retry may be performed again to RV22 and RV23. If the error is not corrected yet, the read retry is performed again to the read levels RV31, RV32 and RV33 of the index 2 of the read retry table RTAB.

Referring to FIG. 22, when the first initial read voltage for identifying the first cell spread E and the second cell spread P among the initial read voltage RV0 is RV01, the first cell spread S1 and the first The error of the identification (lead) between the two cell distributions S2 is, in the above example, the first lead level RV11 of index 0 of the read retry table RTAB and the index 1 of the read retry table RTAB. An error still exists when the read retry is made by the first read level RV21. By the way, in the example of FIG. 22, an error that is not corrected also by the read levels RVn1, RVn2 and RVn3 of the last index n of the read retry table RTAB is not corrected. In this case, the soft data described above can be generated.

In the soft decision method according to the embodiment of the present invention, as shown in FIGS. 23A and 23B, read levels included in the first index among the indices of the read retry table for the first target page. After the first target page reads the first target page is transferred to the second latch LAT2 through the first latch LAT1 among the latches, the read included in the second index among the indices of the read retry table for the first target page. While transferring the first target page read at the level to the first latch LAT1, as illustrated in FIG. 23C, the first ECC for the second target page transmitted to the second latch LAT2. Decoding (Error Check and Correction Decoding) may be performed by an ECC engine (ECCE) that may be included in the memory controller.

Simultaneously with the first ECC decoding, the first target page of the first latch LAT1 is transferred to the second latch LAT2, and the second ECC for the second target page TPAG2 transmitted to the second latch LAT2. Decoding may be performed by the ECC engine (ECCE).

The ECC engine (ECCE) compares the number of ECC sectors corrected in the first target page by the first ECC decoding and the number of ECC sectors corrected in the first target page by the second ECC decoding, as in the example of FIG. 24. Can be. 24 shows an example in which two ECC sectors are corrected by the read level of the first index, and four ECC sectors are corrected by the read level of the second index. In addition, an example is shown in which five ECC sectors are corrected by the read level of the third index, and two ECC sectors are corrected by the fourth index.

In the case of the example of FIG. 24, the first read voltage performing the hard decision according to the embodiment of the present invention may be set to the read level of the third index. In this case, as the soft decision is performed by the more accurate hard read voltage, read error correction efficiency may be increased.

The reed retry table according to the embodiment of the present invention may be selected by the wear table WTAB of FIG. 25. The wear level table WTAB of FIG. 25 includes information WO regarding the wear level of each block, with each block of the flash memory MEM as an index. In this case, the information WO of the wear degree of each block may be based on the second state information Inf_ST2 detected in the flash memory MEM in response to the first command CMD1 transmitted from the memory controller Ctrl. have. In the example of FIG. 26, the first command CMD1 is an erase command, and the second state information Inf_ST erases each of the blocks of the NAND flash memory in response to the erase command. It may be an incremental step pulse erase loop count value.

The wear level table WTAB of FIG. 25 may further include, for each block, information Ind about the read level in which the read error was recently corrected by the read retry. Accordingly, when there is a read retry request for a specific block, the retry retry may be performed from a read level in which a read error has recently been corrected by the read retry. Therefore, according to the read method according to the exemplary embodiment of the present invention, the number of repetitions of the read retry may be significantly reduced, thereby reducing waste of resources and time required for the read retry.

In addition, the read retry table RTAB according to an embodiment of the present invention may be selected from among a plurality of read retry tables as shown in FIG. 27 based on the wear information on the wear table WTAB. That is, the read method and the memory system according to the embodiment of the present invention may separately include a read retry table for each endurance state of the flash memory MEM. The endurance of the flash memory can be represented by a P / E cycle (Program / Erase Cycle). For example, the first read retry table RTABA of FIG. 27 is a read retry table when the P / E cycle is less than 1K, and the second read retry table RTABB is P. The read retry table for the case where the / E cycle is 1K or more and less than 2K, and the third read retry table (RTABC) may be the read retry table for the case where the P / E cycle is 2K or more and less than 3K. However, the present invention is not limited thereto, and the read retry tables according to the exemplary embodiment of the present invention may be set for different P / E cycles.

28 is a block diagram illustrating a computing system device in accordance with an embodiment of the present invention.

The computing system CSYS according to an embodiment of the present invention includes a processor (CPU), a user interface (UI), and a flash memory system (MSYS) electrically connected to a bus (BUS). The flash memory system MSYS includes a memory controller Ctrl and a flash memory MEM. In the flash memory MEM, N-bit data (N is an integer of 1 or larger) to be processed or to be processed by the processor CPU will be stored through the memory controller Ctrl. The flash memory MEM of FIG. 28 may be the same as the flash memory MEM of FIG. 2. Therefore, according to the computing system CSYS, even in a flash memory that does not support the soft decision, the soft decision is efficiently performed by using a command set for the flash memory, thereby saving the flash memory MEM and saving the flash memory. The reliability of the read of the memory MEM can be improved.

The computing system CSYS according to an embodiment of the present invention may further include a power supply device PS. In addition, the computing system CSYS according to an embodiment of the present invention may further include a volatile memory device (eg, RAM).

When the computing system CSYS according to the embodiment of the present invention is a mobile device, a modem such as a battery and a baseband chipset for supplying an operating voltage of the computing system may be additionally provided. In addition, it is common knowledge in the art that an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further provided in the computing system CSYS according to the embodiment of the present invention. This is obvious to those who have learned, so a detailed description is omitted.

29 is a block diagram illustrating a memory card according to an embodiment of the present invention.

Referring to FIG. 29, a memory card MCRD according to an embodiment of the present invention includes a memory controller Ctrl and a flash memory MEM. The memory controller Ctrl controls data writing to or reading data from the flash memory MEM in response to a request from an external host (not shown) received through the input / output means I / O. . Also, the memory controller Ctrl controls the erase operation on the flash memory MEM. The memory controller Ctrl of the memory card MCRD according to an exemplary embodiment of the present invention may include interface units (not shown) and RAM (not shown) for performing an interface with a host and a memory device, respectively, in order to perform the above control operations. RAM) and the like. The flash memory MEM of the memory card MCRD according to the exemplary embodiment of the present invention may be implemented with the flash memory MEM of FIG. 2.

The memory card MCRD of FIG. 29 may include a compact flash card (CFC), a microdrive, a micro media (SMC), a multimedia card (MMC), and a secure digital card (SDC). It may be implemented as a security digital card, a memory stick, or a USB flash memory driver. Therefore, according to the memory card MCRD of FIG. 22, the soft decision is efficiently performed even in the NAND flash memory that does not support the soft decision, thereby saving the resources of the flash memory MEM and saving the flash memory MEM. The reliability of the lead can be improved.

30 is a view showing a solid state drive (SSD) according to an embodiment of the present invention.

Referring to FIG. 30, an SSD according to an embodiment of the present invention includes an SSD controller SCTL and a flash memory MEM. The SSD controller SCTL may include a processor PROS, a RAM, a cache buffer CBUF, and a memory controller Ctrl connected to a bus BUS. The processor PROS controls the memory controller Ctrl to exchange data with the flash memory MEM in response to a request (command, address, data) of the host (not shown). The processor PROS and the memory controller Ctrl of the SSD according to the embodiment of the present invention may be implemented as one ARM processor. Data necessary for the operation of the processor PROS may be loaded into the RAM. For example, the read retry table RTAB of FIG. 2 may be loaded into the RAM.

The host interface HOST I / F receives a request from the host and transmits the request to the processor PROS or transmits data transmitted from the flash memory MEM to the host. Host interfaces (HOST I / F) include Universal Serial Bus (USB), Man Machine Communication (MMC), Peripheral Component Interconnect-Express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Various interface protocols, such as Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), and Intelligent Drive Electronics (IDE), can interface with the host. Data to be transferred to the flash memory MEM or data transferred from the flash memory MEM may be temporarily stored in the cache buffer CBUF. The cache buffer CBUF may be an SRAM or the like.

The SSD according to the embodiment of the present invention may include the flash memory MEM of FIG. 2. Therefore, according to the SSD of FIG. 30, it is possible to reduce the resources required for the system while improving the reliability of the read.

31 is a diagram illustrating a server system and a network system including an SSD.

Referring to FIG. 31, a network system NSYS according to an embodiment of the present invention may include a server system SSYS and a plurality of terminals TEM1 to TEMn connected through a network. The server system SSYS according to an embodiment of the present invention responds to a request received from a server SERVER and terminals TEM1 to TEMn processing a request received from a plurality of terminals TEM1 to TEMn connected to a network. And an SSD for storing corresponding data. In this case, the SSD of FIG. 31 may be the SSD of FIG. 30. That is, the SSD of FIG. 31 may include an SSD controller SCTL and a flash memory MEM, and the flash memory MEM may be a flash memory that performs a read by the read method of FIG. 1.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms are employed herein, they are used for purposes of describing the present invention only and are not used to limit the scope of the present invention. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims

In a read method for a flash memory,
Sensing hard data for the first target page using the first hard read voltage; And
While the flash memory performs a first operation on the sensed hard data, soft data for the first target page is generated using at least one pair of soft read voltages having different voltage levels from the first hard read voltage. And a read method for a flash memory.

The method of claim 1, wherein the pair of first soft read voltages,
And setting the voltage level of the first hard read voltage twice.

The method of claim 1, wherein the pair of first soft read voltages,
And changing a voltage level of a second hard read voltage for a second target page programmed with a number of bits different from the first target page, respectively.

The method of claim 3, wherein the pair of first soft read voltages,
And changing the voltage levels of the pair of second hard read voltages with respect to the second target page, respectively.

The method of claim 3, wherein the pair of first soft read voltages,
And changing a voltage level of one second hard read voltage for the second target page twice.

The voltage level of the pair of soft read voltages is:
And the read method is set in a ready state for the array of flash memories.

The method of claim 3, wherein generating soft data for the first target page comprises:
Detecting state information indicating a program state of the first target page from the hard data; And
And changing the state information so as to correspond to a read mode for the second target page.

The method of claim 7, wherein the changing of the state information,
Read method for the flash memory, characterized in that performed using a test mode command (Test Mode Command) of the flash memory.

The method of claim 1, wherein the first target page,
A method for reading a flash memory, characterized in that the memory cells comprising pages are programmed with the least significant bit of a single bit or multi bit, respectively.

The method of claim 9, wherein generating soft data for the first target page comprises:
Transmitting a first soft value sensed by the first target page to one of the pair of soft read voltages to a first latch; And
And cooking the second soft value of sensing the first target page by another one of the pair of soft read voltages and the first soft value of the first latch. About the lead way.

The method of claim 10, wherein the cooking of the first soft value and the second soft value comprises:
And performing a bitwise operation on the first soft value and the second soft value.

The method of claim 10, wherein the cooking of the first soft value and the second soft value comprises:
Read method for the flash memory, characterized in that performed using a test mode command (Test Mode Command) of the flash memory.

The method according to claim 1,
The first target page is a page in which memory cells that are included are programmed with higher bits of a multi bit, and the first hard read voltage is set to two or more different voltage levels corresponding to the number of the multi bits. Read method for a flash memory, characterized in that.

The method of claim 13, wherein generating soft data for the first target page comprises:
The first soft value of the first target page sensed by one of the first pair of soft read voltages with respect to the first voltage level of the first hard read voltage is transmitted to the first latch, and the first pair of soft read voltages. A second soft value of sensing the first target page by another one of voltages and a third soft value of the first pair of soft read voltages of the first latch of the first latch, the second soft value being cooked. Transmitting;
And transmits a first soft value of sensing the first target page to the first latch as one of the soft read voltages of the second pair corresponding to the second voltage level of the first hard read voltage. Cooking a second soft value sensing the first target page with the other one of the soft read voltages and the first soft value of the first latch to obtain a third soft value by the second soft read voltages; ; And
Cooking a third soft value by the second pair of soft read voltages and a third soft value of the second latch to change the third soft value of the second latch. About the lead way.

15. The method of claim 14,
Obtaining the third soft value sequentially for all of the voltage levels of the first hard read voltage, and changing the third soft value of the second latch; And
And outputting the third soft value of the second latch as the soft data.

The method according to claim 1,
And the first operation is an operation for outputting the sensed hard data from the flash memory.

The method according to claim 1,
The first operation is a method of backing up the sensed hard data stored in one of a plurality of latches of a buffer unit of the flash memory to another latch of the buffer unit. .

The method of claim 17,
And successively outputting the backed up hard data and the soft data.

The method of claim 17,
The flash memory includes a plurality of memory cell arrays, each of the memory cell arrays including the first target page, and sensing of the hard data and generation of the soft data for each of the first target pages. A read method for a flash memory, characterized in that performed.

20. The method of claim 19,
Sequentially outputting the backed up hard data of the first target page of each of the memory cell arrays and the soft data of the first target page of each of the memory cell arrays sequentially to the memory cell array. Read method for a flash memory, characterized in that further comprising.

The method according to claim 1,
Generating the soft data,
And a read error of the first target page or a read error of the first target page is not corrected.

22. The method of claim 21,
Generating the soft data,
Performed when a read retry for correcting a read error of the first target page fails;
The read retry for the first target page is
With reference to a wear-out table that indexes each block of the flash memory,
A read level included in one of indexes of a corresponding read retry table among read retry tables provided differently for each endurance state interval of the flash memory. A read method for a flash memory, starting from the beginning to the last read level of the last index.

The wear and tear table of claim 22, wherein
A read for a flash memory having an incremental ISPE loop count value required to erase the blocks of the flash memory in response to an erase command. Way.

The flash memory of claim 1, wherein the flash memory comprises:
And a separate logic for generating the soft data is generated, and the soft data is generated using a command set in the flash memory.

A read method for a multi-level cell NAND flash memory, the method comprising:
Sensing hard data for the first target page using the first hard read voltage;
At least one pair of pages for the pages programmed with a greater number of bits than the first target page while the hard data is backed up from the first latch to the second latch among the plurality of latches included in the buffer unit of the flash memory. Sensing soft data by changing the voltage level of the second hard read voltage, and storing the soft data in a third latch; And
And successively outputting the soft data and the backed up hard data.

The solid state drive of claim 1, wherein the read operation is performed on the flash memory.