KR20130030099A

KR20130030099A - Flash memory device and reading method of flash memory device

Info

Publication number: KR20130030099A
Application number: KR1020110093641A
Authority: KR
Inventors: 은희석; 김재홍
Original assignee: 삼성전자주식회사
Priority date: 2011-09-16
Filing date: 2011-09-16
Publication date: 2013-03-26

Abstract

PURPOSE: A flash memory system and a reading method thereof are provided to improve the reliability of a reading operation by performing soft decision. CONSTITUTION: A first read command for a first bit page is transmitted from a controller to a flash memory to generate hard data of the first bit page which programs each first bit of program data(S220). A second read command for a second bit page is transmitted from the controller to the flash memory to generate the first soft data of the first bit page with a first soft read voltage to change a voltage level of a second read voltage for a second bit page which programs each second bit of the program data(S240). [Reference numerals] (S220) Transmitting a first read command from a controller to a flash memory to generate hard data for a first bit page by the flash memory; (S240) Transmitting a second read command of changing a voltage level of a second read voltage into a first soft read voltage from the controller to the flash memory to generate a first soft data for the first bit page by the flash memory

Description

Flash memory device and reading method of flash memory device

The present invention relates to a flash memory system and a read method in a flash memory system, and more particularly, to a flash memory system and a read method in a flash memory system that can improve the reliability of the read.

Flash memory systems are scaled down according to the demand for high integration, and the number of bits stored in each memory cell is increasing. Thus, read margins between program states are decreasing. In order to overcome this and improve the reliability of the flash memory system, methods for accurately performing reads between adjacent program states have been discussed.

An object of the present invention is to provide a flash memory system and a read method in a flash memory system that can improve read reliability.

A flash memory system according to an embodiment of the present invention includes a flash memory including a memory cell programmed with at least two bits of program data, and a controller for controlling the flash memory, wherein the reading method in the flash memory system includes: A first for the first bit page from the controller to the flash memory such that hard data of the first bit page is generated with a first read voltage for the first bit page that programmed the first bit of each of the program data. Transmitting a read command; And generating first soft data of the first bit page using a first soft read voltage having a voltage level of a second read voltage for a second bit page programmed with a second bit of each of the program data. And transmitting a second read command for a second bit page from the controller to the flash memory.

The method may further include determining, according to the first soft data, how much the bit value of the first bit of each of the program data is equal to the bit value of the corresponding bit of the hard data.

The first bit and the second bit may be adjacent bits of the program data or may be spaced apart bits.

The first read command may be a read command for reading an LSB page for each LSB of the program data, and the second read command may be a read command for reading an MSB page for each MSB of the program data. have.

The flash memory system may be a 2-bit multi-level cell flash memory system in which the program data is 2 bits or a 3-bit multi-level cell flash memory system in which the program data is 3 bits.

The first read command is a read command for reading an LSB page for each LSB of the program data, and the second read command is a read command for reading a CSB page for each CSB of the program data, The first read command may be a command to read a CSB page for a CSB of each of the program data, and the second read command may be a command to read an MSB page for an MSB of each of the program data.

Retransmitting the second read command to the flash memory such that the second soft data of the first bit page is generated with a second soft read voltage which has changed the voltage level of the second read voltage again. Can be.

The method may further include determining, according to the second soft data, how much the bit value of the first bit of each of the program data is equal to the bit value of the bit of the corresponding hard data.

The second soft data of the first bit page is generated with a second soft read voltage having a voltage level of a third read voltage for a third bit page programmed with a third bit of each of the program data. The method may further include transmitting a third read command for a 3 bit page from the controller to the flash memory.

The voltage level of the second soft read voltage is 2 m (m is a natural number) multiple of the first read voltage and may be symmetrical or asymmetrical with respect to the first read voltage.

The voltage level of the first soft read voltage is 2 n (n is a natural number) multiple of the first read voltage and may be symmetrical or asymmetrical with respect to the first read voltage.

The read method may be performed in response to a soft decision signal including at least one of channel information on a channel state between the controller and the flash memory and performance information on the performance of the flash memory system.

The method may further include detecting the channel information or the performance information.

The method may further include determining whether to generate second soft data generated by reading the first bit page with a second soft read voltage according to at least one of the channel information and the performance information.

When it is determined to generate the second soft data, the second soft data is generated by the second read command set to the second soft voltage having a different voltage level from the first soft read voltage, or the program data. The second soft data may be generated by a third read command set to the second soft read voltage of which the voltage level of the third read voltage for the third bit page in which each third bit is programmed is changed.

Transmitting the second read command from the controller to the flash memory such that hard data for the second bit page is generated at the second read voltage; And retransmitting the second read command from the controller to the flash memory such that the first soft data of the second bit page is generated with a second soft read voltage having changed the voltage level of the second read voltage. It can be provided.

To generate the first soft data of the second bit page, an erase state of the second bit page and i (i is 2 ^j -1 and j is a natural number) are read with the second read voltage. And the second soft read voltage can be read for all adjacent states.

To generate the first soft data of the second bit page, a second soft read for a portion of the erased state and the i program states of the second bit page that are read with the second read voltage and adjacent to each other; Can be read by voltage.

The method may further include determining read data by error correcting the hard data according to a result of determining the same degree of the hard data and the first soft data.

The flash memory may not generate the first soft data by the first read command.

According to another aspect of the present invention, there is provided a method of reading a flash memory system, the method comprising: generating LSB hard data by reading an LSB page using an LSB read command; Reading the LSB page with an MSB read command that changes a voltage level of an MSB read voltage to generate LSB soft data; Determining how much LSB data programmed in the LSB page is identical to the LSB hard data using the LSB soft data; And determining the read data of the LSB data by error correcting the LSB hard data according to a result of determining the same degree of the LSB data and the LSB hard data.

The generating of the LSB soft data may include transmitting the MSB read command from the controller of the flash memory device to the flash memory of the flash memory device.

The generating of the LSB soft data may include changing the voltage level of the MSB read voltage once and reading the LSB page once with the MSB read command, or changing the voltage level of the MSB read voltage two or more times. An LSB page may be read two or more times by the MSB read command.

Reading the MSB page with the MSB read command to generate MSB hard data; Reading the MSB page again with the MSB read command which changed the voltage level of the MSB read voltage to generate MSB soft data; Determining, using the MSB soft data, how much MSB data programmed in the MSB page is identical to the MSB hard data; And determining the read data of the MSB data by error correcting the MSB hard data according to a result of determining the same degree of the MSB data and the MSB hard data.

In the generating of the MSB soft data, the MSB read command whose voltage level of the MSB read voltage is changed may be transmitted from the controller of the flash memory device to the flash memory of the flash memory device.

The generating of the MSB soft data may include changing the voltage level of the MSB read voltage once and reading the MSB page once with the MSB read command, or changing the voltage level of the MSB read voltage two or more times. The MSB page can be read more than once with the MSB read command.

According to an aspect of the present invention, there is provided a flash memory system including: a flash memory in which memory cells of at least one or more pages are programmed with at least two bits of program data; And a controller configured to control reading of the program data programmed into the flash memory, wherein the controller generates a control signal corresponding to channel information of a channel connected to the flash memory or performance information of the flash memory system. A control signal generator; In response to the control signal, the first bit page to the flash memory such that hard data of the first bit page is generated at a first read voltage for a first bit page programmed with a first bit of each of the program data. Transmits a first read command for and changes a voltage level of a second read voltage for a second bit page programmed with a second bit of each of the program data to a second soft read voltage of the first bit page. A command controller which transmits a second read command for the second bit page to the flash memory so that first soft data is generated; And determining, according to the first soft data, a bit value of a first bit of each of the program data is equal to a bit value of a bit of the corresponding hard data, and determining the first bit of each of the program data. And an error correction decoder for performing error correction encoding on the bit value.

The command controller may be further configured to generate a second read command for the second bit page such that the second soft data of the first bit page is generated using the second soft read voltage having the voltage level of the second read voltage changed again. You can transfer more to flash memory.

The command control unit may be configured as a second soft read voltage that changes a voltage level of a third read voltage for a third bit page in which the third bit of each of the program data is programmed, and the second soft data of the first bit page may be changed. A third read command for the third bit page may be further sent to the flash memory to be generated.

The error correction decoder may determine how much the bit value of the first bit of each of the program data is equal to the bit value of the corresponding bit of the hard data according to the second soft data.

The command control unit transmits the second read command from the controller to the flash memory to generate hard data for the second bit page at the second read voltage, and changes the voltage level of the second read voltage. The second read command may be transmitted to the flash memory again so that the first soft data of the second bit page is generated using a second soft read voltage.

The error correction decoder may determine, according to the first soft data of the second bit page, a bit value of a bit of hard data for the second bit page to which a bit value of a second bit of each of the program data corresponds. It may be determined whether the degree is the same, and error correction encoding may be performed on the bit value of the second bit of each of the program data.

The channel information generator may generate the channel information based on a state of the channel or a decoding result of the error correction decoder.

The error correction decoder may correct the hard data as the read data according to a result of determining the same degree of the hard data and the first soft data.

The flash memory system may be included in a solid state drive.

According to the flash memory system and the read method in the flash memory system according to the embodiment of the present invention, the external memory of the flash memory system may not be required or the internal structure of the flash memory system may be added or the internal structure design may be changed. For example, a soft decision may be performed.

Therefore, according to the flash memory system and the read method in the flash memory system according to the embodiment of the present invention, it is possible to prevent a decrease in reliability of the read due to high integration.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.
1 is a block diagram illustrating a flash memory system according to an exemplary embodiment of the present invention.
2 is a flowchart illustrating a reading method in a flash memory system according to an exemplary embodiment of the present invention.
3A and 3B are diagrams illustrating a memory cell array of the flash memory of FIG. 1.
FIG. 4 is a diagram illustrating a distribution of memory cells of the flash memory of FIG. 1.
FIG. 5 is a diagram illustrating an LSB page and an MSB page in the 2-bit MLC of FIG. 4.
6 is a diagram illustrating an example in which the cell distribution of FIG. 5 is changed.
FIG. 7 is a diagram illustrating a method of generating hard data and first soft data of an LSB page by a reading method in a 2-bit multi-level cell flash memory according to an exemplary embodiment of the present invention.
8 is a flowchart illustrating a method of determining read data for a first bit page according to an embodiment of the present invention based on hard data and first soft data.
9 is a flowchart illustrating a reading method of a bit page after completion of a program according to an exemplary embodiment of the present invention.
10 and 11 are diagrams illustrating a method of generating hard data and first soft data of an MSB page by a read method in a 2-bit multi-level cell flash memory according to an embodiment of the present invention, respectively.
12 is a flash memory system including a 3-bit multi-level cell flash memory.
FIG. 13 is a diagram for describing an LSB page, a CSB page, and an MSB page of the flash memory of FIG. 12.
14 is a block diagram illustrating a flash memory system according to another exemplary embodiment of the present invention.
FIG. 15 is a flowchart illustrating a reading method of FIG. 14.
16 and 17 are diagrams for explaining an example of reading by the reading method of FIG. 15, respectively.
FIG. 18 is a flowchart illustrating a method of determining read data for a first bit page according to an embodiment of the present invention based on the hard data and the first soft data of FIG. 16.
19 is a block diagram illustrating a flash memory system according to another exemplary embodiment of the present invention.
20 is a flowchart illustrating a reading method in FIG. 19.
21 is a view for explaining an example of reading by the reading method of FIG. 20.
FIG. 22 is a flowchart for describing a method of generating a control signal of FIG. 1.
23 to 26 are each a block diagram illustrating a flash memory system according to another embodiment of the present invention.
27 is a block diagram illustrating a computing system device according to an exemplary embodiment of the present invention.
28 is a block diagram illustrating a memory card according to an embodiment of the present invention.
FIG. 29 illustrates a solid state drive (SSD) according to an embodiment of the present invention.
30 is a diagram illustrating a server system and a network system including an SSD.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art, and the following embodiments may be modified in various other forms, The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an," and "the" include plural forms unless the context clearly dictates otherwise. Also, as used herein, "comprise" and / or "comprising" specifies the presence of the mentioned shapes, numbers, steps, actions, members, elements and / or groups of these. It is not intended to exclude the presence or the addition of one or more other shapes, numbers, acts, members, elements and / or groups. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various elements, regions and / or regions, it should be understood that these elements, components, regions, layers and / Do. These terms are not intended to be in any particular order, up or down, or top-down, and are used only to distinguish one member, region or region from another member, region or region. Thus, the first member, region or region described below may refer to a second member, region or region without departing from the teachings of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing embodiments of the present invention. In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions illustrated herein, including, for example, variations in shape resulting from manufacturing.

1 is a block diagram illustrating a flash memory system according to an embodiment of the present invention, and FIG. 2 is a flowchart illustrating a read method in a flash memory system according to an embodiment of the present invention.

1 and 2, a flash memory system MSYS according to an embodiment of the present invention includes a flash memory MEM and a controller Ctrl. The read method may include transmitting a first read command RCMD1 from the controller Ctrl to the flash memory MEM so that the flash memory MEM generates the hard data HDTA for the first bit page (S220). And the first soft read voltage at which the voltage level of the second read voltage is changed from the controller Ctrl to the flash memory MEM so that the flash memory MEM generates the first soft data SDTA1 for the first bit page. In operation S240, the second read command RCMD2 is transmitted.

The flash memory MEM of the flash memory system MSYS according to the embodiment of the present invention may include a memory cell array MA having the structure shown in FIG. 3A. The memory cell array MA includes a (a is an integer of 2 or more) blocks BLK0 to BLKa-1, and each of the blocks BLK0 to BLKa-1 has b (b is an integer of 2 or more) pages. Fields PAG0 to PAGb-1, each of the pages PAG0 to PAGb-1 may include c (c is an integer of 2 or more) sectors SEC0 to SECC-1. In FIG. 3A, the pages PAG0 to PAGb-1 and the sectors SEC0 to SECC-1 are shown for the block BLK0 only for convenience of illustration, but the other blocks BLK1 to BLKa-1 also block BLK0. It may have the same structure as.

When the memory cell array MA according to the embodiment of the present invention is a memory cell array of a NAND flash memory, the blocks BLK0 to BLKa-1 of FIG. 3A may be the same as the example of FIG. 3B. It may be provided. Referring to FIG. 3B, each of the blocks BLK0 to BLKa-1 has a number of d (d is an integer of 2 or more) in which eight memory cells MCEL are connected in series in the bit lines BLO to BLD-1. It may be provided as a string (STR). Each string STR may also include a drain select transistor Str1 and a source select transistor Str2, which are connected to both ends of the memory cells MCEL connected in series, respectively.

The NAND flash memory device having the structure as shown in FIG. 3B is erased in units of blocks, and performs a program in units of pages PAG corresponding to each word line WL0 to WL7. 3B shows an example in which eight pages PAG for eight word lines WL0 to WL7 are provided in one block. However, the blocks BLK0 to BLKa-1 of the memory cell array MA according to the embodiment of the present invention may have a different number of memory cells than the number of memory cells MCEL and pages PAG shown in FIG. It may be provided with a page. In addition, the flash memory MEM of FIG. 1 may include a plurality of memory cell arrays that perform the same operation in the same structure as the memory cell array MA described above.

Each of the memory cells MCEL of the semiconductor memory device having the structure as shown in FIG. 3B may have a threshold voltage Vth included in one of the distributions as shown in FIG. 4 according to the number of bits of programmed program data. have. FIG. 4A illustrates a cell distribution in a single-level cell (SLC) flash memory in which memory cells MCELs are programmed with one bit, and FIG. 4B illustrates two memory cells MCELs each. 4 shows a cell spread in a 2-bit MLC (multi-level cell) flash memory programmed into bits, and FIG. 4C shows a cell spread in a 3-bit MLC flash memory in which memory cells MCEL are programmed to 3 bits, respectively. .

Each of the memory cells MCEL of the memory cell array MA of FIG. 3B is included in one of an erased state E and a program state P in the case of an SLC flash memory according to a value of programmed data. Has a threshold voltage, and in the case of a 2-bit MLC flash memory, has a threshold voltage included in one of an erased state E and one of the first program state P1 to the third program state P3, and a 3-bit MLC The flash memory has a threshold voltage included in one of an erased state E and one of a first program state P1 to a seventh program state P7.

However, the present invention is not limited thereto, and each of the memory cells MCEL of the memory cell array MA of FIG. 3B may be programmed with 4 bits or more. In addition, the flash memory MEM of FIG. 1 may include memory cells MCEL programmed with different numbers of bits.

Although FIG. 4A illustrates the SLC flash memory, the read method according to the embodiment of the present invention is a read method in the MLC flash memory. Accordingly, the flash memory MEM of FIG. 1 according to an embodiment of the present invention is an MLC flash memory. However, as described above, the flash memory MEM according to the embodiment of the present invention may include both SLC and MLC, or may include MLCs programmed with different numbers of bits.

Referring back to FIG. 1, the flash memory MEM receives the first read command RCMD1. The first read command RCMD1 is a command for identifying a bit value of a first bit of program data and includes information about an address for a first bit page and a first read voltage for a first bit page. The first read voltage according to an embodiment of the present invention described below is a first read voltage used for reading a first bit of program data during a program, and a read of the first bit of program data in a state in which the program is completed. It may be one of the first read voltages used. In this case, the first bit of the program data may be a Least Signification Bit (LSB). When the distinction between the two is required, the reference numeral of the first read voltage applied to the first bit page to read the first bit during the program is VIR1, and the first bit to read the first bit in the state where the program is completed. The first read voltage applied to the page is referred to as VR1 to distinguish the two.

In this case, the read performed during the program according to the embodiment of the present invention refers to the read performed on the bit page programmed for the bit before the last bit (MSB (Most Signification Bit)) during programming in multi-bit. For example, a read performed during a program in the same 2-bit multi-level cell flash memory will be described. In the 2-bit multi-level cell flash memory as shown in FIG. 4B, the first bit of the program data may be LSB.

Each memory cell of the first bit page during the program may have a threshold voltage of a state included in one of the states of FIG. 5A indicating a program state for the LSB (first bit). That is, as shown in FIG. 5A, the memory cells of the first page are erased or programmed into one of an erased state E and a program state P. FIG.

Whether the first bit of the program data is "0" or "1" is determined by the first read voltage VIR1 having the voltage level between the erased state E and the program state P of FIG. The read performed to identify is the read to the first page performed during the program according to the practice of the present invention.

On the other hand, the read performed when the program according to the embodiment of the present invention is completed means a read performed after programming to the last bit (MSB (Most Signification Bit)) during programming in a multi-bit. For example, in a 2-bit multi-level cell flash memory as shown in FIG. 4B, the first bit of program data may be LSB and the second bit (last bit) may be MSB of program data.

In this case, each of the memory cells in which the program is completed up to the second bit (the last bit) may have one of the states of FIG. 5B. That is, the memory cells may have a threshold voltage included in one of an erased state E, a first program state P1, a second program state P2, and a third program state P3.

In FIG. 5B, the first bit of the program data is read by the first read voltage VR1 having the voltage level between the first program state P1 and the second program state P2. The first bit of the program data programmed into the memory cells having the threshold voltage belonging to the erased state E of FIG. 5B and the first program state P1 by the first read voltage VR1 is “1”. A first bit of program data programmed into memory cells identified as ", and having threshold voltages belonging to the second program state P2 and the third program state P3 may be identified as" 0 ". That is, after the program according to the embodiment of the present invention is completed by the first read voltage VR1, the read of the first page is performed. First, a read method performed on a first bit page by a first read voltage VIR1 during a program according to an exemplary embodiment of the present invention will be described. Referring again to FIG. 3B, high integration and miniaturization have become an issue in the flash memory, and the distance between the memory cells MCEL of FIG. 3B is decreasing. Thus, a coupling phenomenon may occur between adjacently located memory cells in the same string or between adjacently located memory cells in the same page. Furthermore, due to performance degradation of the flash memory system, the cell spread of the LSB page of FIG. 5A may be changed as shown in FIG. 6A. In this case, during the program, a read margin that can distinguish the erased state E and the program state P by the first read voltage VIR1 may be reduced. If the read margin is reduced, an error may occur in the read performed during the program, in which the LSB value of the memory cell having the threshold voltage of the erased state E and the program state P adjacent to each other is incorrectly read.

Therefore, in the read performed during the program, the bit value of the first bit programmed in the first bit page may not be determined as the bit value read by the first read voltage VIR1. Hereinafter, an operation of determining a first bit value by correcting an error that may be included in first bit values output from a flash memory by a first read command for a first bit page in a flash memory system according to an exemplary embodiment of the present invention. It demonstrates. Hereinafter, the data output from the flash memory by the first read command for the first bit page will be referred to as hard data for the first bit page.

Referring back to FIG. 1, in response to the first read command RCMD1, the flash memory MEM outputs the hard data HDTA for the first bit page in response to the first read command RCMD1. The first read command RCMD1 is transmitted from the controller Ctrl. The controller Ctrl includes a command control unit CCON for transmitting a command such as the first read command RCMD1 to the flash memory MEM in order to read program data from the flash memory MEM. The controller Ctrl includes a control signal generation unit CSG and an error correction decoder EDEC together with the command control unit CCON.

The control signal generator CSG generates the control signal XCON corresponding to the channel information CInf of the channel CH connected to the flash memory MEM. The control signal XCON is transmitted to the command control unit CCON to provide a reference for controlling the reading of the flash memory MEM. The error correction decoder EDEC performs error correction encoding on the bit value of the first bit of each of the program data. The control signal generator CSG and the error correction decoder EDEC will be described in more detail later.

1, the command controller CCON transmits the first read command RCMD1 to the flash memory MEM to read the hard data HDTA of the first bit page, and then the first bit page. In order to read the first soft data SDTA1, the second read command RCMD2 having the changed voltage level of the second read voltage is transmitted to the flash memory MEM. However, the present invention is not limited thereto. According to the flash memory system and the method of reading the same according to the embodiment of the present invention, the first soft data SDTA1 is first read by the second read command RCMD2 and then the hard data is read by the first read command RCMD1. (HDTA) can be read later.

The second read command RCMD2 is a command for reading a second bit of program data. Referring to FIG. 5B, the 2-bit multi-level cell flash memory as shown in FIG. 4B is driven by the second read voltages VR21 and VR22 so that the flash memory MEM is the MSB of the memory cell. The value is identified as one of "1" and "0" according to the threshold voltage of the memory cell. The second read voltage VR21 may have a voltage level between the erased state E and the first program state P1. The second read voltage VR22 may have a voltage level between the second program state P2 and the third program state P3.

The command controller CCON according to an exemplary embodiment of the present invention changes the voltage level of the second read voltages VR21 and VR22 to the second read command RCMD2 used to read the second bit page, thereby changing the first bit. The first soft data SDTA1 of the page is transferred to the flash memory MEM. Hereinafter, generation of hard data and first soft data for a first bit page according to an embodiment of the present invention in a flash memory system including a 2-bit multi-level cell flash memory will be described in more detail.

FIG. 7 is a diagram illustrating a method of generating hard data and first soft data of an LSB page by a read method during a program in a 2-bit multi-level cell flash memory according to an exemplary embodiment of the present invention.

1 and 7, a flash memory system MSYS according to an embodiment of the present invention reads an LSB page during a program with an LSB read command to generate LSB hard data. The LSB page is the first bit page described above, and the LSB read command is the first read command RCMD1 described above. Also, the LSB hard data is hard data HDTA of the first bit page described above. In the following description, the LSB page, the LSB read command and the LSB hard data are referred to as hard data of the first bit page, the first read command, and the first bit page, respectively, for a consistent description of terms.

The flash memory MEM may generate hard data HDTA of the first bit page in response to the first read command. The bit value of the first bit of each memory cell of the first bit page during programming is sensed as "1" or "0" by the first read voltage VIR1. Therefore, the hard data HDTA of the first bit page is generated by a combination of sensed "1" or "0".

The flash memory system MSYS according to an embodiment of the present invention reads the first bit page with an MSB read command that has changed the voltage level of the MSB read voltage to generate LSB soft data. The MSB page may be the second bit page described above, and the MSB read command may be the second read command RCMD2 described above. In addition, the LSB soft data may be the first soft data SDTA1 of the first bit page during the program described above, and the MSB read voltage of the MSB read command is the second read voltage VR21 and VR22 of FIG. 5B. May be). Hereinafter, for consistent description of terms, the MLSB page, the MSB read command, the MSB read voltage and the LSB soft data are respectively referred to as a second bit page, a second read command, a second read voltage and a first soft data of the first bit page. It is described.

As described above, the second read voltage VR21 for reading the MSB page may have a voltage level between the erased state E and the first program state P1. The second read voltage VR22 may have a voltage level between the second program state P2 and the third program state P3.

However, in the flash memory system MSYS according to the embodiment of the present invention, the first soft read voltage of the second read command RCMD2 used to generate the first soft data SDTA1 of the first bit page during programming is The second read voltage is different from the second read voltage of the second read command RCMD2 for reading the second bit page. The command control unit CCON according to the embodiment of the present invention changes the voltage level as shown in FIG. 5B to a voltage level approximating the first read voltage VIR1 as shown in FIG. 7. VR22 'generates the first soft data SDTA1 of the first bit page during the program.

The voltage difference d1 between the first read voltage VIR1 and the first soft read voltage VR21 'and the voltage difference d2 between the first read voltage VIR1 and the first soft read voltage VR22' may be the same or different. have. That is, the number of the first soft read voltages VVR21 'and VR22' may be a multiple of 2n (n is a natural number) of the number of the first read voltages VIR1, and the 2n first soft read voltages VR21 'and VR22 are multiples. ') May change the voltage level to be symmetrical or asymmetrical to the first read voltage VIR1. Voltage differences d1 and d2 between the first read voltage VIR1 and the first soft read voltages VR21 'and VR22', and whether the voltage differences d1 and d2 are equal to each other are included in the control signal XCON. It may be set corresponding to (CInf). Detailed description thereof will be described later.

The threshold voltages of the memory cells of the first bit page during the program are sensed as "1" or "0" by the first soft read voltages VR21 'and VR22'. Accordingly, the first soft data SDTA1 of the first bit page during the program corresponds to “11”, “10”, “00” and “01” with respect to the threshold voltages of the periods 1 to 4 in FIG. 7, respectively. Is generated.

8 is a flowchart illustrating a method of determining read data for a first bit page according to an embodiment of the present invention based on hard data and first soft data.

Referring to FIGS. 1 and 8, the error correction decoder EDEC of FIG. 1 uses the first soft data SDTA1 generated as described above to determine the first bit of each program data of the first bit page during the program. The degree of equality between the bit value and the bit value of the bit of the hard data is determined (S820), and the error of the hard data HDTA of the first bit page is corrected according to the same degree to determine the value of the first bit of the program data. (S840).

In the above, the method of reading the first bit page during the program in the flash memory system MSYS according to the exemplary embodiment of the present invention has been described. The flash memory system MSYS according to an embodiment of the present invention generates hard data and first soft data only for a first bit page during a program, and based on this, an error of hard data of a first bit page during a program is detected. By correcting, a read on the first bit page during the program can be performed. However, this is a case of a 2 bit multi-level cell flash memory system.

That is, in a multi-level cell flash memory system of 3 bits or more according to an embodiment of the present invention, a second bit page during a program may also exist. In this case, a soft decision operation for the second bit page during the program, that is, the error of the hard data for the second bit page during the program is corrected by soft data for the second bit page during the program. An operation may be performed. However, hereinafter, for the convenience of explanation, the description of the soft decision operation on the second bit page or more in reading during the program will be omitted.

The flash memory system MSYS according to an embodiment of the present invention may not perform a soft decision operation on a bit page after program completion. That is, as described above, the soft decision operation can be performed only on the bit page during the program. For example, in a 2-bit multi-level cell flash memory, the first bit value is determined by the first read voltage VR1 as shown in FIG. 5B, and the second bit is determined by the second read voltages VR21 and VR22. The value can be determined.

On the other hand, the flash memory system MSYS according to the embodiment of the present invention may perform the soft decision operation on the bit page after the completion of the program separately or together with the soft decision operation on the bit page during the program. In this case, the soft decision operation may be performed only on the bit pages of the bit pages after the completion of the program. For example, in a 2-bit multi-level cell flash memory system, the soft decision operation may be performed only for the first bit page and not for the second bit page.

Hereinafter, various reading methods according to an embodiment of the present invention for a bit page after program completion will be described.

9 is a flowchart illustrating a reading method of a bit page after completion of a program according to an exemplary embodiment of the present invention. The soft decision operation for the first bit page after program completion according to an embodiment of the present invention has been described in FIG. In addition, the specific operation may include the first method during the program described in FIGS. 7 and 8, except that the hard data for the first bit page is read by the first read voltage VR1 of FIG. 5B. 9, the description of the soft decision operation on the second bit page after the completion of the program is omitted in FIG. 9 since the description on the first bit page after the completion of the program is omitted.

1 and 9, the command controller CCON of the controller Ctrl according to an embodiment of the present invention uses the flash memory MEM to read the hard data HDTA for the second bit page as the second read voltage. In operation S820, the second read command RCMD2 is transmitted to the flash memory MEM. The second read command RCMD2 is a command for identifying the bit value of the second bit of the program data. As described above, the second read command RCMD2 is applied to the second read voltage which is an address for the second bit page and a read voltage for the second bit page. Include information about In addition, as described above, in the 2-bit multi-level cell flash memory as shown in FIG. 4B, the second bit of the program data may be an MSB of the program data, and the second bit page may be an MSB page.

Referring to FIG. 5B, the flash memory MEM senses the erased state E as an MSB value of “1” by the second read voltage VR21, and the first program state P1 to the third. The program state P3 may be sensed as an MSB value of "0". The flash memory MEM senses the erased state E, the first program state P1, and the second program state P2 by the second read voltage VR22 to an MSB value of “1”. The program state P1 to the third program state P3 may be sensed as an MSB value of "0". The MSB values of these MSB pages are output as hard data HDTA of the MSB page.

However, due to high integration or performance deterioration of the flash memory system, the cell distribution of the MSB page of FIG. 5B is changed as shown in FIG. 6B, and the MSB value is changed by the second read voltages VR21 and VR22. The read margin can be reduced. When the read margin decreases, a memory having an erase voltage E and a first program state P1 having a threshold voltage in an adjacent region or a second program state P2 and a third program state P3 having a threshold voltage in an adjacent region An error may occur in which a cell's MSB value is read incorrectly.

Hereinafter, an operation of determining a second bit value by correcting an error that may be included in second bit values output from a flash memory by a second read command for a second bit page in a flash memory system according to an exemplary embodiment of the present invention. It demonstrates. In particular, the generation of hard data and first soft data for a second bit page according to an embodiment of the present invention in a flash memory system including a 2-bit multi-level cell flash memory will be described in more detail. In addition, data output for the second bit page by the second read command in which the voltage level is not changed is called hard data of the second bit page, and data for the second bit page in accordance with the second read command in which the voltage level is changed. Note that the output data is referred to as first soft data of the second bit page.

FIG. 10A is a diagram illustrating a method of generating hard data and first soft data of an LSB page by a read method after completion of a program in a 2-bit multi-level cell flash memory according to an embodiment of the present invention, and FIG. A diagram for describing a method of generating hard data and first soft data of an MSB page by a read method after completion of a program in a 2-bit multi-level cell flash memory according to an embodiment of the present invention.

1 and 10A, a flash memory system MSYS according to an exemplary embodiment of the present invention may determine a voltage level between a first program state P1 and a second program state P2 of FIG. 5B. With the first read voltage VR1 having, the read of the LSB page after the completion of the program can be performed. As described above, since the read operation of the first page (LSB page) after the completion of the program differs only from the read voltage level during the program of FIG. 7, a detailed description of FIG. 10A is omitted.

1 and 10B, a flash memory system MSYS according to an exemplary embodiment of the present invention reads a second bit page of program data, which is an MSB page after program completion, as a second read command RCMD2, which is an MSB read command. To generate MSB hard data. The MSB hard data is the hard data HDTA of the second bit page described above. In the following description, MSB hard data is referred to as hard data of a second bit page for a consistent description of terms.

The flash memory MEM may generate hard data HDTA of the second bit page in response to the second read command RCMD2. The bit value of each memory cell of the first bit page, that is, the bit value of the second bit of the program data is sensed as "1" or "0" by the second read voltages VR21 and VR22. In FIG. 10B, a bit value of a cell having a threshold voltage lower than the second read voltage VR21 is sensed as "1", and a bit value of a cell having a threshold voltage between the second read voltage VR21 and VR22 is sensed as "0". An example in which a bit value of a cell having a threshold voltage greater than the second read voltage VR22 is sensed as "1" is shown. When the hard data HDTA is generated using the bit values as described above, the flash memory MEM transmits the hard data HDTA for the second bit page to the controller Ctrl.

In addition, the flash memory system MSYS according to the embodiment of the present invention changes the voltage level of the second bit page and the second read voltages VR21 and VR22 so that the MSB soft data, that is, the first soft page of the second bit page, is changed. Generate the data SDTA1. As shown in FIG. 5B, the second read voltage VR21 for reading the MSB page may have a voltage level between the erased state E and the first program state P1. The second read voltage VR22 may have a voltage level between the second program state P2 and the third program state P3.

However, the second soft read voltage VR21 ′ of the second read command RCMD2 used to generate the first soft data SDTA1 of the second bit page in the flash memory system MSYS according to the embodiment of the present invention. VR22 ', VR21 ", and VR22" are different from the second read voltages VR21 and VR22 of the second read command RCMD2 for generating the hard data HDTA of the second bit page. The command control unit CCON according to an embodiment of the present invention may be configured to change the voltage level of the second read voltages VR21 and VR22 of FIG. 10B used to generate the hard data HDTA of the second bit page. The first soft data SDTA1 of the second bit page is generated using the read voltages VR21 ', VR22', VR21 ", and VR22".

The voltage difference d1 between the second read voltage VR21 and the second soft read voltage VR21 'and the voltage difference d2 between the second read voltage VR21 and the second soft read voltage VR22' may be the same or different. Similarly, the voltage difference d3 between the second read voltage VR22 and the second soft read voltage VR21 "and the voltage difference d4 between the second read voltage VR22 and the second soft read voltage VR22" may be the same or different. Furthermore, the voltage difference d1 and d2 between the second read voltage VR21 and the second soft read voltages VR21 'and VR22' and the voltage difference d3 between the second read voltage VR22 and the second soft read voltage VR21 "and VR22". d4) may be the same or different.

The threshold voltage of each memory cell of the second bit page is sensed as "1" or "0" by the second soft read voltages VR21 ', VR22', VR21 ", and VR22". Accordingly, the first soft data SDTA1 of the first bit page corresponds to "11", "10", "00", "01", "00", and "thresholds" for the threshold voltages of the periods 1 to 7 of FIG. 10 " and " 11 " The method of determining the bit value of each memory cell of the second bit page using the first soft data SDTA1 of the second bit page is the same as that of the first bit page described above, and thus a detailed description thereof is omitted. do.

FIG. 10B illustrates a second read voltage of an erased state of the second bit page and i (i of 2 ^j −1 and j of a natural number) program states for generating the first soft data SDTA1 of the second bit page. An example is shown in which the second soft read voltages VR21 ', VR22', VR21 ", and VR22" are read for all adjacent states identified by (VR21, VR22). Specifically, FIG. 10B illustrates the erase state E and the first program state P1 identified as the second read voltage VR21 and adjacent to each other in generating the first soft data SDTA1 for the second bit page. The threshold voltages of the memory cells are read again by the second soft read voltages VR21 'and VR22', and the second program state P2 and the third program state P3 identified as the second read voltage VR22 and adjacent to each other. The threshold voltage of the memory cell is again read out by the second soft read voltages VR21 "and VR22".

However, the present invention is not limited thereto. As illustrated in FIG. 11, in the erase state E and the first program state P1 identified as the second read voltage VR21 and adjacent to each other, the first soft data (the second soft read voltages VR21 ′ and VR22 ′) is used. While SDTA1) is generated, the second soft read voltage may not be applied to the second program state P2 and the third program state P3 identified as the second read voltage VR22 and adjacent to each other. As described above, according to the flash memory system MSYS according to the exemplary embodiment of the present invention, the first soft data is generated differently according to the change of each program state, so that a read operation optimized for the performance deterioration characteristic of the flash memory may be performed.

In addition, although FIG. 10B has been described with respect to the read operation for the second bit page after the completion of the program, the read of the second bit page during the program in the multi-level cell flash memory system of three or more bits according to an embodiment of the present invention. Of course, it can be applied to the operation. However, as described above, the voltage level of the second read voltage during the program and the voltage level of the second read voltage after the program completion of FIG. 10B will be different.

In the above description, a flash memory system and a reading method thereof according to an exemplary embodiment of the present invention have been described with reference to a 2-bit multi-level cell flash memory. However, the present invention is not limited thereto. Hereinafter, a method of reading in a flash memory system including a 3-bit multi-level cell flash memory will be described.

FIG. 12 is a diagram for describing a program process in a 3 bit multi-level cell flash memory, and FIG. 13 is a diagram illustrating a 3 bit multi-level cell flash memory system.

In a 3-bit multi-level cell flash memory system, first the first bit of program data is programmed into one of the erased state E and the program state P of FIG. At this time, during the program, the program state of the first bit page is read by the first read voltage VIR1. The first read voltage VIR1 of FIG. 12A may be the same as the first read voltage VIR1 described with reference to FIG. 5A.

It is programmed from the state of FIG. 12A to one of the erased state E of FIG. 12B and the first program state P1 to the first program state P1. At this time, during the program, the second bit of the program data is read out by the second read voltages VIR21 and VIR22 shown in Fig. 12B. As shown in FIG. 12A, the first read voltage VIR1 is distinguished from the first read voltage VR1 after the completion of the program of FIG. 10A to indicate that the read is performed during the program. The second read voltages VIR21 and VIR22 in (b) are also shown with different reference numerals than the second read voltages VR21 and VR22 in FIG. 10B.

Programmed from the state of FIG. 12A to the state of FIG. 12C, the program for the program data in the 3-bit multi-level cell flash memory system is completed. Each memory cell in the 3-bit multi-level cell flash memory system may belong to one of an erased state E and a first program state P1 to a seventh program state P7 of FIG. 12C. Can be. In this case, the first bit of the program data is identified by the first read voltage VR1 of FIG. 12C, and the second bit is identified by the second read voltages VR21 and VR22 of FIG. 12C. The third bit may be identified by the third read voltages VR31, VR32, VR33, and VR34.

The flash memory MEM is an erased state after completion of a program, a first program state and a first read voltage VR1 having a voltage level between the third and fourth program states of FIG. 12C. A first bit of program data programmed into a memory cell belonging to the second program state is identified as "1", and a first bit of program data programmed into memory cell belonging to the fourth to seventh program states is set to "0". ". Each of the flash memories MEM has a second read voltage VR21 having a voltage level between the first program state and the second program state of FIG. 12C, and between the fifth program state and the sixth program state. VR22) identifies the bit value of the second bit.

The third read voltages VR31, VR32, VR33, and VR34 of FIG. 12C indicate voltage levels between the erased state E and the first program state P1, the second program state P2, and the third program voltage P3. The voltage level between the program state P3, the voltage level between the fourth program state P4 and the fifth program state P5, and the voltage level between the sixth program state P6 and the seventh program state P7. It can be set to have. The flash memory MEM senses a third bit of program data having a threshold voltage smaller than the third read voltage VR31 as "1", and a third bit of program data having a threshold voltage between the third read voltages VR31 and VR32. Is sensed as "0", and the third bit of program data having a threshold voltage between the third read voltages VR32 and VR33 is "1". In addition, the flash memory MEM senses a third bit of the program data having a threshold voltage between the third read voltages VR33 and VR34 as "0", and the third bit of the program data having a threshold voltage greater than the third read voltage VR34. Three bits sense as "1".

For convenience of explanation, hereinafter, the description will not be made by dividing into embodiments during the program or after the program is completed. Nevertheless, as mentioned above, the difference during the program or after the program completion is in the difference of the read voltage level, and it is understood that the embodiments described below can be applied to any state during the program and after the program completion. .

The flash memory system MSYS of FIG. 13 may be implemented in the same manner as in FIG. 1. However, the command controller CCON of FIG. 13 further transmits the third read command RCMD3 to the flash memory MEM, and the flash memory MEM of FIG. 13 performs an operation according to the third read command RCMD3. do. If FIG. 13 is a 3-bit multi-level cell flash memory system MSYS, the flash memory system MSYS is the LSB page (first bit page) with the first soft read voltage that changed the voltage level of the second read voltage. First soft data may be generated. The flash memory system MSYS generates the first soft data of the CSB page (second bit page). As shown in FIG. 10B, the second read voltage VR21, which identifies the dispersion of the second bit page, is used. The second bit page may be read using the second soft read voltages VR21 'and VR22' which have changed the voltage level of the VR22. In addition, in programming the MSB page (third page), the flash memory system MSYS reads the third bit page with the third soft read voltages VR31 ', V32', V33 ', and V34'. First soft data SDTA1 for a 3 bit page may be generated.

In the above description, only the example in which one soft data is generated for one bit page is described. However, the present invention is not limited thereto. The flash memory system according to the embodiment of the present invention can improve the reliability of reading by generating two or more soft data for one bit page. 14 is a block diagram illustrating a flash memory system according to another exemplary embodiment. FIG. 15 is a flowchart illustrating a read method of FIG. 14. 16 is a view for explaining an example of reading by the reading method of FIG. 15.

14 to 16, in the flash memory system MSYS according to another exemplary embodiment of the present invention, the flash memory MEM stores the hard data HDTA for the first bit page in the same manner as the read method of FIG. 2. Transmitting a first read command RCMD1 from the controller Ctrl to the flash memory MEM to generate (S1520) and causing the flash memory MEM to generate the first soft data SDTA1 for the first bit page. And transmitting a second read command RCMD2 in which the voltage level of the second read voltage is changed to the second soft read voltage from the controller Ctrl to the flash memory MEM (S1540).

Further, according to the read method of FIG. 15 in the flash memory system MSYS of FIG. 14, the voltage level of the second read voltages VR21 and VR22 is changed to the third soft read voltages VR21 "and VR22". In operation S1560, the second read command RCMD2 is again transmitted to the flash memory MEM so that the second soft data SDTA2 of the first bit page is generated. That is, according to another embodiment of the present invention, the hard data HDTA is generated with one first read command RCMD1 with respect to the first bit page, and the first soft data with two second read commands RCMD2, respectively. Data SDTA1 and second soft data SDTA2 are generated.

The flash memory MEM stores each memory cell of the first bit page as "1" or by the soft read voltages VR21 ', VR22', VR21 ", and VR22" whose voltage levels are changed twice. Sense as "0". Accordingly, the second soft data SDTA2 of the first bit page may be “111”, “101”, “100”, “000”, “001”, and “) for the threshold voltages of the periods 1 to 6 of FIG. 16, respectively. Generated to correspond to 011 ".

In FIG. 16, the first soft data SDTA1 of the first bit page is generated by the second soft read voltages VR21 ′ and VR22 ′ in which the voltage level is changed first, and the third soft in which the voltage level is changed second. An example in which the second soft data SDTA2 of the first bit page is generated by the read voltages VR21 "and VR22" is shown. However, the present invention is not limited thereto. As shown in FIG. 17, second soft data SDTA2 of the first bit page is generated by second soft read voltages VR21 ′ and VR22 ′ in which the voltage level is changed first, and secondly, the voltage level. The first soft data SDTA1 of the first bit page may be generated by the changed third soft read voltages VR21 ″ and VR22 ″.

FIG. 18 is a flowchart illustrating a method of determining read data for a first bit page according to an embodiment of the present invention based on the hard data and the first soft data of FIG. 16.

14 and 18, the error correction decoder EDEC of FIG. 14 uses a bit value of a first bit of each program data of a first bit page using the second soft data SDTA2 generated as described above. The degree of identity of the bit values of the bits of the hard data is determined (S1820), and the error of the hard data HDTA of the first bit page is corrected according to the same degree to determine the value of the first bit of the program data (S1840). ).

In the above, the example of generating the first soft data and the second soft data of the first bit page by the second soft read voltage having the voltage level of the second read voltage of the second read command changed twice. . Similarly, the second bit page or the third bit page may generate the first soft data and the second soft data. For example, after generating the first soft data SDTA1 for the MSB page as shown in FIG. 9, the second soft data for the MSB page may be generated by changing the voltage level of the second read voltage again. Therefore, a detailed description thereof will be omitted.

According to another exemplary embodiment of the present invention, a plurality of soft data for the corresponding page may be generated by changing a plurality of voltage levels of the read voltage. For example, after generating the second soft data SDTA2 for the first bit page as shown in FIG. 18, the third soft data may be generated by changing the voltage level of the second read voltage again.

Furthermore, according to another embodiment of the present invention, the hard data HDTA, the first soft data SDTA1 and the second soft data SDTA2 may be generated by different read commands. This will be described.

FIG. 19 is a block diagram illustrating a flash memory system according to another exemplary embodiment. FIG. 20 is a flowchart illustrating a read method of FIG. 19. 21 is a diagram for describing an example of reading by the reading method of FIG. 20.

19 to 21, in the flash memory system MSYS according to another embodiment of the present invention, the flash memory MEM stores the hard data HDTA for the first bit page in the same manner as the read method of FIG. 15. Transmitting the first read command RCMD1 from the controller Ctrl to the flash memory MEM to generate (S2120) and the flash memory MEM to generate the first soft data SDTA1 for the first bit page. And transmitting a second read command RCMD2 from which the voltage level of the second read voltage is changed to the first soft read voltages VR21 'and VR22' from the controller Ctrl to the flash memory MEM (S2040). do.

Furthermore, according to the reading method of FIG. 20 in the flash memory system MSYS of FIG. 19, the second voltage obtained by changing the voltage levels of the third read voltages VR31, VR32, VR33, and VR34 as shown in FIG. 12C. The third read command RCMD3 is again transmitted to the flash memory MEM so that the second soft data SDTA2 of the first bit page is generated using the soft read voltages VR31 ', VR32', VR33 ', and VR34'. Step S2060 is further provided. That is, according to another embodiment of the present invention, the hard data HDTA is generated with one first read command RCMD1 for the first bit page, and the first soft data with one second read command RCMD2. SDTA1 is generated, and the second soft data SDTA2 is generated with one third read command RCMD3.

The flash memory MEM senses each memory cell of the first bit page as "1" or "0" by the first soft read voltages VR21 'and VR22', and thus, the first soft data SDTA1. ) The flash memory MEM sets each memory cell of the first bit page to "1" or "0" by the second soft read voltages VR31 ', VR32', VR33 ', and VR34'. After sensing, the second soft data SDTA2 is generated. The hard data HDTA, the first soft data SDTA1, and the second soft data SDTA2 of the first bit page are respectively " 111 ", " 110 ", " 100 "," 101 "," 001 "," 000 "," 010 "and" 011 ".

Determination of the read data by examining the identity of the hard data HDTA and the second soft data SDTA2 generated as shown in FIG. 21 is the same as the method of FIG. 18, and thus a detailed description thereof will be omitted. The generation of soft data for the other pages of the flash memory of FIG. 19 may be generated by the various methods described above.

1 or 14, the control signal XCON for controlling the generation of the first soft data SDTA1 or the second soft data SDTA2 in the flash memory system MSYS according to the embodiment of the present invention may be described as follows. As described above, the control signal generation unit CSG is generated based on the channel information CInf of the state of the channel CH. For example, the control signal generation unit CSG generates only the first soft data SDTA1 or even the second soft data SDTA2 based on the channel information CInf to further improve the reliability of the readout. It may be determined and reflected in the control signal XCON. Alternatively, the control signal generator CSG may determine which of the read methods of the above-described read method of FIGS. 10 and 11 to perform the read based on the channel information CInf and reflect the result in the control signal XCON. have.

The channel information CInf may be information about an operating temperature of the flash memory, noise information, error occurrence information, a program number for the memory cell, a storage time of the program data, and the like. In the read method of the flash memory system MSYS according to the exemplary embodiment of the present invention, in order to generate the control signal XCON based on the channel information CInf as described above, channel information is detected as shown in FIG. 22. In operation S2220 and determining channel information, determining whether to generate first soft data generated by reading the first bit page using the first soft read voltage may be performed (S2240).

The flash memory system MSYS according to the embodiment of the present invention may further include a channel detector CDEC as shown in FIG. 23 to detect channel information CInf as shown in S2320 of FIG. 22. The channel detector CDEC may be connected to the channel CH to detect channel information CInf and transmit the detected channel information CInf to the error correction decoder EDEC and the control signal generator CSG.

The error correction decoder EDEC may perform an error correction operation with a factor corresponding to the channel information CInf transmitted from the channel detector CDEC. In this case, the error correction decoder EDEC may transmit the decoding information DInf regarding the result of decoding by reflecting the channel information CInf to the control signal generator CSG. The control signal generator CSG may generate the control signal XCON by reflecting the channel information CInf or the decoding information DInf.

However, the present invention is not limited thereto. As shown in FIG. 24, the channel information CInf according to the exemplary embodiment of the present invention may be detected outside the flash memory system MSYS and transmitted to the control signal generator CSG. Although not shown in FIG. 24, the channel information CInf transmitted from the outside to the control signal generator CSG may also be transmitted to the error correction decoder EDEC. In this case, as described above, the error correction decoder EDEC may transmit the decoded information DInf of the decoded result by reflecting the channel information CInf to the control signal generator CSG. The CSG may generate the control signal XCON by reflecting the channel information CInf or the decoding information DInf.

In the above description, only the example in which the flash memory system MSYS generates the control signal XCON based on the channel information CInf has been described. However, the present invention is not limited thereto. According to another embodiment of the present disclosure, the flash memory system MSYS of FIG. 25 may generate a control signal XCON in response to the performance information PInf of the flash memory system MSYS. The performance information PInf of the flash memory system MSYS may be information on the degree of integration or performance degradation of the flash memory MEM. The performance information PInf may be transmitted from the outside as shown in FIG. 25. Alternatively, although not illustrated in FIG. 25, the performance information PInf may be stored in a control signal generation unit CSG or a register (not shown) of the controller Ctrl.

26 is a block diagram illustrating a flash memory system according to another example embodiment.

Referring to FIG. 26, the flash memory system MSYS of FIG. 26 may further include a read buffer RBUF buffering the hard data HDTA and the first soft data SDTA1 transmitted from the flash memory MEM. The read buffer RBUF receives the hard data HDTA and the first soft data SDTA1 after a predetermined time has elapsed after receiving the hard data HDTA and the first soft data SDTA1 from the flash memory MEM. It can be transmitted to the channel detection unit (CDEC). However, the read buffer RBUF uses the hard data HDTA and the first soft data SDTA1 as the error correction decoder EDEC in the flash memory system MSYS in which the channel detector CDEC is not provided as shown in FIG. 26. You can also send.

27 is a block diagram illustrating a computing system device according to an exemplary embodiment of the present invention.

The computing system CSYS according to an embodiment of the present invention includes a processor (CPU), a user interface (UI), and a flash memory system (MSYS) electrically connected to a bus (BUS). The flash memory system MSYS includes a memory controller Ctrl and a flash memory MEM. In the flash memory MEM, N-bit data (N is an integer of 1 or larger) to be processed or to be processed by the processor CPU will be stored through the memory controller Ctrl. The flash memory system MSYS of FIG. 27 may be the same as the flash memory system MSYS of FIG. 1. Therefore, according to the computing system CSYS, the reliability of the read of the flash memory system MSYS can be improved by simple control without the addition of additional modules or the like.

The computing system CSYS according to an embodiment of the present invention may further include a power supply device PS. In addition, when the flash memory MEM is a flash memory device that executes a program by the program method of FIG. It can be provided.

When the computing system CSYS according to the embodiment of the present invention is a mobile device, a modem such as a battery and a baseband chipset for supplying an operating voltage of the computing system may be additionally provided. In addition, it is common knowledge in the art that an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further provided in the computing system CSYS according to the embodiment of the present invention. This is obvious to those who have learned, so a detailed description is omitted.

28 is a block diagram illustrating a memory card according to an embodiment of the present invention.

Referring to FIG. 28, a memory card MCRD according to an embodiment of the present invention includes a memory controller Ctrl and a flash memory MEM. The memory controller Ctrl controls data writing to or reading data from the flash memory MEM in response to a request from an external host (not shown) received through the input / output means I / O. . Also, the memory controller Ctrl controls the erase operation on the flash memory MEM. The memory controller Ctrl of the memory card MCRD according to an exemplary embodiment of the present invention may include interface units (not shown) and RAM (not shown) for performing an interface with a host and a memory device, respectively, in order to perform the above control operations. RAM) and the like. The memory card MCRD according to the embodiment of the present invention may be implemented with the flash memory system MSYS of FIG. 1.

The memory card MCRD of FIG. 28 is a compact flash card (CFC: Compact Flash Card), a microdrive (Microdrive), a smart media card (SMC: Smart Media Card), a multimedia card (MMC: Multimedia Card), a secure digital card (SDC). It may be implemented as a security digital card, a memory stick, or a USB flash memory driver. Therefore, according to the memory card MCRD of FIG. 28, the reliability of reading out of the flash memory system MSYS can be improved by simple control without the addition of additional modules or the like.

29 illustrates a solid state drive (SSD) according to an embodiment of the present invention.

Referring to FIG. 29, an SSD according to an embodiment of the present invention includes an SSD controller SCTL and a flash memory MEM. The SSD controller SCTL may include a processor PROS, a RAM, a cache buffer CBUF, and a memory controller Ctrl connected to a bus BUS. The processor PROS controls the memory controller Ctrl to exchange data with the flash memory MEM in response to a request (command, address, data) of the host (not shown). The processor PROS and the memory controller Ctrl of the SSD according to the embodiment of the present invention may be implemented as one ARM processor. Data necessary for the operation of the processor PROS may be loaded into the RAM.

The host interface HOST I / F receives a request from the host and transmits the request to the processor PROS or transmits data transmitted from the flash memory MEM to the host. Host interfaces (HOST I / F) include Universal Serial Bus (USB), Man Machine Communication (MMC), Peripheral Component Interconnect-Express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Various interface protocols, such as Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), and Intelligent Drive Electronics (IDE), can interface with the host. Data to be transferred to the flash memory MEM or data transferred from the flash memory MEM may be temporarily stored in the cache buffer CBUF. The cache buffer CBUF may be an SRAM or the like.

The SSD according to the embodiment of the present invention may be implemented by the flash memory system MSYS of FIG. 1. Therefore, according to the SSD of FIG. 29, the reliability of reading the flash memory system MSYS can be improved by simple control without the addition of additional modules or the like.

30 is a diagram illustrating a server system and a network system including an SSD.

Referring to FIG. 30, a network system NSYS according to an embodiment of the present invention may include a server system SSYS and a plurality of terminals TEM1 to TEMn connected through a network. The server system SSYS according to an embodiment of the present invention responds to a request received from a server SERVER and terminals TEM1 to TEMn processing a request received from a plurality of terminals TEM1 to TEMn connected to a network. And an SSD for storing corresponding data. In this case, the SSD of FIG. 30 may be the SSD of FIG. 29. That is, the SSD of FIG. 30 may include an SSD controller SCTL and a flash memory MEM, and the flash memory MEM may be a flash memory device that performs a program by the program method of FIG. 1.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms are employed herein, they are used for purposes of describing the present invention only and are not used to limit the scope of the present invention.

For example, a method of generating first soft data or second soft data for a first bit page and a first soft data or second soft for a second bit page in a flash memory system according to another embodiment of the present invention. The method of generating the data may be different. In addition, the above-described method of generating the first soft data or the second soft data of each bit page may be applied to a flash memory system including memory cells programmed with four or more bits of program data. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims

A read method in a flash memory system having a flash memory including memory cells programmed with at least two bits of program data and a controller for controlling the flash memory.
A first read for the first bit page from the controller to the flash memory such that hard data of the first bit page is generated with a first read voltage for the first bit page programmed with the first bit of each of the program data. 1 transmitting a read command; And
The first soft data of the first bit page is generated with a first soft read voltage having a voltage level of a second read voltage for a second bit page programmed with a second bit of each of the program data. And sending a second read command for a two bit page from the controller to the flash memory.

The method of claim 1, wherein the first read voltage,
And a read voltage for the first bit page during program execution before the program for the MSB (Most Signification Bit) of the program data is completed.

The method according to claim 1,
The first read command is a read command that reads an LSB page for a LSB (Least Signification Bit) of each of the program data.
And the second read command is a read command for reading an MSB page for an MSB of each of the program data.

The method according to claim 1,
The first read command is a read command for reading an LSB page for each LSB of the program data, and the second read command is a read command for reading a CSB page for each CSB of the program data,
The first read command is a command for reading a CSB page for each CSB of the program data, and the second read command is a command for reading an MSB page for an MSB of each of the program data. How to read.

The method according to claim 1,
Retransmitting the second read command to the flash memory such that the second soft data of the first bit page is generated with a second soft read voltage that has changed the voltage level of the second read voltage again. Read method, characterized in that.

The method according to claim 1,
The second soft data of the first bit page is generated with a second soft read voltage having a voltage level of a third read voltage for a third bit page programmed with a third bit of each of the program data. And sending a third read command for a three bit page from the controller to the flash memory.

The method of claim 1, wherein the voltage level of the first soft read voltage is
And a reading of 2n (n is a natural number) multiple of the first read voltage and symmetrical or asymmetrical with respect to the first read voltage.

The method of claim 1, wherein the reading method is
And a soft decision signal including at least one of channel information on a channel state between the controller and the flash memory and performance information on the performance of the flash memory system.

The method according to claim 1,
Transmitting the second read command from the controller to the flash memory such that hard data for the second bit page is generated at the second read voltage; And
Retransmitting the second read command from the controller to the flash memory such that the first soft data of the second bit page is generated with a second soft read voltage that has changed the voltage level of the second read voltage. Read method, characterized in that.

The method according to claim 1,
And determining read data by error correcting the hard data according to a result of determining the same degree of the hard data and the first soft data.

A flash memory in which each of the at least one page of memory cells is programmed with at least two bits of program data; And
A flash memory system comprising a controller for controlling reading of the program data programmed into the flash memory.
The controller,
A control signal generator configured to generate a control signal corresponding to channel information of a channel connected to the flash memory or performance information of the flash memory system;
In response to the control signal, the first bit page to the flash memory such that hard data of the first bit page is generated at a first read voltage for a first bit page programmed with a first bit of each of the program data. Transmits a first read command for and changes a voltage level of a second read voltage for a second bit page programmed with a second bit of each of the program data to a second soft read voltage of the first bit page. A command controller which transmits a second read command for the second bit page to the flash memory so that first soft data is generated; And
According to the first soft data, it is determined whether or not the bit value of the first bit of each of the program data is equal to the bit value of the bit of the corresponding hard data to determine the bit value of the first bit of each of the program data. And an error correction decoder for performing error correction encoding on the value.